From 3ec10b734d40cd087573e9e50243002501fd4f78 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 31 Jan 2012 16:47:55 +0100 Subject: [PATCH] --- yaml --- r: 293568 b: refs/heads/master c: 11782b0233c06a35776786f30e19dc4168eb5406 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem.c | 5 ++++- trunk/drivers/gpu/drm/i915/intel_display.c | 6 ------ 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 9ca3d8acaafb..1737dbfb3e55 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f691e2f4cec334e906f971471b3bf1460c6256d4 +refs/heads/master: 11782b0233c06a35776786f30e19dc4168eb5406 diff --git a/trunk/drivers/gpu/drm/i915/i915_gem.c b/trunk/drivers/gpu/drm/i915/i915_gem.c index 86fffd26a894..27fe07a2fd33 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem.c @@ -3685,13 +3685,16 @@ void i915_gem_init_swizzling(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6 || + if (INTEL_INFO(dev)->gen < 5 || dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_TILE_SURFACE_SWIZZLING); + if (IS_GEN5(dev)) + return; + I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); if (IS_GEN6(dev)) I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index fc9bc19f6db9..5ab967ce86cc 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -6029,12 +6029,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev, pipe); - if (IS_GEN5(dev)) { - /* enable address swizzle for tiling buffer */ - temp = I915_READ(DISP_ARB_CTL); - I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); - } - I915_WRITE(DSPCNTR(plane), dspcntr); POSTING_READ(DSPCNTR(plane));