From 3ed68eaa342025af4054c90f52ca5994cac4c3e6 Mon Sep 17 00:00:00 2001 From: David Miller Date: Tue, 12 Aug 2008 15:08:51 -0700 Subject: [PATCH] --- yaml --- r: 108250 b: refs/heads/master c: 969830b2fedf8336c41d6195f49d250b1e166ff8 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/video/aty/radeon_accel.c | 8 ++++++++ trunk/include/video/radeon.h | 4 ++++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 5cde265bc829..82640f31e230 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2b26736c88db85c038e04c2306d0745553e69602 +refs/heads/master: 969830b2fedf8336c41d6195f49d250b1e166ff8 diff --git a/trunk/drivers/video/aty/radeon_accel.c b/trunk/drivers/video/aty/radeon_accel.c index 4d13f68436e6..aa95f8350242 100644 --- a/trunk/drivers/video/aty/radeon_accel.c +++ b/trunk/drivers/video/aty/radeon_accel.c @@ -55,6 +55,10 @@ static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, OUTREG(DP_WRITE_MSK, 0xffffffff); OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); + radeon_fifo_wait(2); + OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); + OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); + radeon_fifo_wait(2); OUTREG(DST_Y_X, (region->dy << 16) | region->dx); OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); @@ -116,6 +120,10 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo, OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); + radeon_fifo_wait(2); + OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); + OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); + radeon_fifo_wait(3); OUTREG(SRC_Y_X, (sy << 16) | sx); OUTREG(DST_Y_X, (dy << 16) | dx); diff --git a/trunk/include/video/radeon.h b/trunk/include/video/radeon.h index 95a1f2038b1d..099ffa5e5bee 100644 --- a/trunk/include/video/radeon.h +++ b/trunk/include/video/radeon.h @@ -742,6 +742,10 @@ #define SOFT_RESET_RB (1 << 6) #define SOFT_RESET_HDP (1 << 7) +/* WAIT_UNTIL bit constants */ +#define WAIT_DMA_GUI_IDLE (1 << 9) +#define WAIT_2D_IDLECLEAN (1 << 16) + /* SURFACE_CNTL bit consants */ #define SURF_TRANSLATION_DIS (1 << 8) #define NONSURF_AP0_SWP_16BPP (1 << 20)