From 3edf6dbdc547032e70aed3f8d5fa136cad8e0a6c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 22 Apr 2008 10:46:42 +1000 Subject: [PATCH] --- yaml --- r: 93105 b: refs/heads/master c: afd1dee896e8b1cbd24258ac673aeccd803ff582 h: refs/heads/master i: 93103: 910bb7146fa0ee403487d5063cbcc6e2a3df8f02 v: v3 --- [refs] | 2 +- trunk/drivers/net/ibm_newemac/mal.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index f93ad792d535..9ed2628e1568 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f34ebab68a8e3c80ff4364f4c61734faec5161d4 +refs/heads/master: afd1dee896e8b1cbd24258ac673aeccd803ff582 diff --git a/trunk/drivers/net/ibm_newemac/mal.c b/trunk/drivers/net/ibm_newemac/mal.c index 6869f08c9dcb..fb9c9eb114f4 100644 --- a/trunk/drivers/net/ibm_newemac/mal.c +++ b/trunk/drivers/net/ibm_newemac/mal.c @@ -136,6 +136,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel) { unsigned long flags; + /* + * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple + * of 8, but enabling in MAL_RXCASR needs the divided by 8 value + * for the bitmask + */ + if (!(channel % 8)) + channel >>= 3; + spin_lock_irqsave(&mal->lock, flags); MAL_DBG(mal, "enable_rx(%d)" NL, channel); @@ -148,6 +156,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel) void mal_disable_rx_channel(struct mal_instance *mal, int channel) { + /* + * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple + * of 8, but enabling in MAL_RXCASR needs the divided by 8 value + * for the bitmask + */ + if (!(channel % 8)) + channel >>= 3; + set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); MAL_DBG(mal, "disable_rx(%d)" NL, channel);