From 3ef380e5d2e6103a1965c0c232f97dd19e6304fa Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 26 Aug 2011 22:44:59 +0100 Subject: [PATCH] --- yaml --- r: 263594 b: refs/heads/master c: 25904157168ddc8841748a729914f00e53d7e049 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/proc-v7.S | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 6b438ca90ff4..d542b42e0b08 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f35235a315a167e38e8e5bc9e476dcd7c932612c +refs/heads/master: 25904157168ddc8841748a729914f00e53d7e049 diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index a773f4e2869c..9049c0764db2 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -248,7 +248,9 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register + teq r4, r10 @ Is it already set? + mcrne p15, 0, r10, c1, c0, 1 @ No, so write it mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR