From 3f8f13819d3f891dcaded98ef83fe3e34d41a1b8 Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Thu, 30 Apr 2009 17:06:09 +0100
Subject: [PATCH] --- yaml --- r: 144527 b: refs/heads/master c:
 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 h: refs/heads/master i:   144525:
 d99783c0d39d2d85edd301a2f7816b9c1123101d   144523:
 1b8d0e219fe36892c9fa65929a08682ea5e45801   144519:
 806768346bd4ee67f43d63188bbcb58612d25f46   144511:
 cd2d8bf02527805e7bba7d680577d9e63d023191 v: v3

---
 [refs]                      |  2 +-
 trunk/arch/arm/Kconfig      | 16 ++++++++++++++++
 trunk/arch/arm/mm/proc-v7.S |  8 ++++++++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 9c116cc601c4..5eba34eb076f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f
+refs/heads/master: 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47
diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig
index e28a76bd1793..84e4816362b3 100644
--- a/trunk/arch/arm/Kconfig
+++ b/trunk/arch/arm/Kconfig
@@ -749,6 +749,22 @@ config ARM_ERRATA_411920
 	  It does not affect the MPCore. This option enables the ARM Ltd.
 	  recommended workaround.
 
+config ARM_ERRATA_430973
+	bool "ARM errata: Stale prediction on replaced interworking branch"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 430973 Cortex-A8
+	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
+	  interworking branch is replaced with another code sequence at the
+	  same virtual address, whether due to self-modifying code or virtual
+	  to physical address re-mapping, Cortex-A8 does not recover from the
+	  stale interworking branch prediction. This results in Cortex-A8
+	  executing the new code sequence in the incorrect ARM or Thumb state.
+	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
+	  and also flushes the branch target cache at every context switch.
+	  Note that setting specific bits in the ACTLR register may not be
+	  available in non-secure mode.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S
index d1ebec42521d..fc81159596fe 100644
--- a/trunk/arch/arm/mm/proc-v7.S
+++ b/trunk/arch/arm/mm/proc-v7.S
@@ -95,6 +95,9 @@ ENTRY(cpu_v7_switch_mm)
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
 	orr	r0, r0, #TTB_FLAGS
+#ifdef CONFIG_ARM_ERRATA_430973
+	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
+#endif
 	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
 	isb
 1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -180,6 +183,11 @@ __v7_setup:
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
 	bl	v7_flush_dcache_all
 	ldmia	r12, {r0-r5, r7, r9, r11, lr}
+#ifdef CONFIG_ARM_ERRATA_430973
+	mrc	p15, 0, r10, c1, c0, 1		@ read aux control register
+	orr	r10, r10, #(1 << 6)		@ set IBE to 1
+	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register
+#endif
 	mov	r10, #0
 #ifdef HARVARD_CACHE
 	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate