From 3f91647367d695863138d37a78d22cbb3c8192da Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Wed, 25 Jan 2012 11:54:22 +0100
Subject: [PATCH] --- yaml --- r: 287197 b: refs/heads/master c:
 6d3ec1ae6cdcda185bd9452b2daed5145e2493a5 h: refs/heads/master i:   287195:
 b4b441a6f77fda6ff261b04ec71c3759aa91850a v: v3

---
 [refs]                           |  2 +-
 trunk/arch/arm/include/asm/tlb.h | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index ec8de0405d44..9efe12399501 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 91756acb58b17aee68d055fc15b1e2550ff00801
+refs/heads/master: 6d3ec1ae6cdcda185bd9452b2daed5145e2493a5
diff --git a/trunk/arch/arm/include/asm/tlb.h b/trunk/arch/arm/include/asm/tlb.h
index 5d3ed7e38561..314d4664eae7 100644
--- a/trunk/arch/arm/include/asm/tlb.h
+++ b/trunk/arch/arm/include/asm/tlb.h
@@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 	unsigned long addr)
 {
 	pgtable_page_dtor(pte);
-	tlb_add_flush(tlb, addr);
+
+	/*
+	 * With the classic ARM MMU, a pte page has two corresponding pmd
+	 * entries, each covering 1MB.
+	 */
+	addr &= PMD_MASK;
+	tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
+	tlb_add_flush(tlb, addr + SZ_1M);
+
 	tlb_remove_page(tlb, pte);
 }