From 3ff21faa32600289422aae1af6285ae142e5713d Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 6 Sep 2012 15:45:22 +0300 Subject: [PATCH] --- yaml --- r: 325723 b: refs/heads/master c: a0f38b87de1df05acf2e3cc23ee2f02a18d80c85 h: refs/heads/master i: 325721: a23370c8b4910d2c122226b31799b349e365961e 325719: a1251b9c3770d0d12ba1919803e920bb2997bc61 v: v3 --- [refs] | 2 +- trunk/include/linux/serial_reg.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e243412a8390..74c452820a17 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 494574304711a333386e7dd5fd3ebbc3b7024994 +refs/heads/master: a0f38b87de1df05acf2e3cc23ee2f02a18d80c85 diff --git a/trunk/include/linux/serial_reg.h b/trunk/include/linux/serial_reg.h index 8ce70d76f836..5ed325e88a81 100644 --- a/trunk/include/linux/serial_reg.h +++ b/trunk/include/linux/serial_reg.h @@ -40,6 +40,10 @@ #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ +#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ +#define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ +#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ + #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */