From 40b41663b11443c2202cf53648e27f649b346462 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 6 Jan 2011 21:19:16 -0500
Subject: [PATCH] --- yaml --- r: 228863 b: refs/heads/master c:
 a572eaa3726968555451ba301ff8c61e90e8c278 h: refs/heads/master i:   228861:
 2b7d72e9fe226f7068904885429880f4acd71134   228859:
 7110ed1963c5369c62ee56b053fe21c103af9b40   228855:
 5e5e66d680d74a2d59fe5a3018b7ea6365397855   228847:
 02d954c89347cfebb027b7447f37843535713292   228831:
 8b077f39102a15266d9185d7a26d4af676177ac0   228799:
 e48b784c03038b526f69bf7e2ddca65a4297b974   228735:
 224f15a7f402aaa96421cf33758a0b760e2a55df   228607:
 a77bbaa93009277b92d4b3866a6f1c2853918c88   228351:
 89afbffab92f4e63674e117fecc1c12bba3127fd v: v3

---
 [refs]                                       |  2 +-
 trunk/drivers/gpu/drm/radeon/atombios_crtc.c | 26 +++++++++++++++++++-
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 6ab8f23a6b94..36589406489f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f82b3ddc5fac044a28ab841bfd4ae48e2e43a21b
+refs/heads/master: a572eaa3726968555451ba301ff8c61e90e8c278
diff --git a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
index b3e5e7549008..b0ab185b86f6 100644
--- a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -403,6 +403,7 @@ union atom_enable_ss {
 	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 };
 
 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
@@ -417,7 +418,30 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
 
 	memset(&args, 0, sizeof(args));
 
-	if (ASIC_IS_DCE4(rdev)) {
+	if (ASIC_IS_DCE5(rdev)) {
+		args.v3.usSpreadSpectrumAmountFrac = 0;
+		args.v3.ucSpreadSpectrumType = ss->type;
+		switch (pll_id) {
+		case ATOM_PPLL1:
+			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
+			args.v3.usSpreadSpectrumAmount = ss->amount;
+			args.v3.usSpreadSpectrumStep = ss->step;
+			break;
+		case ATOM_PPLL2:
+			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
+			args.v3.usSpreadSpectrumAmount = ss->amount;
+			args.v3.usSpreadSpectrumStep = ss->step;
+			break;
+		case ATOM_DCPLL:
+			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
+			args.v3.usSpreadSpectrumAmount = 0;
+			args.v3.usSpreadSpectrumStep = 0;
+			break;
+		case ATOM_PPLL_INVALID:
+			return;
+		}
+		args.v2.ucEnable = enable;
+	} else if (ASIC_IS_DCE4(rdev)) {
 		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 		args.v2.ucSpreadSpectrumType = ss->type;
 		switch (pll_id) {