From 410b3cb1d5d356d9b31aee47cb5e55eba2f8bf26 Mon Sep 17 00:00:00 2001
From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Date: Thu, 10 Nov 2011 16:42:16 +0900
Subject: [PATCH] --- yaml --- r: 275930 b: refs/heads/master c:
 b3c004542229099e18198061c737e13eafc8d4d6 h: refs/heads/master v: v3

---
 [refs]                                 | 2 +-
 trunk/drivers/pci/hotplug/pciehp_hpc.c | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 89fd7f45b675..ee15fc9e6371 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 0027cb3e1947d0f453fece40ed16764fb362bac6
+refs/heads/master: b3c004542229099e18198061c737e13eafc8d4d6
diff --git a/trunk/drivers/pci/hotplug/pciehp_hpc.c b/trunk/drivers/pci/hotplug/pciehp_hpc.c
index 81a177a5f032..7b1414810ae3 100644
--- a/trunk/drivers/pci/hotplug/pciehp_hpc.c
+++ b/trunk/drivers/pci/hotplug/pciehp_hpc.c
@@ -302,6 +302,14 @@ int pciehp_check_link_status(struct controller *ctrl)
 		return retval;
 	}
 
+	/*
+	 * If the port supports Link speeds greater than 5.0 GT/s, we
+	 * must wait for 100 ms after Link training completes before
+	 * sending configuration request.
+	 */
+	if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT)
+		msleep(100);
+
 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 
 	return retval;