From 411173ed0b1991abeeed0bffabee8663a800cbcd Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 2 Jan 2013 14:53:21 -0700 Subject: [PATCH] --- yaml --- r: 355755 b: refs/heads/master c: 97d5520f9364444ec78f0a20bf6d880ea80934b8 h: refs/heads/master i: 355753: 67e11a87215bff2c30466c152b2e70e38d6be723 355751: f04ad43944743832e90832f49018bc4a48e4ad4e v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/tegra20-ventana.dts | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 4fd107f46709..455ac0297678 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a75191e6b4743d756b5435b11abe41cc3dd62cdd +refs/heads/master: 97d5520f9364444ec78f0a20bf6d880ea80934b8 diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index 0392dea69837..e3d3b29abbb3 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,6 +10,18 @@ reg = <0x00000000 0x40000000>; }; + host1x { + hdmi { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -320,7 +332,7 @@ i2c@7000c400 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; }; i2cmux { @@ -335,7 +347,7 @@ pinctrl-1 = <&state_i2cmux_pta>; pinctrl-2 = <&state_i2cmux_idle>; - i2c@0 { + hdmi_ddc: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -446,13 +458,13 @@ regulator-max-microvolt = <1800000>; }; - ldo7 { + hdmi_vdd_reg: ldo7 { regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo8 { + hdmi_pll_reg: ldo8 { regulator-name = "vdd_ldo8,avdd_hdmi_pll"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>;