From 411b20f4bbe039b81f2e1e1f4bcdc6e7866ec400 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 12 May 2008 14:02:25 -0700 Subject: [PATCH] --- yaml --- r: 96487 b: refs/heads/master c: baf6332a238a680ef3add9cfb0729f136da886b8 h: refs/heads/master i: 96485: 10670a27fc183407c036881c6c2f26e9dba311dc 96483: c30cb23668eaba45fd23f51dddee5f996089b448 96479: 9109b2a3e086bf0d125ffedf9bdb8a1a389a5906 v: v3 --- [refs] | 2 +- trunk/drivers/video/atmel_lcdfb.c | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 715979a9c2f0..950d48916965 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 945185a69daa457c4c5e46e47f4afad7dcea734f +refs/heads/master: baf6332a238a680ef3add9cfb0729f136da886b8 diff --git a/trunk/drivers/video/atmel_lcdfb.c b/trunk/drivers/video/atmel_lcdfb.c index 8ffdf3578768..b004036d4087 100644 --- a/trunk/drivers/video/atmel_lcdfb.c +++ b/trunk/drivers/video/atmel_lcdfb.c @@ -441,14 +441,15 @@ static int atmel_lcdfb_set_par(struct fb_info *info) value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); - value = (value / 2) - 1; - dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value); - - if (value <= 0) { + if (value < 2) { dev_notice(info->device, "Bypassing pixel clock divider\n"); lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); } else { - lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET); + value = (value / 2) - 1; + dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", + value); + lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, + value << ATMEL_LCDC_CLKVAL_OFFSET); info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1))); dev_dbg(info->device, " updated pixclk: %lu KHz\n", PICOS2KHZ(info->var.pixclock));