From 41e256f5c659d18ec84e04f1c5c475193cee4406 Mon Sep 17 00:00:00 2001 From: Jeff Garzik Date: Tue, 14 Nov 2006 14:46:17 -0500 Subject: [PATCH] --- yaml --- r: 42116 b: refs/heads/master c: 46b027cc30b6f6571191826afc718fa942403fc8 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/ata/sata_promise.c | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 48dabd4cf3ae..752694617ab2 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d25614bad6eec8fb80f3ef5bffbf720ebb7d2412 +refs/heads/master: 46b027cc30b6f6571191826afc718fa942403fc8 diff --git a/trunk/drivers/ata/sata_promise.c b/trunk/drivers/ata/sata_promise.c index 72eda5160fad..9c4389b5689a 100644 --- a/trunk/drivers/ata/sata_promise.c +++ b/trunk/drivers/ata/sata_promise.c @@ -46,15 +46,14 @@ #include "sata_promise.h" #define DRV_NAME "sata_promise" -#define DRV_VERSION "1.04" +#define DRV_VERSION "1.05" enum { PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ - PDC_TBG_MODE = 0x41, /* TBG mode */ + PDC_TBG_MODE = 0x41C, /* TBG mode */ PDC_FLASH_CTL = 0x44, /* Flash control register */ - PDC_PCI_CTL = 0x48, /* PCI control and status register */ PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */