From 42006919a3ef09e6565c8f2e30734083c5c23461 Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Fri, 4 May 2012 17:18:18 -0300
Subject: [PATCH] --- yaml --- r: 307409 b: refs/heads/master c:
 1d4f85ac2d5ef1892deba2a3df8a5695645418c8 h: refs/heads/master i:   307407:
 b6fd13a468fd98ff8bddcb340baf5f2a871d0fa5 v: v3

---
 [refs]                                  | 2 +-
 trunk/drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index dc1d04184034..4da2b7b9cbb0 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 22509ec8676fdbba8da525b9ec9cb3ddb4cb71b0
+refs/heads/master: 1d4f85ac2d5ef1892deba2a3df8a5695645418c8
diff --git a/trunk/drivers/gpu/drm/i915/intel_hdmi.c b/trunk/drivers/gpu/drm/i915/intel_hdmi.c
index b84d19d0eaed..af88313d72d0 100644
--- a/trunk/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/trunk/drivers/gpu/drm/i915/intel_hdmi.c
@@ -132,7 +132,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
 	else
 		return;
 
-	val &= ~VIDEO_DIP_SELECT_MASK;
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
 	val |= VIDEO_DIP_ENABLE;