diff --git a/[refs] b/[refs]
index b679e6ffc401..f0c953a5fe14 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9a8fca0499c611ab37b5c0d4481ca09d3f6e8101
+refs/heads/master: e6ed89ac9f5da16fea5111651b6de0ff0a76a5c2
diff --git a/trunk/arch/arm/mm/proc-xsc3.S b/trunk/arch/arm/mm/proc-xsc3.S
index 80873b36c3f7..8d32e21fe151 100644
--- a/trunk/arch/arm/mm/proc-xsc3.S
+++ b/trunk/arch/arm/mm/proc-xsc3.S
@@ -427,12 +427,13 @@ __xsc3_setup:
 #endif
 	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg
 	mrc	p15, 0, r0, c1, c0, 0		@ get control register
-	bic	r0, r0, #0x0200			@ .... ..R. .... ....
 	bic	r0, r0, #0x0002			@ .... .... .... ..A.
 	orr	r0, r0, #0x0005			@ .... .... .... .C.M
 #if BTB_ENABLE
+	bic	r0, r0, #0x0200			@ .... ..R. .... ....
 	orr	r0, r0, #0x3900			@ ..VI Z..S .... ....
 #else
+	bic	r0, r0, #0x0a00			@ .... Z.R. .... ....
 	orr	r0, r0, #0x3100			@ ..VI ...S .... ....
 #endif
 #if L2_CACHE_ENABLE