From 435f4f966a394bd72c751a1a05ec3665eb2bb107 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 21 Apr 2012 16:23:24 +0100 Subject: [PATCH] --- yaml --- r: 307290 b: refs/heads/master c: 1869b620d27a0e353bd6558015713fad2d0cc09b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem_tiling.c | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 7533490dfb50..9bccb7ee1874 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5d82e3e6427d407e5e4713a2f73210b4e7801ad3 +refs/heads/master: 1869b620d27a0e353bd6558015713fad2d0cc09b diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c index c9786cd5dfe3..b964df51cec7 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -354,14 +354,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, /* We need to rebind the object if its current allocation * no longer meets the alignment restrictions for its new * tiling mode. Otherwise we can just leave it alone, but - * need to ensure that any fence register is cleared. + * need to ensure that any fence register is updated before + * the next fenced (either through the GTT or by the BLT unit + * on older GPUs) access. * * After updating the tiling parameters, we then flag whether * we need to update an associated fence register. Note this * has to also include the unfenced register the GPU uses * whilst executing a fenced command for an untiled object. */ - i915_gem_release_mmap(obj); obj->map_and_fenceable = obj->gtt_space == NULL || @@ -385,6 +386,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, obj->tiling_mode = args->tiling_mode; obj->stride = args->stride; + + /* Force the fence to be reacquired for GTT access */ + i915_gem_release_mmap(obj); } } /* we have to maintain this existing ABI... */