From 4378a2dcc0ab4ffdbbfd46a9733770070f2d6907 Mon Sep 17 00:00:00 2001
From: Matt Carlson <mcarlson@broadcom.com>
Date: Mon, 12 Apr 2010 06:58:26 +0000
Subject: [PATCH] --- yaml --- r: 194025 b: refs/heads/master c:
 a977dbe8445b8a81d6127c4aa9112a2c29a1a008 h: refs/heads/master i:   194023:
 dc30f8deb5dd049348ddc6cb999c70fdab2c685b v: v3

---
 [refs]                  | 2 +-
 trunk/drivers/net/tg3.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index d51611b603d7..846decf66957 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1a3190254c0d1d1951e1d7e93542387c6ec82384
+refs/heads/master: a977dbe8445b8a81d6127c4aa9112a2c29a1a008
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index a0ab89eb8bcc..3e893231fef3 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 		     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
 
 		tw32(GRC_MODE, grc_mode);
+
+		val = tr32(TG3_CPMU_LSPD_10MB_CLK);
+		val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
+		val |= CPMU_LSPD_10MB_MACCLK_6_25;
+		tw32(TG3_CPMU_LSPD_10MB_CLK, val);
 	}
 
 	/* This works around an issue with Athlon chipsets on