From 442f7575b22b0384998b7fc29166bdeb531fe4da Mon Sep 17 00:00:00 2001
From: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Date: Mon, 24 Dec 2007 19:46:06 -0600
Subject: [PATCH] --- yaml --- r: 81216 b: refs/heads/master c:
 67196d7275fcbc62c41c34400855d3d3c95d8d1d h: refs/heads/master v: v3

---
 [refs]                        |  2 +-
 trunk/arch/powerpc/boot/4xx.c | 13 ++++++-------
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/[refs] b/[refs]
index bb69bb4d5379..7ad396199c58 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3f8c5c3b4d07fa24e7081a54798ddfab7360a102
+refs/heads/master: 67196d7275fcbc62c41c34400855d3d3c95d8d1d
diff --git a/trunk/arch/powerpc/boot/4xx.c b/trunk/arch/powerpc/boot/4xx.c
index 1a83efe274c1..33f25b671340 100644
--- a/trunk/arch/powerpc/boot/4xx.c
+++ b/trunk/arch/powerpc/boot/4xx.c
@@ -243,7 +243,8 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
 		*emac1 = EMAC_RESET;
 
 	mtdcr(DCRN_MAL0_CFG, MAL_RESET);
-	while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {};
+	while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
+		; /* loop until reset takes effect */
 }
 
 /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
@@ -515,19 +516,17 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
 	opb = plb / opdv;
 	ebc = plb / epdv;
 
-	if (cpc0_cr0 & 0x80) {
+	if (cpc0_cr0 & 0x80)
 		/* uart0 uses the external clock */
 		uart0 = ser_clk;
-	} else {
+	else
 		uart0 = cpu / udiv;
-	}
 
-	if (cpc0_cr0 & 0x40) {
+	if (cpc0_cr0 & 0x40)
 		/* uart1 uses the external clock */
 		uart1 = ser_clk;
-	} else {
+	else
 		uart1 = cpu / udiv;
-	}
 
 	/* setup the timebase clock to tick at the cpu frequency */
 	cpc0_cr1 = cpc0_cr1 & ~0x00800000;