From 44f91e179c8d3dd3b156e93d7cd47ea86701e5af Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 18 Feb 2013 19:00:21 -0300 Subject: [PATCH] --- yaml --- r: 371159 b: refs/heads/master c: 3f1e109a8be5670487e00e1c6bc0670526325227 h: refs/heads/master i: 371157: 79902ff041ae42e9bc4bf469e014e16a7dad6503 371155: 29c0b3721609be414da8c11a2e3dc92f3cc3f9ed 371151: e414a1a75bec36438191f5817dcb594b481a227c v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_drv.c | 8 ++++---- trunk/drivers/gpu/drm/i915/i915_reg.h | 3 +++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 396356b9ee30..34b0c4a39d84 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 115bc2de52af131c2c9bb2bda1adde88c9aa8fef +refs/heads/master: 3f1e109a8be5670487e00e1c6bc0670526325227 diff --git a/trunk/drivers/gpu/drm/i915/i915_drv.c b/trunk/drivers/gpu/drm/i915/i915_drv.c index 07ac769d7313..b342749fcc87 100644 --- a/trunk/drivers/gpu/drm/i915/i915_drv.c +++ b/trunk/drivers/gpu/drm/i915/i915_drv.c @@ -1133,10 +1133,10 @@ static void hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) { if (IS_HASWELL(dev_priv->dev) && - (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { + (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); - I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); } } @@ -1144,9 +1144,9 @@ static void hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) { if (IS_HASWELL(dev_priv->dev) && - (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { + (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { DRM_ERROR("Unclaimed write to %x\n", reg); - writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); } } diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 527b664d3434..9e5844b2f1f5 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -522,6 +522,9 @@ #define GEN7_ERR_INT 0x44040 #define ERR_INT_MMIO_UNCLAIMED (1<<13) +#define FPGA_DBG 0x42300 +#define FPGA_DBG_RM_NOCLAIM (1<<31) + #define DERRMR 0x44050 /* GM45+ chicken bits -- debug workaround bits that may be required