From 457a7f8c9afa0acd15393ea335fe8545fffba826 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Fri, 7 Mar 2008 01:34:52 +1100 Subject: [PATCH] --- yaml --- r: 91467 b: refs/heads/master c: 6e42b21bb91a562cd843a156586fe7b5954f58b3 h: refs/heads/master i: 91465: d79ebd9e38d9082d40487ce0b0044aab191141f9 91463: c131027d4fa5cb121eb20c0f4db1c511479fc83d v: v3 --- [refs] | 2 +- trunk/arch/powerpc/sysdev/ppc4xx_pci.c | 13 +++++-------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 05f0b2b77d1e..f188d588a099 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 266d028acb615e1766c3fb9530c9e86de8476a33 +refs/heads/master: 6e42b21bb91a562cd843a156586fe7b5954f58b3 diff --git a/trunk/arch/powerpc/sysdev/ppc4xx_pci.c b/trunk/arch/powerpc/sysdev/ppc4xx_pci.c index d183b8390ec3..6c925b7975f9 100644 --- a/trunk/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/trunk/arch/powerpc/sysdev/ppc4xx_pci.c @@ -646,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np) int time_out = 20; /* Set PLL clock receiver to LVPECL */ - mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28); + dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); /* Shouldn't we do all the calibration stuff etc... here ? */ if (ppc440spe_pciex_check_reset(np)) @@ -660,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np) } /* De-assert reset of PCIe PLL, wait for lock */ - mtdcri(SDR0, PESDR0_PLLLCT1, - mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24)); + dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); udelay(3); while (time_out) { @@ -713,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 0x35000000); } - val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET); - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - (val & ~(1 << 24 | 1 << 16)) | 1 << 12); + dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, + (1 << 24) | (1 << 16), 1 << 12); return 0; } @@ -1156,8 +1154,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) port->link = 0; } - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20); + dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); msleep(100); return 0;