From 45baa2f93dff7d719b385e0a2bc1fbc3fb256e7a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 30 Oct 2007 12:03:47 +0800 Subject: [PATCH] --- yaml --- r: 72885 b: refs/heads/master c: 41241c17eb11df08efa81727f9c01225cd0f56b3 h: refs/heads/master i: 72883: 7a9ad90681dd66ad90a9be08039abe1b8cdf4597 v: v3 --- [refs] | 2 +- trunk/include/asm-blackfin/mach-bf561/defBF561.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e84c49cc56e8..5571cdd5f5f9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 36208059c18cd5e8c89fc9037cb1a79e62733882 +refs/heads/master: 41241c17eb11df08efa81727f9c01225cd0f56b3 diff --git a/trunk/include/asm-blackfin/mach-bf561/defBF561.h b/trunk/include/asm-blackfin/mach-bf561/defBF561.h index bf7dc4e00065..7945e8a3a841 100644 --- a/trunk/include/asm-blackfin/mach-bf561/defBF561.h +++ b/trunk/include/asm-blackfin/mach-bf561/defBF561.h @@ -55,6 +55,9 @@ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ #define SWRST SICA_SWRST #define SYSCR SICA_SYSCR +#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) +#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) +#define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define SICA_SWRST 0xFFC00100 /* Software Reset register */