From 463589e9a2cac8ff27af951bb11b0fbb0fc69976 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 19 Nov 2012 09:11:27 -0500 Subject: [PATCH] --- yaml --- r: 335886 b: refs/heads/master c: 804cc4a0ad3a896ca295f771a28c6eb36ced7903 h: refs/heads/master v: v3 --- [refs] | 2 +- .../gpu/drm/nouveau/core/engine/disp/nv50.c | 19 +++++++------------ .../drm/nouveau/core/engine/graph/ctxnv40.c | 12 +++--------- .../gpu/drm/nouveau/core/engine/graph/nv40.c | 4 +--- .../gpu/drm/nouveau/core/engine/graph/nv40.h | 2 +- .../drm/nouveau/core/include/core/object.h | 14 +++++--------- .../drm/nouveau/core/include/subdev/clock.h | 3 +-- .../gpu/drm/nouveau/core/subdev/bios/dcb.c | 2 +- .../gpu/drm/nouveau/core/subdev/clock/nva3.c | 19 ------------------- .../gpu/drm/nouveau/core/subdev/clock/nvc0.c | 1 - trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c | 4 ---- trunk/drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-- trunk/drivers/gpu/drm/radeon/evergreen.c | 2 ++ 13 files changed, 23 insertions(+), 64 deletions(-) diff --git a/[refs] b/[refs] index b82899fbb86c..24cc0b03939c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: da6004b8d02f79b893d425d11400ccad2b7c2efd +refs/heads/master: 804cc4a0ad3a896ca295f771a28c6eb36ced7903 diff --git a/trunk/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/trunk/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 15b182c84ce8..05a909a17cee 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/trunk/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -49,7 +49,13 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) if (chan->vblank.crtc != crtc) continue; - if (nv_device(priv)->chipset >= 0xc0) { + if (nv_device(priv)->chipset == 0x50) { + nv_wr32(priv, 0x001704, chan->vblank.channel); + nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); + bar->flush(bar); + nv_wr32(priv, 0x001570, chan->vblank.offset); + nv_wr32(priv, 0x001574, chan->vblank.value); + } else { nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); bar->flush(bar); nv_wr32(priv, 0x06000c, @@ -57,17 +63,6 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); nv_wr32(priv, 0x060014, chan->vblank.value); - } else { - nv_wr32(priv, 0x001704, chan->vblank.channel); - nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); - bar->flush(bar); - if (nv_device(priv)->chipset == 0x50) { - nv_wr32(priv, 0x001570, chan->vblank.offset); - nv_wr32(priv, 0x001574, chan->vblank.value); - } else { - nv_wr32(priv, 0x060010, chan->vblank.offset); - nv_wr32(priv, 0x060014, chan->vblank.value); - } } list_del(&chan->vblank.head); diff --git a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c index 7bbb1e1b7a8d..e45035efb8ca 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c +++ b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c @@ -669,27 +669,21 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) }); } -int +void nv40_grctx_init(struct nouveau_device *device, u32 *size) { - u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; + u32 ctxprog[256], i; struct nouveau_grctx ctx = { .device = device, .mode = NOUVEAU_GRCTX_PROG, .data = ctxprog, - .ctxprog_max = 256, + .ctxprog_max = ARRAY_SIZE(ctxprog) }; - if (!ctxprog) - return -ENOMEM; - nv40_grctx_generate(&ctx); nv_wr32(device, 0x400324, 0); for (i = 0; i < ctx.ctxprog_len; i++) nv_wr32(device, 0x400328, ctxprog[i]); *size = ctx.ctxvals_pos * 4; - - kfree(ctxprog); - return 0; } diff --git a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c index cc6574eeb80e..425001204a89 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c +++ b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c @@ -346,9 +346,7 @@ nv40_graph_init(struct nouveau_object *object) return ret; /* generate and upload context program */ - ret = nv40_grctx_init(nv_device(priv), &priv->size); - if (ret) - return ret; + nv40_grctx_init(nv_device(priv), &priv->size); /* No context present currently */ nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); diff --git a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h index 7da35a4e7970..d2ac975afc2e 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h +++ b/trunk/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h @@ -15,7 +15,7 @@ nv44_graph_class(void *priv) return !(0x0baf & (1 << (device->chipset & 0x0f))); } -int nv40_grctx_init(struct nouveau_device *, u32 *size); +void nv40_grctx_init(struct nouveau_device *, u32 *size); void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); #endif diff --git a/trunk/drivers/gpu/drm/nouveau/core/include/core/object.h b/trunk/drivers/gpu/drm/nouveau/core/include/core/object.h index 486f1a9217fd..818feabbf4a0 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/include/core/object.h +++ b/trunk/drivers/gpu/drm/nouveau/core/include/core/object.h @@ -175,18 +175,14 @@ nv_mo32(void *obj, u32 addr, u32 mask, u32 data) return temp; } -static inline int -nv_memcmp(void *obj, u32 addr, const char *str, u32 len) +static inline bool +nv_strncmp(void *obj, u32 addr, u32 len, const char *str) { - unsigned char c1, c2; - while (len--) { - c1 = nv_ro08(obj, addr++); - c2 = *(str++); - if (c1 != c2) - return c1 - c2; + if (nv_ro08(obj, addr++) != *(str++)) + return false; } - return 0; + return true; } #endif diff --git a/trunk/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/trunk/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index 41b7a6a76f19..39e73b91d360 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/trunk/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -54,7 +54,6 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, struct nouveau_pll_vals *); -int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, - int clk, struct nouveau_pll_vals *); + #endif diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c index c51197157749..7d750382a833 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c @@ -64,7 +64,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } } else if (*ver >= 0x15) { - if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) { + if (!nv_strncmp(bios, dcb - 7, 7, "DEV_REC")) { u16 i2c = nv_ro16(bios, dcb + 2); *hdr = 4; *cnt = (i2c - dcb) / 10; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c index 9068c98b96f6..cc8d7d162d7c 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c @@ -66,24 +66,6 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) return ret; } -int -nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, - int clk, struct nouveau_pll_vals *pv) -{ - int ret, N, M, P; - - ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P); - - if (ret > 0) { - pv->refclk = info->refclk; - pv->N1 = N; - pv->M1 = M; - pv->log2P = P; - } - return ret; -} - - static int nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, @@ -98,7 +80,6 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.pll_set = nva3_clock_pll_set; - priv->base.pll_calc = nva3_clock_pll_calc; return 0; } diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c index f6962c9b6c36..5ccce0b17bf3 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c @@ -79,7 +79,6 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.pll_set = nvc0_clock_pll_set; - priv->base.pll_calc = nva3_clock_pll_calc; return 0; } diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c b/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c index cbf1fc60a386..cc79c796afee 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -241,10 +241,6 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) if (unlikely(!abi16)) return -ENOMEM; - - if (!drm->channel) - return nouveau_abi16_put(abi16, -ENODEV); - client = nv_client(abi16->client); if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c index 8503b2ea570a..0910125cbbc3 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -129,8 +129,7 @@ nouveau_accel_init(struct nouveau_drm *drm) /* initialise synchronisation routines */ if (device->card_type < NV_10) ret = nv04_fence_create(drm); - else if (device->card_type < NV_50) ret = nv10_fence_create(drm); - else if (device->chipset < 0x84) ret = nv50_fence_create(drm); + else if (device->chipset < 0x84) ret = nv10_fence_create(drm); else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); else ret = nvc0_fence_create(drm); if (ret) { diff --git a/trunk/drivers/gpu/drm/radeon/evergreen.c b/trunk/drivers/gpu/drm/radeon/evergreen.c index af31f829f4a8..219942c660d7 100644 --- a/trunk/drivers/gpu/drm/radeon/evergreen.c +++ b/trunk/drivers/gpu/drm/radeon/evergreen.c @@ -1330,6 +1330,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav break; udelay(1); } + } else { + save->crtc_enabled[i] = false; } }