From 46c77792758fccea225fe78308f612a5277e7437 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Tue, 26 Mar 2013 15:42:59 -0700 Subject: [PATCH] --- yaml --- r: 374647 b: refs/heads/master c: 6ead7e484957f2ae9bf2085688518d95ce75ab80 h: refs/heads/master i: 374645: 741be6e0377a216e8a98777a5efcdf41a7ab5f4e 374643: e39296abcb523f353c1bc1c27156f1f7043a2d67 374639: 4191b5e3cd07dffc7442dc40da713c077c50e859 v: v3 --- [refs] | 2 +- trunk/drivers/dma/ioat/dma_v3.c | 34 ++++++++++++++++++++------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/[refs] b/[refs] index ea6e08c7ebae..662c40858e39 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8a52b9ff1154a68b6a2a8da9a31a87e52f5f6418 +refs/heads/master: 6ead7e484957f2ae9bf2085688518d95ce75ab80 diff --git a/trunk/drivers/dma/ioat/dma_v3.c b/trunk/drivers/dma/ioat/dma_v3.c index 65b912aa1012..804522c1300a 100644 --- a/trunk/drivers/dma/ioat/dma_v3.c +++ b/trunk/drivers/dma/ioat/dma_v3.c @@ -1331,20 +1331,28 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); - /* clear any pending errors */ - err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); - if (err) { - dev_err(&pdev->dev, "channel error register unreachable\n"); - return err; - } - pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr); + if (device->version < IOAT_VER_3_3) { + /* clear any pending errors */ + err = pci_read_config_dword(pdev, + IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); + if (err) { + dev_err(&pdev->dev, + "channel error register unreachable\n"); + return err; + } + pci_write_config_dword(pdev, + IOAT_PCI_CHANERR_INT_OFFSET, chanerr); - /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit - * (workaround for spurious config parity error after restart) - */ - pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); - if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) - pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); + /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit + * (workaround for spurious config parity error after restart) + */ + pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); + if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { + pci_write_config_dword(pdev, + IOAT_PCI_DMAUNCERRSTS_OFFSET, + 0x10); + } + } err = ioat2_reset_sync(chan, msecs_to_jiffies(200)); if (err) {