From 46ce3d46c81c12b3b8c58ba391ddd4f7154a0800 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Mon, 29 Oct 2012 18:25:45 +0800 Subject: [PATCH] --- yaml --- r: 340038 b: refs/heads/master c: 5ab134ad09988ca8225e759a052df7a1bbd26145 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/tegra20.dtsi | 9 +++++++++ trunk/arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 26726c58d506..7fbfb54879d5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d534b5d4a530d2d1597c3ffb9e896a3499da6172 +refs/heads/master: 5ab134ad09988ca8225e759a052df7a1bbd26145 diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index f3a09d0d45bc..f40cfbaa7c7e 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index b1497c7d7d68..148371b432a0 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000