From 4795f9d0233cf1d03a1c929eca2c9b76ce2489f8 Mon Sep 17 00:00:00 2001
From: Stephane Eranian <eranian@google.com>
Date: Mon, 20 Aug 2012 11:24:21 +0200
Subject: [PATCH] --- yaml --- r: 322819 b: refs/heads/master c:
 3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4 h: refs/heads/master i:   322817:
 705475084bf8f4a9da402f5d7cc1817935140bdf   322815:
 377639e670cffbf9dd6357a14b18a7fdaeb9ee51 v: v3

---
 [refs]                                           | 2 +-
 trunk/arch/x86/kernel/cpu/perf_event_intel.c     | 1 +
 trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c | 3 ++-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 93b0a4ed1254..cebfc45ee22b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a6fa941d94b411bbd2b6421ffbde6db3c93e65ab
+refs/heads/master: 3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
diff --git a/trunk/arch/x86/kernel/cpu/perf_event_intel.c b/trunk/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e03e79..0d3d63afa76a 100644
--- a/trunk/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/trunk/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 28: /* Atom */
+	case 54: /* Cedariew */
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 
diff --git a/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b4265fcd2..da02e9cc3754 100644
--- a/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
 	 * to have an operational LBR which can freeze
 	 * on PMU interrupt
 	 */
-	if (boot_cpu_data.x86_mask < 10) {
+	if (boot_cpu_data.x86_model == 28
+	    && boot_cpu_data.x86_mask < 10) {
 		pr_cont("LBR disabled due to erratum");
 		return;
 	}