From 482a17782b9d222bd60f0a4a17d58d232dd4a659 Mon Sep 17 00:00:00 2001 From: Akira Takeuchi Date: Wed, 27 Oct 2010 17:28:39 +0100 Subject: [PATCH] --- yaml --- r: 218708 b: refs/heads/master c: 06019be31a1b5812eec5bb3e1dbdeced04950e8e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mn10300/include/asm/cache.h | 14 +++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 5452071e8044..904ec39ea62d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a116956423e1cdc4398110bdc66d66ae4c5ba90f +refs/heads/master: 06019be31a1b5812eec5bb3e1dbdeced04950e8e diff --git a/trunk/arch/mn10300/include/asm/cache.h b/trunk/arch/mn10300/include/asm/cache.h index 781bf613366d..f29cde2cfc91 100644 --- a/trunk/arch/mn10300/include/asm/cache.h +++ b/trunk/arch/mn10300/include/asm/cache.h @@ -43,14 +43,18 @@ /* instruction cache access registers */ #define ICACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) + __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) #define ICACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES, u32) -/* instruction cache access registers */ +/* data cache access registers */ #define DCACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) + __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) #define DCACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) + __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \ + (ENTRY) * L1_CACHE_BYTES, u32) #endif /* _ASM_CACHE_H */