From 488702522ab272b207508bb4d901517ebb8e0e23 Mon Sep 17 00:00:00 2001 From: Martin Peres Date: Sun, 10 Jul 2011 00:08:41 +0200 Subject: [PATCH] --- yaml --- r: 282596 b: refs/heads/master c: dd1da8de172057b36860f427777ecfa293bb8f6c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_pm.h | 4 ++-- trunk/drivers/gpu/drm/nouveau/nv40_pm.c | 7 +++++-- trunk/drivers/gpu/drm/nouveau/nva3_pm.c | 6 +++++- 5 files changed, 14 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index 374e86d4d2dd..2b9817d86e87 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6109183794a711d80c08705d477d2a19b437d5c1 +refs/heads/master: dd1da8de172057b36860f427777ecfa293bb8f6c diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h b/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h index 156aea75d3e7..067bda411a21 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -555,7 +555,7 @@ struct nouveau_pm_engine { int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); - void (*clocks_set)(struct drm_device *, void *); + int (*clocks_set)(struct drm_device *, void *); int (*voltage_get)(struct drm_device *); int (*voltage_set)(struct drm_device *, int voltage); diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.h b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.h index 5c87afde82d6..41050feb5b90 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.h +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.h @@ -55,7 +55,7 @@ void nv04_pm_clock_set(struct drm_device *, void *); /* nv40_pm.c */ int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *); void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *); -void nv40_pm_clocks_set(struct drm_device *, void *); +int nv40_pm_clocks_set(struct drm_device *, void *); int nv40_pm_pwm_get(struct drm_device *, struct dcb_gpio_entry *, u32*, u32*); int nv40_pm_pwm_set(struct drm_device *, struct dcb_gpio_entry *, u32, u32); @@ -70,7 +70,7 @@ int nv50_pm_pwm_set(struct drm_device *, struct dcb_gpio_entry *, u32, u32); /* nva3_pm.c */ int nva3_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *); void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *); -void nva3_pm_clocks_set(struct drm_device *, void *); +int nva3_pm_clocks_set(struct drm_device *, void *); /* nvc0_pm.c */ int nvc0_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *); diff --git a/trunk/drivers/gpu/drm/nouveau/nv40_pm.c b/trunk/drivers/gpu/drm/nouveau/nv40_pm.c index 02d5be8bff1b..3d5a5a7856e6 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv40_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nv40_pm.c @@ -222,7 +222,7 @@ nv40_pm_gr_idle(void *data) return true; } -void +int nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -231,7 +231,7 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) struct bit_entry M; u32 crtc_mask = 0; u8 sr1[2]; - int i; + int i, ret = -EAGAIN; /* determine which CRTCs are active, fetch VGA_SR1 for each */ for (i = 0; i < 2; i++) { @@ -263,6 +263,8 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev)) goto resume; + ret = 0; + /* set engine clocks */ nv_mask(dev, 0x00c040, 0x00000333, 0x00000000); nv_wr32(dev, 0x004004, info->npll_coef); @@ -345,6 +347,7 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); kfree(info); + return ret; } int diff --git a/trunk/drivers/gpu/drm/nouveau/nva3_pm.c b/trunk/drivers/gpu/drm/nouveau/nva3_pm.c index 618c144b7a30..9e636e6ef6d7 100644 --- a/trunk/drivers/gpu/drm/nouveau/nva3_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nva3_pm.c @@ -287,12 +287,13 @@ nva3_pm_grcp_idle(void *data) return false; } -void +int nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nva3_pm_state *info = pre_state; unsigned long flags; + int ret = -EAGAIN; /* prevent any new grctx switches from starting */ spin_lock_irqsave(&dev_priv->context_switch_lock, flags); @@ -328,6 +329,8 @@ nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) nv_wr32(dev, 0x100210, 0x80000000); } + ret = 0; + cleanup: /* unfreeze PFIFO */ nv_mask(dev, 0x002504, 0x00000001, 0x00000000); @@ -339,4 +342,5 @@ nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) nv_mask(dev, 0x400824, 0x10000000, 0x10000000); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); kfree(info); + return ret; }