From 48a3efaa3be02c4a0dbb6e218ee5dfe0f34528aa Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 21 Jun 2011 20:53:20 +0200 Subject: [PATCH] --- yaml --- r: 256079 b: refs/heads/master c: e913d468308be1cce7cc8e6e6e997d54a403ce64 h: refs/heads/master i: 256077: f9a3006ee2efdf644ddfbe3301c27667b0376bcd 256075: 49ee37ec0c3f86eccf46b14a86620f7ac72c68a0 256071: c390d57efb0482b0185792d7c0c86837fdc2b0d0 256063: eb2b2bd5f38f0928220262e3b0c34cd43117fdbc v: v3 --- [refs] | 2 +- trunk/drivers/ssb/main.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 7ead890a1395..f1b4b20eed0e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f9fc51365d0cf66d1f95f47618566f27177ecbbc +refs/heads/master: e913d468308be1cce7cc8e6e6e997d54a403ce64 diff --git a/trunk/drivers/ssb/main.c b/trunk/drivers/ssb/main.c index e568664f8b9c..57b7b6460896 100644 --- a/trunk/drivers/ssb/main.c +++ b/trunk/drivers/ssb/main.c @@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) switch (plltype) { case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ if (m & SSB_CHIPCO_CLK_T6_MMASK) - return SSB_CHIPCO_CLK_T6_M0; - return SSB_CHIPCO_CLK_T6_M1; + return SSB_CHIPCO_CLK_T6_M1; + return SSB_CHIPCO_CLK_T6_M0; case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */