From 48d3411143d19b7d1642400cba727181f0dbcb60 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 31 Oct 2012 18:12:38 -0200 Subject: [PATCH] --- yaml --- r: 345239 b: refs/heads/master c: b6b4e185a7d2835fa145bf1a2e3553431cb24a92 h: refs/heads/master i: 345237: b11d3ae492e537c5a1139ef2ae04c904ca0e0a69 345235: e95d0ff177a48f2c3dce3f326a4952e4b2660c37 345231: dd4ce0a5ed3916598e91bd3586b83a53e61ff475 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 4dd25b862f9b..24664d6f0441 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8c52b5e8554d21b1cb69836f04c9dbe483915b86 +refs/heads/master: b6b4e185a7d2835fa145bf1a2e3553431cb24a92 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 28b9d662109c..22da6d1279d7 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -1579,14 +1579,14 @@ intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) } /** - * intel_enable_pch_pll - enable PCH PLL + * ironlake_enable_pch_pll - enable PCH PLL * @dev_priv: i915 private structure * @pipe: pipe PLL to enable * * The PCH PLL needs to be enabled before the PCH transcoder, since it * drives the transcoder clock. */ -static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) +static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) { struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; struct intel_pch_pll *pll; @@ -3084,7 +3084,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) * Note that enable_pch_pll tries to do the right thing, but get_pch_pll * unconditionally resets the pll - we need that to have the right LVDS * enable sequence. */ - intel_enable_pch_pll(intel_crtc); + ironlake_enable_pch_pll(intel_crtc); if (HAS_PCH_CPT(dev)) { u32 sel; @@ -3188,7 +3188,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) * Note that enable_pch_pll tries to do the right thing, but get_pch_pll * unconditionally resets the pll - we need that to have the right LVDS * enable sequence. */ - intel_enable_pch_pll(intel_crtc); + ironlake_enable_pch_pll(intel_crtc); lpt_program_iclkip(crtc);