From 48e77df39337bd06c8cbee8e1d841731d6f2a2cd Mon Sep 17 00:00:00 2001 From: Jaswinder Singh Rajput Date: Wed, 1 Jul 2009 17:49:38 +0530 Subject: [PATCH] --- yaml --- r: 155035 b: refs/heads/master c: 44973998a111dfda09b952aa0f27cad326a97793 h: refs/heads/master i: 155033: aef98a4cd7ba081c546e2a4b55b3eec2c14760c1 155031: 487e646747bc2d507fed30978f10007aad4b1430 v: v3 --- [refs] | 2 +- trunk/arch/x86/include/asm/msr-index.h | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 7369d5699f73..82b56e831f30 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a70c352a37671fe1ebcbd317b439aa4760f4ccb7 +refs/heads/master: 44973998a111dfda09b952aa0f27cad326a97793 diff --git a/trunk/arch/x86/include/asm/msr-index.h b/trunk/arch/x86/include/asm/msr-index.h index 1692fb5050e3..6be7fc254b59 100644 --- a/trunk/arch/x86/include/asm/msr-index.h +++ b/trunk/arch/x86/include/asm/msr-index.h @@ -246,10 +246,6 @@ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) -/* Intel Model 6 */ -#define MSR_P6_EVNTSEL0 0x00000186 -#define MSR_P6_EVNTSEL1 0x00000187 - /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 #define MSR_IA32_MCG_EBX 0x00000181