From 493f4763a6b6d76b491c534fb15ee2cbb0b1769e Mon Sep 17 00:00:00 2001 From: Andrew Vasquez Date: Thu, 19 Jul 2007 15:06:01 -0700 Subject: [PATCH] --- yaml --- r: 62731 b: refs/heads/master c: f85ec187dcd65c76dcb29f70ff3b5c7f2ae37cc8 h: refs/heads/master i: 62729: b9242a7b5b1a00686e57d8012bd19a530cdc8dd8 62727: c761fc9034d056c6c9981e3b6e3d7eebc88f6454 v: v3 --- [refs] | 2 +- trunk/drivers/scsi/qla2xxx/qla_init.c | 25 ++++--------------------- 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/[refs] b/[refs] index dec5c99bd6e8..60e98898428f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fd34f55694a784052981977cb84c50ea369ffc68 +refs/heads/master: f85ec187dcd65c76dcb29f70ff3b5c7f2ae37cc8 diff --git a/trunk/drivers/scsi/qla2xxx/qla_init.c b/trunk/drivers/scsi/qla2xxx/qla_init.c index 401a8798ce52..622cf8f15fc7 100644 --- a/trunk/drivers/scsi/qla2xxx/qla_init.c +++ b/trunk/drivers/scsi/qla2xxx/qla_init.c @@ -255,7 +255,6 @@ qla24xx_pci_config(scsi_qla_host_t *ha) uint32_t d; unsigned long flags = 0; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; - int pcix_cmd_reg, pcie_dctl_reg; pci_set_master(ha->pdev); ret = pci_set_mwi(ha->pdev); @@ -268,28 +267,12 @@ qla24xx_pci_config(scsi_qla_host_t *ha) pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ - pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX); - if (pcix_cmd_reg) { - uint16_t pcix_cmd; - - pcix_cmd_reg += PCI_X_CMD; - pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd); - pcix_cmd &= ~PCI_X_CMD_MAX_READ; - pcix_cmd |= 0x0008; - pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd); - } + if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) + pcix_set_mmrbc(ha->pdev, 2048); /* PCIe -- adjust Maximum Read Request Size (2048). */ - pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); - if (pcie_dctl_reg) { - uint16_t pcie_dctl; - - pcie_dctl_reg += PCI_EXP_DEVCTL; - pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl); - pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ; - pcie_dctl |= 0x4000; - pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl); - } + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) + pcie_set_readrq(ha->pdev, 2048); /* Reset expansion ROM address decode enable */ pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);