From 49c02bf4c24599d4e8f78be4b38914535fc729f2 Mon Sep 17 00:00:00 2001 From: Stefan Schmidt Date: Wed, 9 Jul 2008 08:07:29 +0100 Subject: [PATCH] --- yaml --- r: 105098 b: refs/heads/master c: 390d452fa1d912b6e76744a34777d7390ab1fa1c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-arm/arch-pxa/pxa27x-udc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index fb3b14695cab..2bfab0012d66 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c1450f156fda8921a55e3f4fe596274278010f31 +refs/heads/master: 390d452fa1d912b6e76744a34777d7390ab1fa1c diff --git a/trunk/include/asm-arm/arch-pxa/pxa27x-udc.h b/trunk/include/asm-arm/arch-pxa/pxa27x-udc.h index bc1cf7d0773a..ab1443f8bd89 100644 --- a/trunk/include/asm-arm/arch-pxa/pxa27x-udc.h +++ b/trunk/include/asm-arm/arch-pxa/pxa27x-udc.h @@ -97,7 +97,7 @@ #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ -#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ +#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ #define UDCCSN(x) __REG2(0x40600100, (x) << 2) #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */