From 49e9662bf64b24cce1215663c49aef7bc78d252f Mon Sep 17 00:00:00 2001
From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Date: Thu, 27 Sep 2012 19:13:01 +0530
Subject: [PATCH] --- yaml --- r: 345079 b: refs/heads/master c:
 9473c8f485e1e3740d5aebf1de4838b615f9dedc h: refs/heads/master i:   345077:
 400e8a4ae45b18bee084b3403dd99d9234c578a8   345075:
 635e95e9a8cd9658d6776aea280abd8287ae2d43   345071:
 73019a1e6521a0887736359398632d998adba931 v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/intel_dp.c | 8 +++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 5a779170be4b..0fb472741183 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3bcedbe5f2a3da65326d99803cac71c1e89bc93f
+refs/heads/master: 9473c8f485e1e3740d5aebf1de4838b615f9dedc
diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c
index c63f54e84847..94945ce0048f 100644
--- a/trunk/drivers/gpu/drm/i915/intel_dp.c
+++ b/trunk/drivers/gpu/drm/i915/intel_dp.c
@@ -286,6 +286,10 @@ intel_hrawclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t clkcfg;
 
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
 	clkcfg = I915_READ(CLKCFG);
 	switch (clkcfg & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_400:
@@ -366,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if (IS_VALLEYVIEW(dev))
+			aux_clock_divider = 100;
+		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */