From 4a403ec4a9c6a0e34c425d2371a3a0c0502003d2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 12 Dec 2009 10:07:34 +0000 Subject: [PATCH] --- yaml --- r: 176008 b: refs/heads/master c: d0d26c33b63c7ec10c3fdf9c7ce0aa035f0b3200 h: refs/heads/master v: v3 --- [refs] | 2 +- .../ABI/testing/sysfs-devices-system-cpu | 15 - .../ABI/testing/sysfs-kernel-slab | 109 +- trunk/Documentation/cpu-hotplug.txt | 6 - trunk/Documentation/kernel-parameters.txt | 5 - .../powerpc/dts-bindings/fsl/board.txt | 4 - .../powerpc/dts-bindings/fsl/mpc5200.txt | 17 +- trunk/MAINTAINERS | 15 - trunk/arch/arm/Kconfig.debug | 8 - trunk/arch/arm/configs/htcherald_defconfig | 9 +- .../arm/configs/omap3_touchbook_defconfig | 2431 ------------ trunk/arch/arm/configs/omap_4430sdp_defconfig | 146 +- trunk/arch/arm/configs/omap_zoom2_defconfig | 3 +- trunk/arch/arm/configs/omap_zoom3_defconfig | 3 +- trunk/arch/arm/configs/zeus_defconfig | 2032 ---------- trunk/arch/arm/kernel/Makefile | 1 - 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trunk/arch/arm/mach-omap2/clock2xxx.h | 41 - trunk/arch/arm/mach-omap2/clock34xx.c | 953 ++++- trunk/arch/arm/mach-omap2/clock34xx.h | 2999 ++++++++++++++- trunk/arch/arm/mach-omap2/clock34xx_data.c | 3289 ----------------- trunk/arch/arm/mach-omap2/clock44xx.c | 33 - trunk/arch/arm/mach-omap2/clock44xx.h | 15 - trunk/arch/arm/mach-omap2/clock44xx_data.c | 2766 -------------- trunk/arch/arm/mach-omap2/clock_common_data.c | 39 - trunk/arch/arm/mach-omap2/clockdomain.c | 6 +- trunk/arch/arm/mach-omap2/cm-regbits-44xx.h | 1474 -------- trunk/arch/arm/mach-omap2/cm.c | 7 +- trunk/arch/arm/mach-omap2/cm.h | 15 +- trunk/arch/arm/mach-omap2/cm44xx.h | 358 -- trunk/arch/arm/mach-omap2/devices.c | 62 +- trunk/arch/arm/mach-omap2/dpll.c | 538 --- trunk/arch/arm/mach-omap2/gpmc-smc91x.c | 8 +- trunk/arch/arm/mach-omap2/gpmc.c | 2 +- trunk/arch/arm/mach-omap2/i2c.c | 56 - trunk/arch/arm/mach-omap2/id.c | 31 +- trunk/arch/arm/mach-omap2/io.c | 5 +- trunk/arch/arm/mach-omap2/mux.c | 1061 ++---- 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| 50 + trunk/arch/powerpc/platforms/iseries/htab.c | 8 +- trunk/arch/powerpc/platforms/iseries/irq.c | 4 +- trunk/arch/powerpc/platforms/powermac/pic.c | 12 +- trunk/arch/powerpc/platforms/ps3/interrupt.c | 2 +- trunk/arch/powerpc/platforms/ps3/mm.c | 2 +- trunk/arch/powerpc/platforms/pseries/Kconfig | 3 +- trunk/arch/powerpc/platforms/pseries/Makefile | 4 +- trunk/arch/powerpc/platforms/pseries/cmm.c | 29 +- trunk/arch/powerpc/platforms/pseries/dlpar.c | 558 --- .../powerpc/platforms/pseries/eeh_driver.c | 18 +- .../powerpc/platforms/pseries/hotplug-cpu.c | 182 +- .../platforms/pseries/offline_states.h | 18 - .../platforms/pseries/plpar_wrappers.h | 22 - .../arch/powerpc/platforms/pseries/reconfig.c | 8 +- .../{kernel => platforms/pseries}/rtasd.c | 48 +- .../arch/powerpc/platforms/pseries/scanlog.c | 4 +- trunk/arch/powerpc/platforms/pseries/smp.c | 19 - trunk/arch/powerpc/platforms/pseries/xics.c | 70 +- trunk/arch/powerpc/sysdev/Makefile | 1 - trunk/arch/powerpc/sysdev/cpm1.c | 4 +- trunk/arch/powerpc/sysdev/cpm2_pic.c | 14 +- trunk/arch/powerpc/sysdev/cpm_common.c | 5 +- trunk/arch/powerpc/sysdev/fsl_msi.c | 4 +- trunk/arch/powerpc/sysdev/fsl_pci.c | 18 +- trunk/arch/powerpc/sysdev/fsl_pmc.c | 88 - trunk/arch/powerpc/sysdev/fsl_soc.c | 2 +- trunk/arch/powerpc/sysdev/i8259.c | 8 +- trunk/arch/powerpc/sysdev/ipic.c | 8 +- trunk/arch/powerpc/sysdev/mpc8xx_pic.c | 6 +- trunk/arch/powerpc/sysdev/mpic.c | 26 +- trunk/arch/powerpc/sysdev/mpic_pasemi_msi.c | 2 +- trunk/arch/powerpc/sysdev/mpic_u3msi.c | 2 +- trunk/arch/powerpc/sysdev/mv64x60_pic.c | 2 +- trunk/arch/powerpc/sysdev/qe_lib/qe.c | 61 +- trunk/arch/powerpc/sysdev/qe_lib/qe_ic.c | 8 +- trunk/arch/powerpc/sysdev/tsi108_pci.c | 6 +- trunk/arch/powerpc/sysdev/uic.c | 10 +- trunk/arch/powerpc/sysdev/xilinx_intc.c | 8 +- trunk/arch/powerpc/xmon/xmon.c | 3 +- trunk/drivers/ata/Kconfig | 10 - trunk/drivers/ata/Makefile | 1 - trunk/drivers/ata/pata_macio.c | 1427 ------- trunk/drivers/base/cpu.c | 34 - trunk/drivers/block/swim3.c | 39 +- trunk/drivers/char/agp/uninorth-agp.c | 77 +- trunk/drivers/char/hvc_console.c | 1 - trunk/drivers/char/tty_io.c | 2 + trunk/drivers/ide/pmac.c | 92 +- trunk/drivers/leds/leds-fsg.c | 7 - trunk/drivers/macintosh/macio_asic.c | 52 - trunk/drivers/macintosh/mediabay.c | 328 +- trunk/drivers/macintosh/nvram.c | 11 +- trunk/drivers/macintosh/therm_adt746x.c | 15 +- trunk/drivers/macintosh/via-pmu.c | 160 +- .../drivers/macintosh/windfarm_smu_controls.c | 2 - trunk/drivers/mmc/host/of_mmc_spi.c | 2 - trunk/drivers/net/arm/ixp4xx_eth.c | 2 +- trunk/drivers/net/benet/be_main.c | 4 +- trunk/drivers/net/ehea/ehea_hcall.h | 51 + trunk/drivers/net/ehea/ehea_phyp.h | 1 + trunk/drivers/net/igb/igb_main.c | 22 +- trunk/drivers/net/igbvf/igbvf.h | 1 - trunk/drivers/net/igbvf/netdev.c | 8 +- trunk/drivers/net/smc91x.h | 15 + trunk/drivers/net/usb/kaweth.c | 4 +- trunk/drivers/of/platform.c | 305 +- trunk/drivers/pcmcia/Kconfig | 2 +- trunk/drivers/pcmcia/Makefile | 2 +- trunk/drivers/pcmcia/pxa2xx_base.c | 19 +- trunk/drivers/pcmcia/pxa2xx_base.h | 3 - trunk/drivers/pcmcia/pxa2xx_viper.c | 119 +- trunk/drivers/spi/Kconfig | 11 +- trunk/drivers/spi/Makefile | 1 - trunk/drivers/spi/mpc52xx_psc_spi.c | 25 +- trunk/drivers/spi/mpc52xx_spi.c | 520 --- trunk/drivers/spi/spi_mpc8xxx.c | 618 +--- trunk/drivers/spi/xilinx_spi.c | 3 +- trunk/drivers/usb/gadget/fsl_qe_udc.h | 15 + trunk/drivers/video/offb.c | 15 +- trunk/drivers/video/omap/lcdc.c | 33 +- trunk/drivers/watchdog/Kconfig | 4 +- trunk/drivers/watchdog/Makefile | 1 + trunk/drivers/watchdog/mpc5200_wdt.c | 293 ++ trunk/fs/proc/proc_devtree.c | 41 +- trunk/include/linux/cpu.h | 15 - trunk/include/linux/cpumask.h | 2 - trunk/include/linux/fsl_devices.h | 11 +- trunk/include/linux/kvm.h | 1 - trunk/include/linux/pci_ids.h | 14 - trunk/include/linux/sched.h | 20 +- trunk/include/linux/spi/mpc52xx_spi.h | 10 - trunk/kernel/cpu.c | 18 +- trunk/kernel/cpuset.c | 18 +- trunk/kernel/sched.c | 218 +- trunk/kernel/sched_debug.c | 13 +- trunk/kernel/sched_fair.c | 155 +- trunk/kernel/sched_features.h | 5 + trunk/kernel/sched_idletask.c | 2 +- trunk/kernel/sched_rt.c | 2 +- trunk/kernel/sysctl.c | 30 +- trunk/lib/kernel_lock.c | 4 +- trunk/mm/slab.c | 118 +- trunk/mm/slub.c | 20 +- trunk/sound/core/hrtimer.c | 15 +- trunk/sound/isa/opti9xx/opti92x-ad1848.c | 18 +- trunk/sound/pci/hda/hda_codec.h | 5 - trunk/sound/pci/hda/hda_intel.c | 3 +- trunk/sound/pci/hda/hda_proc.c | 7 +- trunk/sound/pci/hda/patch_intelhdmi.c | 114 +- trunk/sound/pci/hda/patch_sigmatel.c | 103 +- trunk/sound/soc/omap/Makefile | 6 +- trunk/virt/kvm/kvm_main.c | 5 +- 441 files changed, 12140 insertions(+), 39882 deletions(-) delete mode 100644 trunk/arch/arm/configs/omap3_touchbook_defconfig delete mode 100644 trunk/arch/arm/configs/zeus_defconfig delete mode 100644 trunk/arch/arm/kernel/early_printk.c create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/avila.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/coyote.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/dsmg600.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/fsg.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/ixdp425.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/nas100d.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/nslu2.h create mode 100644 trunk/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h delete mode 100644 trunk/arch/arm/mach-omap1/clock_data.c delete mode 100644 trunk/arch/arm/mach-omap1/i2c.c delete mode 100644 trunk/arch/arm/mach-omap1/include/mach/lcd_dma.h delete mode 100644 trunk/arch/arm/mach-omap1/include/mach/lcdc.h delete mode 100644 trunk/arch/arm/mach-omap1/lcd_dma.c delete mode 100644 trunk/arch/arm/mach-omap1/opp.h delete mode 100644 trunk/arch/arm/mach-omap1/opp_data.c delete mode 100644 trunk/arch/arm/mach-omap2/board-omap3touchbook.c create mode 100644 trunk/arch/arm/mach-omap2/clock24xx.c rename trunk/arch/arm/mach-omap2/{clock2xxx_data.c => clock24xx.h} (73%) delete mode 100644 trunk/arch/arm/mach-omap2/clock2xxx.c delete mode 100644 trunk/arch/arm/mach-omap2/clock2xxx.h delete mode 100644 trunk/arch/arm/mach-omap2/clock34xx_data.c delete mode 100644 trunk/arch/arm/mach-omap2/clock44xx.c delete mode 100644 trunk/arch/arm/mach-omap2/clock44xx.h delete mode 100644 trunk/arch/arm/mach-omap2/clock44xx_data.c delete mode 100644 trunk/arch/arm/mach-omap2/clock_common_data.c delete mode 100644 trunk/arch/arm/mach-omap2/cm-regbits-44xx.h delete mode 100644 trunk/arch/arm/mach-omap2/cm44xx.h delete mode 100644 trunk/arch/arm/mach-omap2/dpll.c delete mode 100644 trunk/arch/arm/mach-omap2/i2c.c delete mode 100644 trunk/arch/arm/mach-omap2/mux.h delete mode 100644 trunk/arch/arm/mach-omap2/mux34xx.c delete mode 100644 trunk/arch/arm/mach-omap2/mux34xx.h delete mode 100644 trunk/arch/arm/mach-omap2/opp2420_data.c delete mode 100644 trunk/arch/arm/mach-omap2/opp2430_data.c delete mode 100644 trunk/arch/arm/mach-omap2/opp2xxx.h delete mode 100644 trunk/arch/arm/mach-omap2/prm-regbits-44xx.h delete mode 100644 trunk/arch/arm/mach-omap2/prm44xx.h delete mode 100644 trunk/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h delete mode 100644 trunk/arch/arm/mach-pxa/include/mach/zeus.h delete mode 100644 trunk/arch/arm/mach-pxa/zeus.c delete mode 100644 trunk/arch/arm/plat-omap/include/plat/clkdev_omap.h delete mode 100644 trunk/arch/arm/plat-omap/include/plat/i2c.h delete mode 100644 trunk/arch/powerpc/boot/dts/p1020rdb.dts delete mode 100644 trunk/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts delete mode 100644 trunk/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts delete mode 100644 trunk/arch/powerpc/boot/dts/p4080ds.dts delete mode 100644 trunk/arch/powerpc/include/asm/kvm_book3s.h delete mode 100644 trunk/arch/powerpc/include/asm/kvm_book3s_64_asm.h rename trunk/arch/powerpc/kernel/{proc_powerpc.c => proc_ppc64.c} (87%) delete mode 100644 trunk/arch/powerpc/kvm/book3s.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_32_mmu.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_emulate.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_exports.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_interrupts.S delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_mmu.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_mmu_host.c delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_rmhandlers.S delete mode 100644 trunk/arch/powerpc/kvm/book3s_64_slb.S delete mode 100644 trunk/arch/powerpc/mm/hugetlbpage-hash64.c delete mode 100644 trunk/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c delete mode 100644 trunk/arch/powerpc/platforms/85xx/corenet_ds.c delete mode 100644 trunk/arch/powerpc/platforms/85xx/corenet_ds.h delete mode 100644 trunk/arch/powerpc/platforms/85xx/p4080_ds.c delete mode 100644 trunk/arch/powerpc/platforms/pseries/dlpar.c delete mode 100644 trunk/arch/powerpc/platforms/pseries/offline_states.h rename trunk/arch/powerpc/{kernel => platforms/pseries}/rtasd.c (95%) delete mode 100644 trunk/arch/powerpc/sysdev/fsl_pmc.c delete mode 100644 trunk/drivers/ata/pata_macio.c create mode 100644 trunk/drivers/net/ehea/ehea_hcall.h delete mode 100644 trunk/drivers/spi/mpc52xx_spi.c create mode 100644 trunk/drivers/watchdog/mpc5200_wdt.c delete mode 100644 trunk/include/linux/spi/mpc52xx_spi.h diff --git a/[refs] b/[refs] index acac7a31ccbb..7a8400ede29b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bc7ecbcbc2c0ff235382077b55de7896775afc16 +refs/heads/master: d0d26c33b63c7ec10c3fdf9c7ce0aa035f0b3200 diff --git a/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu b/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu index 2aae06fcbed7..974e29f5da86 100644 --- a/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -62,21 +62,6 @@ Description: CPU topology files that describe kernel limits related to See Documentation/cputopology.txt for more information. -What: /sys/devices/system/cpu/probe - /sys/devices/system/cpu/release -Date: November 2009 -Contact: Linux kernel mailing list -Description: Dynamic addition and removal of CPU's. This is not hotplug - removal, this is meant complete removal/addition of the CPU - from the system. - - probe: writes to this file will dynamically add a CPU to the - system. Information written to the file to add CPU's is - architecture specific. - - release: writes to this file dynamically remove a CPU from - the system. Information writtento the file to remove CPU's - is architecture specific. What: /sys/devices/system/cpu/cpu#/node Date: October 2009 diff --git a/trunk/Documentation/ABI/testing/sysfs-kernel-slab b/trunk/Documentation/ABI/testing/sysfs-kernel-slab index 8b093f8222d3..6dcf75e594fb 100644 --- a/trunk/Documentation/ABI/testing/sysfs-kernel-slab +++ b/trunk/Documentation/ABI/testing/sysfs-kernel-slab @@ -45,9 +45,8 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The alloc_fastpath file shows how many objects have been - allocated using the fast path. It can be written to clear the - current count. + The alloc_fastpath file is read-only and specifies how many + objects have been allocated using the fast path. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/alloc_from_partial @@ -56,10 +55,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The alloc_from_partial file shows how many times a cpu slab has - been full and it has been refilled by using a slab from the list - of partially used slabs. It can be written to clear the current - count. + The alloc_from_partial file is read-only and specifies how + many times a cpu slab has been full and it has been refilled + by using a slab from the list of partially used slabs. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/alloc_refill @@ -68,9 +66,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The alloc_refill file shows how many times the per-cpu freelist - was empty but there were objects available as the result of - remote cpu frees. It can be written to clear the current count. + The alloc_refill file is read-only and specifies how many + times the per-cpu freelist was empty but there were objects + available as the result of remote cpu frees. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/alloc_slab @@ -79,9 +77,8 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The alloc_slab file is shows how many times a new slab had to - be allocated from the page allocator. It can be written to - clear the current count. + The alloc_slab file is read-only and specifies how many times + a new slab had to be allocated from the page allocator. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/alloc_slowpath @@ -90,10 +87,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The alloc_slowpath file shows how many objects have been - allocated using the slow path because of a refill or - allocation from a partial or new slab. It can be written to - clear the current count. + The alloc_slowpath file is read-only and specifies how many + objects have been allocated using the slow path because of a + refill or allocation from a partial or new slab. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/cache_dma @@ -121,11 +117,10 @@ KernelVersion: 2.6.31 Contact: Pekka Enberg , Christoph Lameter Description: - The file cpuslab_flush shows how many times a cache's cpu slabs - have been flushed as the result of destroying or shrinking a - cache, a cpu going offline, or as the result of forcing an - allocation from a certain node. It can be written to clear the - current count. + The file cpuslab_flush is read-only and specifies how many + times a cache's cpu slabs have been flushed as the result of + destroying or shrinking a cache, a cpu going offline, or as + the result of forcing an allocation from a certain node. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/ctor @@ -144,8 +139,8 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The deactivate_empty file shows how many times an empty cpu slab - was deactivated. It can be written to clear the current count. + The file deactivate_empty is read-only and specifies how many + times an empty cpu slab was deactivated. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/deactivate_full @@ -154,8 +149,8 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The deactivate_full file shows how many times a full cpu slab - was deactivated. It can be written to clear the current count. + The file deactivate_full is read-only and specifies how many + times a full cpu slab was deactivated. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/deactivate_remote_frees @@ -164,9 +159,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The deactivate_remote_frees file shows how many times a cpu slab - has been deactivated and contained free objects that were freed - remotely. It can be written to clear the current count. + The file deactivate_remote_frees is read-only and specifies how + many times a cpu slab has been deactivated and contained free + objects that were freed remotely. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/deactivate_to_head @@ -175,9 +170,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The deactivate_to_head file shows how many times a partial cpu - slab was deactivated and added to the head of its node's partial - list. It can be written to clear the current count. + The file deactivate_to_head is read-only and specifies how + many times a partial cpu slab was deactivated and added to the + head of its node's partial list. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/deactivate_to_tail @@ -186,9 +181,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The deactivate_to_tail file shows how many times a partial cpu - slab was deactivated and added to the tail of its node's partial - list. It can be written to clear the current count. + The file deactivate_to_tail is read-only and specifies how + many times a partial cpu slab was deactivated and added to the + tail of its node's partial list. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/destroy_by_rcu @@ -206,9 +201,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_add_partial file shows how many times an object has - been freed in a full slab so that it had to added to its node's - partial list. It can be written to clear the current count. + The file free_add_partial is read-only and specifies how many + times an object has been freed in a full slab so that it had to + added to its node's partial list. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/free_calls @@ -227,9 +222,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_fastpath file shows how many objects have been freed - using the fast path because it was an object from the cpu slab. - It can be written to clear the current count. + The free_fastpath file is read-only and specifies how many + objects have been freed using the fast path because it was an + object from the cpu slab. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/free_frozen @@ -238,9 +233,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_frozen file shows how many objects have been freed to - a frozen slab (i.e. a remote cpu slab). It can be written to - clear the current count. + The free_frozen file is read-only and specifies how many + objects have been freed to a frozen slab (i.e. a remote cpu + slab). Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/free_remove_partial @@ -249,10 +244,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_remove_partial file shows how many times an object has - been freed to a now-empty slab so that it had to be removed from - its node's partial list. It can be written to clear the current - count. + The file free_remove_partial is read-only and specifies how + many times an object has been freed to a now-empty slab so + that it had to be removed from its node's partial list. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/free_slab @@ -261,9 +255,8 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_slab file shows how many times an empty slab has been - freed back to the page allocator. It can be written to clear - the current count. + The free_slab file is read-only and specifies how many times an + empty slab has been freed back to the page allocator. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/free_slowpath @@ -272,9 +265,9 @@ KernelVersion: 2.6.25 Contact: Pekka Enberg , Christoph Lameter Description: - The free_slowpath file shows how many objects have been freed - using the slow path (i.e. to a full or partial slab). It can - be written to clear the current count. + The free_slowpath file is read-only and specifies how many + objects have been freed using the slow path (i.e. to a full or + partial slab). Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/hwcache_align @@ -353,10 +346,10 @@ KernelVersion: 2.6.26 Contact: Pekka Enberg , Christoph Lameter Description: - The order_fallback file shows how many times an allocation of a - new slab has not been possible at the cache's order and instead - fallen back to its minimum possible order. It can be written to - clear the current count. + The file order_fallback is read-only and specifies how many + times an allocation of a new slab has not been possible at the + cache's order and instead fallen back to its minimum possible + order. Available when CONFIG_SLUB_STATS is enabled. What: /sys/kernel/slab/cache/partial diff --git a/trunk/Documentation/cpu-hotplug.txt b/trunk/Documentation/cpu-hotplug.txt index 4d4a644b505e..9d620c153b04 100644 --- a/trunk/Documentation/cpu-hotplug.txt +++ b/trunk/Documentation/cpu-hotplug.txt @@ -49,12 +49,6 @@ maxcpus=n Restrict boot time cpus to n. Say if you have 4 cpus, using additional_cpus=n (*) Use this to limit hotpluggable cpus. This option sets cpu_possible_map = cpu_present_map + additional_cpus -cede_offline={"off","on"} Use this option to disable/enable putting offlined - processors to an extended H_CEDE state on - supported pseries platforms. - If nothing is specified, - cede_offline is set to "on". - (*) Option valid only for following architectures - ia64 diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index ab95d3ada5c7..3f886e298f62 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1787,11 +1787,6 @@ and is between 256 and 4096 characters. It is defined in the file waiting for the ACK, so if this is set too high interrupts *may* be lost! - omap_mux= [OMAP] Override bootloader pin multiplexing. - Format: ... - For example, to override I2C bus2: - omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100 - opl3= [HW,OSS] Format: diff --git a/trunk/Documentation/powerpc/dts-bindings/fsl/board.txt b/trunk/Documentation/powerpc/dts-bindings/fsl/board.txt index 39e941515a36..e8b5bc24d0ac 100644 --- a/trunk/Documentation/powerpc/dts-bindings/fsl/board.txt +++ b/trunk/Documentation/powerpc/dts-bindings/fsl/board.txt @@ -20,16 +20,12 @@ Required properities: - compatible : should be "fsl,fpga-pixis". - reg : should contain the address and the length of the FPPGA register set. -- interrupt-parent: should specify phandle for the interrupt controller. -- interrupts : should specify event (wakeup) IRQ. Example (MPC8610HPCD): board-control@e8000000 { compatible = "fsl,fpga-pixis"; reg = <0xe8000000 32>; - interrupt-parent = <&mpic>; - interrupts = <8 8>; }; * Freescale BCSR GPIO banks diff --git a/trunk/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt b/trunk/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt index 5c6602dbfdc2..cabc780f7258 100644 --- a/trunk/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt +++ b/trunk/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt @@ -103,22 +103,7 @@ fsl,mpc5200-gpt nodes --------------------- On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board design supports the internal wdt, then the device node for GPT0 should -include the empty property 'fsl,has-wdt'. Note that this does not activate -the watchdog. The timer will function as a GPT if the timer api is used, and -it will function as watchdog if the watchdog device is used. The watchdog -mode has priority over the gpt mode, i.e. if the watchdog is activated, any -gpt api call to this timer will fail with -EBUSY. - -If you add the property - fsl,wdt-on-boot = ; -GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it. -If n>0, the watchdog is started with a timeout of n seconds. If n=0, the -configuration of the watchdog is not touched. This is useful in two cases: -- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later; -- do not touch a configuration assigned by the boot loader which supervises - the boot process itself. - -The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option. +include the empty property 'fsl,has-wdt'. An mpc5200-gpt can be used as a single line GPIO controller. To do so, add the following properties to the gpt node: diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index cff133be42c6..d58fa703ec16 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -3260,7 +3260,6 @@ LINUX FOR IBM pSERIES (RS/6000) M: Paul Mackerras W: http://www.ibm.com/linux/ltc/projects/ppc S: Supported -F: arch/powerpc/boot/rs6000.h LINUX FOR POWERPC (32-BIT AND 64-BIT) M: Benjamin Herrenschmidt @@ -3269,24 +3268,18 @@ W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git S: Supported -F: Documentation/powerpc/ -F: arch/powerpc/ LINUX FOR POWER MACINTOSH M: Benjamin Herrenschmidt W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org S: Maintained -F: arch/powerpc/platforms/powermac/ -F: drivers/macintosh/ LINUX FOR POWERPC EMBEDDED MPC5XXX M: Grant Likely L: linuxppc-dev@ozlabs.org T: git git://git.secretlab.ca/git/linux-2.6.git S: Maintained -F: arch/powerpc/platforms/512x/ -F: arch/powerpc/platforms/52xx/ LINUX FOR POWERPC EMBEDDED PPC4XX M: Josh Boyer @@ -3295,8 +3288,6 @@ W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git S: Maintained -F: arch/powerpc/platforms/40x/ -F: arch/powerpc/platforms/44x/ LINUX FOR POWERPC EMBEDDED XILINX VIRTEX M: Grant Likely @@ -3304,8 +3295,6 @@ W: http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex L: linuxppc-dev@ozlabs.org T: git git://git.secretlab.ca/git/linux-2.6.git S: Maintained -F: arch/powerpc/*/*virtex* -F: arch/powerpc/*/*/*virtex* LINUX FOR POWERPC EMBEDDED PPC8XX M: Vitaly Bordug @@ -3319,16 +3308,12 @@ M: Kumar Gala W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org S: Maintained -F: arch/powerpc/platforms/83xx/ LINUX FOR POWERPC PA SEMI PWRFICIENT M: Olof Johansson W: http://www.pasemi.com/ L: linuxppc-dev@ozlabs.org S: Supported -F: arch/powerpc/platforms/pasemi/ -F: drivers/*/*pasemi* -F: drivers/*/*/*pasemi* LINUX SECURITY MODULE (LSM) FRAMEWORK M: Chris Wright diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index 5cb9326df7a7..ff54c23d085e 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -71,14 +71,6 @@ config DEBUG_LL in the kernel. This is helpful if you are debugging code that executes before the console is initialized. -config EARLY_PRINTK - bool "Early printk" - depends on DEBUG_LL - help - Say Y here if you want to have an early console using the - kernel low-level debugging functions. Add earlyprintk to your - kernel parameters to enable this console. - config DEBUG_ICEDCC bool "Kernel low-level debugging via EmbeddedICE DCC channel" depends on DEBUG_LL diff --git a/trunk/arch/arm/configs/htcherald_defconfig b/trunk/arch/arm/configs/htcherald_defconfig index 1b39691b816f..338267674075 100644 --- a/trunk/arch/arm/configs/htcherald_defconfig +++ b/trunk/arch/arm/configs/htcherald_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc8 -# Sat Dec 5 12:16:24 2009 +# Linux kernel version: 2.6.32-rc6 +# Sat Nov 14 10:56:01 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -198,9 +198,7 @@ CONFIG_ARCH_OMAP1=y # OMAP Feature Selections # # CONFIG_OMAP_RESET_CLOCKS is not set -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y +# CONFIG_OMAP_MUX is not set CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MBOX_FWK is not set CONFIG_OMAP_MPU_TIMER=y @@ -209,7 +207,6 @@ CONFIG_OMAP_LL_DEBUG_UART1=y # CONFIG_OMAP_LL_DEBUG_UART2 is not set # CONFIG_OMAP_LL_DEBUG_UART3 is not set # CONFIG_OMAP_LL_DEBUG_NONE is not set -CONFIG_OMAP_SERIAL_WAKE=y # CONFIG_OMAP_PM_NONE is not set CONFIG_OMAP_PM_NOOP=y diff --git a/trunk/arch/arm/configs/omap3_touchbook_defconfig b/trunk/arch/arm/configs/omap3_touchbook_defconfig deleted file mode 100644 index 7c8515e65c02..000000000000 --- a/trunk/arch/arm/configs/omap3_touchbook_defconfig +++ /dev/null @@ -1,2431 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc8 -# Fri Dec 4 16:02:17 2009 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=15 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set -# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -CONFIG_MACH_OMAP3_TOUCHBOOK=y -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=y -CONFIG_BT_HCIBTSDIO=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_BT_HCIBFUSB=y -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=1 -# CONFIG_CFG80211_DEBUGFS is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_LEDS is not set -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -# CONFIG_NET_ETHERNET is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_LIBERTAS is not set -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_AT76C50X_USB is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8187 is not set -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_P54_COMMON is not set -# CONFIG_ATH_COMMON is not set -# CONFIG_HOSTAP is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set -# CONFIG_RT2X00 is not set -# CONFIG_WL12XX is not set -# CONFIG_IWM is not set - -# -# WiMAX Wireless Broadband devices -# -# CONFIG_WIMAX_I2400M_USB is not set -# CONFIG_WIMAX_I2400M_SDIO is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_ATM_DRIVERS is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -CONFIG_BATTERY_BQ27x00=y -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -# CONFIG_TWL4030_CODEC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_OXU210HP_HCD=y -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_ATM is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -CONFIG_TWL4030_USB=y -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_W35UND is not set -# CONFIG_PRISM2_USB is not set -# CONFIG_ECHO is not set -# CONFIG_OTUS is not set -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Android -# - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=m -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=m -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=m -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=y -# CONFIG_CUSE is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -# CONFIG_CRAMFS is not set -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/arm/configs/omap_4430sdp_defconfig b/trunk/arch/arm/configs/omap_4430sdp_defconfig index 2319113c86bf..a464ca332a23 100644 --- a/trunk/arch/arm/configs/omap_4430sdp_defconfig +++ b/trunk/arch/arm/configs/omap_4430sdp_defconfig @@ -1,29 +1,26 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Sun Dec 6 23:37:45 2009 +# Linux kernel version: 2.6.30-rc7 +# Tue Jun 9 12:36:23 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_LOCKBREAK=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y # # General setup @@ -42,12 +39,11 @@ CONFIG_BSD_PROCESS_ACCT=y # # RCU Subsystem # -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_GROUP_SCHED=y @@ -56,7 +52,8 @@ CONFIG_FAIR_GROUP_SCHED=y CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_DEPRECATED=y is not set +# CONFIG_SYSFS_DEPRECATED_V2=y is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y @@ -73,6 +70,7 @@ CONFIG_UID16=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -85,10 +83,6 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -96,16 +90,13 @@ CONFIG_COMPAT_BRK=y CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# # CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y @@ -119,7 +110,7 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -CONFIG_LBDAF=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -140,7 +131,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # # System Type # -CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set @@ -152,10 +142,8 @@ CONFIG_MMU=y # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -178,13 +166,10 @@ CONFIG_MMU=y # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set # # TI OMAP Implementations @@ -205,12 +190,9 @@ CONFIG_ARCH_OMAP4=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set +CONFIG_OMAP_LL_DEBUG_UART1=y # CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y +# CONFIG_OMAP_LL_DEBUG_UART3 is not set # # OMAP Board Type @@ -225,7 +207,7 @@ CONFIG_CPU_32v6K=y CONFIG_CPU_V7=y CONFIG_CPU_32v7=y CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PABRT_IFAR=y CONFIG_CPU_CACHE_V7=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y @@ -240,10 +222,9 @@ CONFIG_CPU_CP15_MMU=y # CONFIG_ARM_THUMB is not set # CONFIG_ARM_THUMBEE is not set # CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_CPU_DCACHE_DISABLE=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_458693 is not set # CONFIG_ARM_ERRATA_460075 is not set @@ -264,20 +245,18 @@ CONFIG_ARM_GIC=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_NR_CPUS=2 # CONFIG_HOTPLUG_CPU is not set -# CONFIG_LOCAL_TIMERS is not set -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y +CONFIG_LOCAL_TIMERS=y +# CONFIG_PREEMPT is not set CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y +# CONFIG_OABI_COMPAT is not set # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -292,13 +271,10 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_UNEVICTABLE_LRU is not set CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options @@ -322,11 +298,9 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600 # # At least one emulation must be selected # -# CONFIG_FPE_NWFPE is not set -# CONFIG_FPE_FASTFPE is not set CONFIG_VFP=y CONFIG_VFPv3=y -CONFIG_NEON=y +# CONFIG_NEON is not set # # Userspace binary formats @@ -351,7 +325,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set @@ -369,7 +342,6 @@ CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set -# CONFIG_MG_DISK is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -383,7 +355,6 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set -# CONFIG_PHONE is not set # # Input device support @@ -456,11 +427,6 @@ CONFIG_HW_RANDOM=y # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set # CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -481,14 +447,11 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # - -# -# AC97 GPIO expanders: -# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -509,8 +472,21 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y # # Graphics support @@ -535,17 +511,14 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set # @@ -562,12 +535,9 @@ CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -631,6 +601,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set # # Partition Types @@ -702,24 +673,23 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DETECT_SOFTLOCKUP is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_DETECT_HUNG_TASK=y # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -738,22 +708,31 @@ CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_BRANCH_PROFILE_NONE is not set -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -775,6 +754,7 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD2=y @@ -816,13 +796,11 @@ CONFIG_CRYPTO_PCBC=m # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set # # Digest # CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set diff --git a/trunk/arch/arm/configs/omap_zoom2_defconfig b/trunk/arch/arm/configs/omap_zoom2_defconfig index 4b00a4306812..eef93627fb13 100644 --- a/trunk/arch/arm/configs/omap_zoom2_defconfig +++ b/trunk/arch/arm/configs/omap_zoom2_defconfig @@ -610,8 +610,7 @@ CONFIG_INPUT_EVDEV=y # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_TWL4030=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set diff --git a/trunk/arch/arm/configs/omap_zoom3_defconfig b/trunk/arch/arm/configs/omap_zoom3_defconfig index 0d7e37a3651b..f0e7d0f85582 100644 --- a/trunk/arch/arm/configs/omap_zoom3_defconfig +++ b/trunk/arch/arm/configs/omap_zoom3_defconfig @@ -629,8 +629,7 @@ CONFIG_INPUT_EVDEV=y # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_TWL4030=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set diff --git a/trunk/arch/arm/configs/zeus_defconfig b/trunk/arch/arm/configs/zeus_defconfig deleted file mode 100644 index 823b11e7091a..000000000000 --- a/trunk/arch/arm/configs/zeus_defconfig +++ /dev/null @@ -1,2032 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Tue Dec 8 20:27:05 2009 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_MTD_XIP=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -# CONFIG_TREE_RCU is not set -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_TINY_RCU=y -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=13 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_NET_NS is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -# CONFIG_EMBEDDED is not set -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_IOSCHED_CFQ is not set -CONFIG_DEFAULT_DEADLINE=y -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="deadline" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -CONFIG_ARCH_PXA=y -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# Intel PXA2xx/PXA3xx Implementations -# - -# -# Intel/Marvell Dev Platforms (sorted by hardware release time) -# -# CONFIG_ARCH_LUBBOCK is not set -# CONFIG_MACH_MAINSTONE is not set -# CONFIG_MACH_ZYLONITE300 is not set -# CONFIG_MACH_ZYLONITE320 is not set -# CONFIG_MACH_LITTLETON is not set -# CONFIG_MACH_TAVOREVB is not set -# CONFIG_MACH_SAAR is not set - -# -# Third Party Dev Platforms (sorted by vendor name) -# -# CONFIG_ARCH_PXA_IDP is not set -# CONFIG_ARCH_VIPER is not set -CONFIG_MACH_ARCOM_ZEUS=y -# CONFIG_MACH_BALLOON3 is not set -# CONFIG_MACH_CSB726 is not set -# CONFIG_MACH_ARMCORE is not set -# CONFIG_MACH_EM_X270 is not set -# CONFIG_MACH_EXEDA is not set -# CONFIG_MACH_CM_X300 is not set -# CONFIG_ARCH_GUMSTIX is not set -# CONFIG_MACH_INTELMOTE2 is not set -# CONFIG_MACH_STARGATE2 is not set -# CONFIG_MACH_XCEP is not set -# CONFIG_TRIZEPS_PXA is not set -CONFIG_ARCOM_PCMCIA=y -# CONFIG_MACH_LOGICPD_PXA270 is not set -# CONFIG_MACH_PCM027 is not set -# CONFIG_MACH_COLIBRI is not set -# CONFIG_MACH_COLIBRI300 is not set -# CONFIG_MACH_COLIBRI320 is not set - -# -# End-user Products (sorted by vendor name) -# -# CONFIG_MACH_H4700 is not set -# CONFIG_MACH_H5000 is not set -# CONFIG_MACH_HIMALAYA is not set -# CONFIG_MACH_MAGICIAN is not set -# CONFIG_MACH_MIOA701 is not set -# CONFIG_PXA_EZX is not set -# CONFIG_MACH_MP900C is not set -# CONFIG_ARCH_PXA_PALM is not set -# CONFIG_PXA_SHARPSL is not set -# CONFIG_ARCH_PXA_ESERIES is not set -CONFIG_PXA27x=y -CONFIG_PXA_SSP=y -CONFIG_PXA_HAVE_BOARD_IRQS=y -CONFIG_PXA_HAVE_ISA_IRQS=y -CONFIG_PLAT_PXA=y - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_XSCALE=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_CPU_DCACHE_DISABLE is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_IWMMXT=y -CONFIG_XSCALE_PMU=y -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -CONFIG_ISA=y -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCCARD=m -CONFIG_PCMCIA=m -CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_IOCTL=y - -# -# PC-card bridges -# -# CONFIG_I82365 is not set -# CONFIG_TCIC is not set -CONFIG_PCMCIA_SOC_COMMON=m -CONFIG_PCMCIA_PXA2XX=m -# CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA_PROBE=y - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_FREQ_STAT_DETAILS is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_APM_EMULATION=y -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=m -CONFIG_BT_L2CAP=m -# CONFIG_BT_SCO is not set -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -# CONFIG_BT_BNEP_MC_FILTER is not set -# CONFIG_BT_BNEP_PROTO_FILTER is not set -# CONFIG_BT_HIDP is not set - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTSDIO is not set -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIDTL1 is not set -# CONFIG_BT_HCIBT3C is not set -# CONFIG_BT_HCIBLUECARD is not set -# CONFIG_BT_HCIBTUART is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_MINSTREL=y -# CONFIG_MAC80211_RC_DEFAULT_PID is not set -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT="minstrel" -# CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_LEDS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_GEN_PROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -CONFIG_MTD_RAM=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set - -# -# Mapping drivers for chip access -# -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -CONFIG_MTD_PXA2XX=y -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_IMPA7 is not set -# CONFIG_MTD_GPIO_ADDR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -# CONFIG_PNP is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -CONFIG_EEPROM_AT24=m -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_IWMC3200TOP is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=m -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -CONFIG_ATA=m -# CONFIG_ATA_NONSTANDARD is not set -CONFIG_ATA_VERBOSE_ERROR=y -# CONFIG_SATA_PMP is not set -CONFIG_ATA_SFF=y -# CONFIG_SATA_MV is not set -# CONFIG_PATA_LEGACY is not set -CONFIG_PATA_PCMCIA=m -# CONFIG_PATA_QDI is not set -# CONFIG_PATA_WINBOND_VLB is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_SMC91X is not set -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=4 -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_DNET is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_NET_PCI is not set -# CONFIG_B44 is not set -# CONFIG_CS89x0 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_TR is not set -CONFIG_WLAN=y -# CONFIG_PCMCIA_RAYCS is not set -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_ATMEL is not set -# CONFIG_AT76C50X_USB is not set -# CONFIG_AIRO_CS is not set -# CONFIG_PCMCIA_WL3501 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8187 is not set -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_HOSTAP is not set -# CONFIG_IWM is not set -# CONFIG_LIBERTAS is not set -CONFIG_HERMES=m -CONFIG_HERMES_CACHE_FW_ON_INIT=y -CONFIG_PCMCIA_HERMES=m -# CONFIG_PCMCIA_SPECTRUM is not set -# CONFIG_P54_COMMON is not set -CONFIG_RT2X00=m -# CONFIG_RT2500USB is not set -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -# CONFIG_WL12XX is not set -# CONFIG_ZD1211RW is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -CONFIG_NET_PCMCIA=y -# CONFIG_PCMCIA_3C589 is not set -# CONFIG_PCMCIA_3C574 is not set -# CONFIG_PCMCIA_FMVJ18X is not set -# CONFIG_PCMCIA_PCNET is not set -# CONFIG_PCMCIA_NMCLAN is not set -# CONFIG_PCMCIA_SMC91C92 is not set -# CONFIG_PCMCIA_XIRC2PS is not set -# CONFIG_PCMCIA_AXNET is not set -# CONFIG_WAN is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -# CONFIG_PPP_MPPE is not set -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -# CONFIG_SLIP is not set -CONFIG_SLHC=m -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -CONFIG_TOUCHSCREEN_FUJITSU=m -# CONFIG_TOUCHSCREEN_GUNZE is not set -CONFIG_TOUCHSCREEN_ELO=m -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_INEXIO=m -# CONFIG_TOUCHSCREEN_MK712 is not set -CONFIG_TOUCHSCREEN_HTCPEN=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -# CONFIG_TOUCHSCREEN_WM97XX is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -CONFIG_TOUCHSCREEN_TOUCHIT213=m -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_UINPUT=m -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_CS is not set -CONFIG_SERIAL_8250_NR_UARTS=7 -CONFIG_SERIAL_8250_RUNTIME_UARTS=7 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_PXA is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=m -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# PCMCIA character devices -# -# CONFIG_SYNCLINK_CS is not set -# CONFIG_CARDMAN_4000 is not set -# CONFIG_CARDMAN_4040 is not set -# CONFIG_IPWIRELESS is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set - -# -# I2C Algorithms -# -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -CONFIG_I2C_GPIO=y -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_PXA=y -# CONFIG_I2C_PXA_SLAVE is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_PXA2XX=y - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -CONFIG_GPIO_PCA953X=y -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -CONFIG_SENSORS_LM75=m -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SA1100_WATCHDOG is not set - -# -# ISA-based Watchdog Cards -# -# CONFIG_PCWATCHDOG is not set -# CONFIG_MIXCOMWD is not set -# CONFIG_WDT is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_UCB1400_CORE is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_PXA=m -# CONFIG_FB_PXA_OVERLAY is not set -# CONFIG_FB_PXA_SMARTPANEL is not set -CONFIG_FB_PXA_PARAMETERS=y -# CONFIG_FB_MBX is not set -# CONFIG_FB_W100 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -# CONFIG_LCD_PLATFORM is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=m -CONFIG_BACKLIGHT_GENERIC=m - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=m -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=m -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_VMASTER=y -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_AC97_POWER_SAVE is not set -CONFIG_SND_ARM=y -CONFIG_SND_PXA2XX_PCM=m -CONFIG_SND_PXA2XX_LIB=m -CONFIG_SND_PXA2XX_LIB_AC97=y -CONFIG_SND_PXA2XX_AC97=m -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_SND_SOC_I2C_AND_SPI=m -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_AC97_BUS=m -# CONFIG_HID_SUPPORT is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -CONFIG_USB_OHCI_HCD=m -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_EZUSB is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -CONFIG_USB_SERIAL_MCT_U232=m -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -CONFIG_USB_GADGET_PXA27X=y -CONFIG_USB_PXA27X=m -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_MMC_PXA=y -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -CONFIG_RTC_DRV_ISL1208=m -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_SA1100 is not set -CONFIG_RTC_DRV_PXA=m -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -CONFIG_NLS_CODEPAGE_850=m -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=m -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -CONFIG_NLS_ISO8859_15=m -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=m -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=m -CONFIG_CRYPTO_ALGAPI2=m -CONFIG_CRYPTO_AEAD2=m -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_BLKCIPHER2=m -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_HASH2=m -CONFIG_CRYPTO_RNG2=m -CONFIG_CRYPTO_PCOMP=m -CONFIG_CRYPTO_MANAGER=m -CONFIG_CRYPTO_MANAGER2=m -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=m -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=m -CONFIG_CRC16=m -CONFIG_CRC_T10DIF=m -CONFIG_CRC_ITU_T=m -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index dd00f747e2ad..e7ccf7e697ce 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -54,6 +54,5 @@ endif head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o extra-y := $(head-y) init_task.o vmlinux.lds diff --git a/trunk/arch/arm/kernel/early_printk.c b/trunk/arch/arm/kernel/early_printk.c deleted file mode 100644 index 85aa2b292692..000000000000 --- a/trunk/arch/arm/kernel/early_printk.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * linux/arch/arm/kernel/early_printk.c - * - * Copyright (C) 2009 Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -extern void printch(int); - -static void early_write(const char *s, unsigned n) -{ - while (n-- > 0) { - if (*s == '\n') - printch('\r'); - printch(*s); - s++; - } -} - -static void early_console_write(struct console *con, const char *s, unsigned n) -{ - early_write(s, n); -} - -static struct console early_console = { - .name = "earlycon", - .write = early_console_write, - .flags = CON_PRINTBUFFER | CON_BOOT, - .index = -1, -}; - -asmlinkage void early_printk(const char *fmt, ...) -{ - char buf[512]; - int n; - va_list ap; - - va_start(ap, fmt); - n = vscnprintf(buf, sizeof(buf), fmt, ap); - early_write(buf, n); - va_end(ap); -} - -static int __init setup_early_printk(char *buf) -{ - register_console(&early_console); - return 0; -} - -early_param("earlyprintk", setup_early_printk); diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index ea02a7b1c244..a73a34dccf2a 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -160,7 +160,6 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) /* Make sure our local interrupt controller has this enabled */ local_irq_save(flags); - irq_to_desc(clk->irq)->status |= IRQ_NOPROBE; get_irq_chip(clk->irq)->unmask(clk->irq); local_irq_restore(flags); diff --git a/trunk/arch/arm/mach-ixp4xx/Kconfig b/trunk/arch/arm/mach-ixp4xx/Kconfig index 9e5070da17ae..264f4d59f898 100644 --- a/trunk/arch/arm/mach-ixp4xx/Kconfig +++ b/trunk/arch/arm/mach-ixp4xx/Kconfig @@ -179,21 +179,21 @@ config IXP4XX_INDIRECT_PCI help IXP4xx provides two methods of accessing PCI memory space: - 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). + 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). To access PCI via this space, we simply ioremap() the BAR into the kernel and we can use the standard read[bwl]/write[bwl] macros. This is the preferred method due to speed but it - limits the system to just 64MB of PCI memory. This can be + limits the system to just 64MB of PCI memory. This can be problematic if using video cards and other memory-heavy devices. - - 2) If > 64MB of memory space is required, the IXP4xx can be - configured to use indirect registers to access the whole PCI - memory space. This currently allows for up to 1 GB (0x10000000 - to 0x4FFFFFFF) of memory on the bus. The disadvantage of this - is that every PCI access requires three local register accesses - plus a spinlock, but in some cases the performance hit is - acceptable. In addition, you cannot mmap() PCI devices in this - case due to the indirect nature of the PCI window. + + 2) If > 64MB of memory space is required, the IXP4xx can be + configured to use indirect registers to access PCI This allows + for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. + The disadvantage of this is that every PCI access requires + three local register accesses plus a spinlock, but in some + cases the performance hit is acceptable. In addition, you cannot + mmap() PCI devices in this case due to the indirect nature + of the PCI window. By default, the direct method is used. Choose this option if you need to use the indirect method instead. If you don't know diff --git a/trunk/arch/arm/mach-ixp4xx/avila-pci.c b/trunk/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b500548..08d65dcdb5fe 100644 --- a/trunk/arch/arm/mach-ixp4xx/avila-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/avila-pci.c @@ -22,45 +22,40 @@ #include #include #include + #include #include #include #include -#define AVILA_MAX_DEV 4 -#define LOFT_MAX_DEV 6 -#define IRQ_LINES 4 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 11 -#define INTB 10 -#define INTC 9 -#define INTD 8 - void __init avila_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[IRQ_LINES] = { - IXP4XX_GPIO_IRQ(INTA), - IXP4XX_GPIO_IRQ(INTB), - IXP4XX_GPIO_IRQ(INTC), - IXP4XX_GPIO_IRQ(INTD) + static int pci_irq_table[AVILA_PCI_IRQ_LINES] = { + IRQ_AVILA_PCI_INTA, + IRQ_AVILA_PCI_INTB, + IRQ_AVILA_PCI_INTC, + IRQ_AVILA_PCI_INTD }; + int irq = -1; + if (slot >= 1 && - slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && - pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[(slot + pin - 2) % 4]; + slot <= (machine_is_loft() ? LOFT_PCI_MAX_DEV : AVILA_PCI_MAX_DEV) && + pin >= 1 && pin <= AVILA_PCI_IRQ_LINES) { + irq = pci_irq_table[(slot + pin - 2) % 4]; + } - return -1; + return irq; } struct hw_pci avila_pci __initdata = { @@ -80,3 +75,4 @@ int __init avila_pci_init(void) } subsys_initcall(avila_pci_init); + diff --git a/trunk/arch/arm/mach-ixp4xx/avila-setup.c b/trunk/arch/arm/mach-ixp4xx/avila-setup.c index 6e558a76457d..797995ce18b9 100644 --- a/trunk/arch/arm/mach-ixp4xx/avila-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/avila-setup.c @@ -19,6 +19,7 @@ #include #include #include + #include #include #include @@ -28,9 +29,6 @@ #include #include -#define AVILA_SDA_PIN 7 -#define AVILA_SCL_PIN 6 - static struct flash_platform_data avila_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/common-pci.c b/trunk/arch/arm/mach-ixp4xx/common-pci.c index c4a01594c761..70afcfe5b881 100644 --- a/trunk/arch/arm/mach-ixp4xx/common-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/common-pci.c @@ -481,7 +481,11 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) res[1].name = "PCI Memory Space"; res[1].start = PCIBIOS_MIN_MEM; - res[1].end = PCIBIOS_MAX_MEM; +#ifndef CONFIG_IXP4XX_INDIRECT_PCI + res[1].end = 0x4bffffff; +#else + res[1].end = 0x4fffffff; +#endif res[1].flags = IORESOURCE_MEM; request_resource(&ioport_resource, &res[0]); diff --git a/trunk/arch/arm/mach-ixp4xx/common.c b/trunk/arch/arm/mach-ixp4xx/common.c index 3bbf40f6d964..cfd52fb341cb 100644 --- a/trunk/arch/arm/mach-ixp4xx/common.c +++ b/trunk/arch/arm/mach-ixp4xx/common.c @@ -117,7 +117,7 @@ int gpio_to_irq(int gpio) } EXPORT_SYMBOL(gpio_to_irq); -int irq_to_gpio(unsigned int irq) +int irq_to_gpio(int irq) { int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; diff --git a/trunk/arch/arm/mach-ixp4xx/coyote-pci.c b/trunk/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8bd6f0..efddf01ed17b 100644 --- a/trunk/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/coyote-pci.c @@ -18,31 +18,27 @@ #include #include #include + #include #include #include -#include - -#define SLOT0_DEVID 14 -#define SLOT1_DEVID 15 -/* PCI controller GPIO to IRQ pin mappings */ -#define SLOT0_INTA 6 -#define SLOT1_INTA 11 +#include void __init coyote_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - if (slot == SLOT0_DEVID) - return IXP4XX_GPIO_IRQ(SLOT0_INTA); - else if (slot == SLOT1_DEVID) - return IXP4XX_GPIO_IRQ(SLOT1_INTA); + if (slot == COYOTE_PCI_SLOT0_DEVID) + return IRQ_COYOTE_PCI_SLOT0; + else if (slot == COYOTE_PCI_SLOT1_DEVID) + return IRQ_COYOTE_PCI_SLOT1; else return -1; } diff --git a/trunk/arch/arm/mach-ixp4xx/coyote-setup.c b/trunk/arch/arm/mach-ixp4xx/coyote-setup.c index 25bf5ad770ea..aab1954e2747 100644 --- a/trunk/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/coyote-setup.c @@ -25,15 +25,6 @@ #include #include -#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) -#define COYOTE_IDE_BASE_VIRT 0xFFFE1000 -#define COYOTE_IDE_REGION_SIZE 0x1000 - -#define COYOTE_IDE_DATA_PORT 0xFFFE10E0 -#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC -#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 -#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 - static struct flash_platform_data coyote_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/dsmg600-pci.c b/trunk/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed462ba..926d15f885fb 100644 --- a/trunk/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -19,45 +19,39 @@ #include #include #include + #include #include -#define MAX_DEV 4 -#define IRQ_LINES 3 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 11 -#define INTB 10 -#define INTC 9 -#define INTD 8 -#define INTE 7 -#define INTF 6 - void __init dsmg600_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[MAX_DEV][IRQ_LINES] = { - { IXP4XX_GPIO_IRQ(INTE), -1, -1 }, - { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, - { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), - IXP4XX_GPIO_IRQ(INTD) }, - { IXP4XX_GPIO_IRQ(INTF), -1, -1 }, + static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] = + { + { IRQ_DSMG600_PCI_INTE, -1, -1 }, + { IRQ_DSMG600_PCI_INTA, -1, -1 }, + { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD }, + { IRQ_DSMG600_PCI_INTF, -1, -1 }, }; - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[slot - 1][pin - 1]; + int irq = -1; + + if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV && + pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES) + irq = pci_irq_table[slot-1][pin-1]; - return -1; + return irq; } struct hw_pci __initdata dsmg600_pci = { diff --git a/trunk/arch/arm/mach-ixp4xx/dsmg600-setup.c b/trunk/arch/arm/mach-ixp4xx/dsmg600-setup.c index 7c1fa54a6145..a51bfa6978b6 100644 --- a/trunk/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -33,23 +33,6 @@ #include #include -#define DSMG600_SDA_PIN 5 -#define DSMG600_SCL_PIN 4 - -/* DSM-G600 Timer Setting */ -#define DSMG600_FREQ 66000000 - -/* Buttons */ -#define DSMG600_PB_GPIO 15 /* power button */ -#define DSMG600_RB_GPIO 3 /* reset button */ - -/* Power control */ -#define DSMG600_PO_GPIO 2 /* power off */ - -/* LEDs */ -#define DSMG600_LED_PWR_GPIO 0 -#define DSMG600_LED_WLAN_GPIO 14 - static struct flash_platform_data dsmg600_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/fsg-pci.c b/trunk/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c930624..ca12a9ca0830 100644 --- a/trunk/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/fsg-pci.c @@ -19,38 +19,33 @@ #include #include #include + #include #include -#define MAX_DEV 3 -#define IRQ_LINES 3 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 6 -#define INTB 7 -#define INTC 5 - void __init fsg_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[IRQ_LINES] = { - IXP4XX_GPIO_IRQ(INTC), - IXP4XX_GPIO_IRQ(INTB), - IXP4XX_GPIO_IRQ(INTA), + static int pci_irq_table[FSG_PCI_IRQ_LINES] = { + IRQ_FSG_PCI_INTC, + IRQ_FSG_PCI_INTB, + IRQ_FSG_PCI_INTA, }; int irq = -1; - slot -= 11; + slot = slot - 11; - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - irq = pci_irq_table[slot - 1]; + if (slot >= 1 && slot <= FSG_PCI_MAX_DEV && + pin >= 1 && pin <= FSG_PCI_IRQ_LINES) + irq = pci_irq_table[(slot - 1)]; printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, irq); diff --git a/trunk/arch/arm/mach-ixp4xx/fsg-setup.c b/trunk/arch/arm/mach-ixp4xx/fsg-setup.c index e7f4befba422..5add22fc9899 100644 --- a/trunk/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/fsg-setup.c @@ -24,18 +24,12 @@ #include #include #include + #include #include #include #include -#define FSG_SDA_PIN 12 -#define FSG_SCL_PIN 13 - -#define FSG_SB_GPIO 4 /* sync button */ -#define FSG_RB_GPIO 9 /* reset button */ -#define FSG_UB_GPIO 10 /* usb button */ - static struct flash_platform_data fsg_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c b/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c index 1c28048209c1..a733b8ff3cec 100644 --- a/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/trunk/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -17,28 +17,29 @@ #include #include +#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) +#define gpio_irq(n) xgpio_irq(n) + #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ #define SLOT_NEC 0x0E /* IDSEL = AD18 */ +#define IRQ_ETHA IRQ_IXP4XX_GPIO4 +#define IRQ_ETHB IRQ_IXP4XX_GPIO5 +#define IRQ_NEC IRQ_IXP4XX_GPIO3 +#define IRQ_MPCI IRQ_IXP4XX_GPIO12 + /* GPIO lines */ #define GPIO_SCL 0 #define GPIO_SDA 1 #define GPIO_STR 2 -#define GPIO_IRQ_NEC 3 -#define GPIO_IRQ_ETHA 4 -#define GPIO_IRQ_ETHB 5 #define GPIO_HSS0_DCD_N 6 #define GPIO_HSS1_DCD_N 7 -#define GPIO_UART0_DCD 8 -#define GPIO_UART1_DCD 9 #define GPIO_HSS0_CTS_N 10 #define GPIO_HSS1_CTS_N 11 -#define GPIO_IRQ_MPCI 12 #define GPIO_HSS1_RTS_N 13 #define GPIO_HSS0_RTS_N 14 -/* GPIO15 is not connected */ /* Control outputs from 74HC4094 */ #define CONTROL_HSS0_CLK_INT 0 @@ -151,7 +152,7 @@ static int hss_set_clock(int port, unsigned int clock_type) static irqreturn_t hss_dcd_irq(int irq, void *pdev) { - int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); + int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); set_carrier_cb_tab[port](pdev, !i); return IRQ_HANDLED; @@ -164,9 +165,9 @@ static int hss_open(int port, void *pdev, int i, irq; if (!port) - irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); + irq = gpio_irq(GPIO_HSS0_DCD_N); else - irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); + irq = gpio_irq(GPIO_HSS1_DCD_N); gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); set_carrier_cb(pdev, !i); @@ -187,8 +188,8 @@ static int hss_open(int port, void *pdev, static void hss_close(int port, void *pdev) { - free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : - IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); + free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), + pdev); set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); @@ -420,8 +421,8 @@ static void __init gmlr_init(void) gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1); @@ -441,10 +442,10 @@ static void __init gmlr_init(void) #ifdef CONFIG_PCI static void __init gmlr_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } @@ -465,10 +466,10 @@ static void __init gmlr_pci_postinit(void) static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { switch(slot) { - case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); - case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); - case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); - default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); + case SLOT_ETHA: return IRQ_ETHA; + case SLOT_ETHB: return IRQ_ETHB; + case SLOT_NEC: return IRQ_NEC; + default: return IRQ_MPCI; } } diff --git a/trunk/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/trunk/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c333c204..7b8a2c323840 100644 --- a/trunk/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -26,16 +26,14 @@ #include #include #include + #include #include +#include #include -#define SLOT0_DEVID 0 -#define SLOT1_DEVID 1 -#define INTA 10 /* slot 1 has INTA and INTB crossed */ -#define INTB 11 - /* + * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h * Slot 0 isn't actually populated with a card connector but * we initialize it anyway in case a future version has the * slot populated or someone with good soldering skills has @@ -43,26 +41,32 @@ */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - int rc = -1; + int rc; + static int gtwx5715_irqmap + [GTWX5715_PCI_SLOT_COUNT] + [GTWX5715_PCI_INT_PIN_COUNT] = { + {GTWX5715_PCI_SLOT0_INTA_IRQ, GTWX5715_PCI_SLOT0_INTB_IRQ}, + {GTWX5715_PCI_SLOT1_INTA_IRQ, GTWX5715_PCI_SLOT1_INTB_IRQ}, +}; - if ((slot == SLOT0_DEVID && pin == 1) || - (slot == SLOT1_DEVID && pin == 2)) - rc = IXP4XX_GPIO_IRQ(INTA); - else if ((slot == SLOT0_DEVID && pin == 2) || - (slot == SLOT1_DEVID && pin == 1)) - rc = IXP4XX_GPIO_IRQ(INTB); + if (slot >= GTWX5715_PCI_SLOT_COUNT || + pin >= GTWX5715_PCI_INT_PIN_COUNT) rc = -1; + else + rc = gtwx5715_irqmap[slot][pin-1]; - printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", - __func__, slot, pin, rc); - return rc; + printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc); + return(rc); } struct hw_pci gtwx5715_pci __initdata = { @@ -77,7 +81,9 @@ struct hw_pci gtwx5715_pci __initdata = { int __init gtwx5715_pci_init(void) { if (machine_is_gtwx5715()) + { pci_common_init(>wx5715_pci); + } return 0; } diff --git a/trunk/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/trunk/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 0bc7185cb6f7..25c21d6665ec 100644 --- a/trunk/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -28,6 +28,7 @@ #include #include #include + #include #include #include @@ -36,34 +37,7 @@ #include #include #include - -/* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch - and operate as an SPI type interface. The details of the interface - are available on Kendin/Micrel's web site. */ - -#define GTWX5715_KSSPI_SELECT 5 -#define GTWX5715_KSSPI_TXD 6 -#define GTWX5715_KSSPI_CLOCK 7 -#define GTWX5715_KSSPI_RXD 12 - -/* The "reset" button is wired to GPIO 3. - The GPIO is brought "low" when the button is pushed. */ - -#define GTWX5715_BUTTON_GPIO 3 - -/* Board Label Front Label - LED1 Power - LED2 Wireless-G - LED3 not populated but could be - LED4 Internet - LED5 - LED8 Controlled by KS8995M Switch - LED9 DMZ */ - -#define GTWX5715_LED1_GPIO 2 -#define GTWX5715_LED2_GPIO 9 -#define GTWX5715_LED3_GPIO 8 -#define GTWX5715_LED4_GPIO 1 -#define GTWX5715_LED9_GPIO 4 +#include /* * Xscale UART registers are 32 bits wide with only the least diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/avila.h b/trunk/arch/arm/mach-ixp4xx/include/mach/avila.h new file mode 100644 index 000000000000..1640cb61972b --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/avila.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/avila.h + * + * Gateworks Avila platform specific definitions + * + * Author: Michael-Luke Jones + * + * Based on ixdp425.h + * Author: Deepak Saxena + * + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define AVILA_SDA_PIN 7 +#define AVILA_SCL_PIN 6 + +/* + * AVILA PCI IRQs + */ +#define AVILA_PCI_MAX_DEV 4 +#define LOFT_PCI_MAX_DEV 6 +#define AVILA_PCI_IRQ_LINES 4 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define AVILA_PCI_INTA_PIN 11 +#define AVILA_PCI_INTB_PIN 10 +#define AVILA_PCI_INTC_PIN 9 +#define AVILA_PCI_INTD_PIN 8 + + diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/coyote.h b/trunk/arch/arm/mach-ixp4xx/include/mach/coyote.h new file mode 100644 index 000000000000..717ac6d16f55 --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/coyote.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/coyote.h + * + * ADI Engineering platform specific definitions + * + * Author: Deepak Saxena + * + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +/* PCI controller GPIO to IRQ pin mappings */ +#define COYOTE_PCI_SLOT0_PIN 6 +#define COYOTE_PCI_SLOT1_PIN 11 + +#define COYOTE_PCI_SLOT0_DEVID 14 +#define COYOTE_PCI_SLOT1_DEVID 15 + +#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) +#define COYOTE_IDE_BASE_VIRT 0xFFFE1000 +#define COYOTE_IDE_REGION_SIZE 0x1000 + +#define COYOTE_IDE_DATA_PORT 0xFFFE10E0 +#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC +#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 + diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/trunk/arch/arm/mach-ixp4xx/include/mach/dsmg600.h new file mode 100644 index 000000000000..dc087a34a268 --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/dsmg600.h @@ -0,0 +1,52 @@ +/* + * DSM-G600 platform specific definitions + * + * Copyright (C) 2006 Tower Technologies + * Author: Alessandro Zummo + * + * based on ixdp425.h: + * Copyright 2004 (C) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define DSMG600_SDA_PIN 5 +#define DSMG600_SCL_PIN 4 + +/* + * DSMG600 PCI IRQs + */ +#define DSMG600_PCI_MAX_DEV 4 +#define DSMG600_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define DSMG600_PCI_INTA_PIN 11 +#define DSMG600_PCI_INTB_PIN 10 +#define DSMG600_PCI_INTC_PIN 9 +#define DSMG600_PCI_INTD_PIN 8 +#define DSMG600_PCI_INTE_PIN 7 +#define DSMG600_PCI_INTF_PIN 6 + +/* DSM-G600 Timer Setting */ +#define DSMG600_FREQ 66000000 + +/* Buttons */ + +#define DSMG600_PB_GPIO 15 /* power button */ +#define DSMG600_RB_GPIO 3 /* reset button */ + +/* Power control */ + +#define DSMG600_PO_GPIO 2 /* power off */ + +/* LEDs */ + +#define DSMG600_LED_PWR_GPIO 0 +#define DSMG600_LED_WLAN_GPIO 14 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/fsg.h b/trunk/arch/arm/mach-ixp4xx/include/mach/fsg.h new file mode 100644 index 000000000000..1f02b7e22a13 --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/fsg.h @@ -0,0 +1,50 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/fsg.h + * + * Freecom FSG-3 platform specific definitions + * + * Author: Rod Whitby + * Author: Tomasz Chmielewski + * Maintainers: http://www.nslu2-linux.org + * + * Based on coyote.h by + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define FSG_SDA_PIN 12 +#define FSG_SCL_PIN 13 + +/* + * FSG PCI IRQs + */ +#define FSG_PCI_MAX_DEV 3 +#define FSG_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define FSG_PCI_INTA_PIN 6 +#define FSG_PCI_INTB_PIN 7 +#define FSG_PCI_INTC_PIN 5 + +/* Buttons */ + +#define FSG_SB_GPIO 4 /* sync button */ +#define FSG_RB_GPIO 9 /* reset button */ +#define FSG_UB_GPIO 10 /* usb button */ + +/* LEDs */ + +#define FSG_LED_WLAN_BIT 0 +#define FSG_LED_WAN_BIT 1 +#define FSG_LED_SATA_BIT 2 +#define FSG_LED_USB_BIT 4 +#define FSG_LED_RING_BIT 5 +#define FSG_LED_SYNC_BIT 7 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h b/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h index a5f87ded2f28..cd5aec26c072 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/gpio.h @@ -70,7 +70,7 @@ static inline void gpio_set_value(unsigned gpio, int value) #include /* cansleep wrappers */ extern int gpio_to_irq(int gpio); -extern int irq_to_gpio(unsigned int irq); +extern int irq_to_gpio(int gpio); #endif diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/trunk/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h new file mode 100644 index 000000000000..5d5e201cac7e --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h @@ -0,0 +1,116 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h + * + * Gemtek GTWX5715 Gateway (Linksys WRV54G) + * + * Copyright 2004 (c) George T. Joseph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif +#include "irqs.h" + +#define GTWX5715_GPIO0 0 +#define GTWX5715_GPIO1 1 +#define GTWX5715_GPIO2 2 +#define GTWX5715_GPIO3 3 +#define GTWX5715_GPIO4 4 +#define GTWX5715_GPIO5 5 +#define GTWX5715_GPIO6 6 +#define GTWX5715_GPIO7 7 +#define GTWX5715_GPIO8 8 +#define GTWX5715_GPIO9 9 +#define GTWX5715_GPIO10 10 +#define GTWX5715_GPIO11 11 +#define GTWX5715_GPIO12 12 +#define GTWX5715_GPIO13 13 +#define GTWX5715_GPIO14 14 + +#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0 +#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1 +#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2 +#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3 +#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4 +#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5 +#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6 +#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7 +#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8 +#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9 +#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10 +#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11 +#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12 +#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 +#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 + +/* PCI controller GPIO to IRQ pin mappings + + INTA INTB +SLOT 0 10 11 +SLOT 1 11 10 + +*/ + +#define GTWX5715_PCI_SLOT0_DEVID 0 +#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10 +#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11 +#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ +#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ + +#define GTWX5715_PCI_SLOT1_DEVID 1 +#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11 +#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10 +#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ +#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ + +#define GTWX5715_PCI_SLOT_COUNT 2 +#define GTWX5715_PCI_INT_PIN_COUNT 2 + +/* + * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch + * and operate as an SPI type interface. The details of the interface + * are available on Kendin/Micrel's web site. + */ + +#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5 +#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6 +#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7 +#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12 + +/* + * The "reset" button is wired to GPIO 3. + * The GPIO is brought "low" when the button is pushed. + */ + +#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3 +#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ + +/* + * Board Label Front Label + * LED1 Power + * LED2 Wireless-G + * LED3 not populated but could be + * LED4 Internet + * LED5 - LED8 Controlled by KS8995M Switch + * LED9 DMZ + */ + +#define GTWX5715_LED1_GPIO GTWX5715_GPIO2 +#define GTWX5715_LED2_GPIO GTWX5715_GPIO9 +#define GTWX5715_LED3_GPIO GTWX5715_GPIO8 +#define GTWX5715_LED4_GPIO GTWX5715_GPIO1 +#define GTWX5715_LED9_GPIO GTWX5715_GPIO4 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/hardware.h b/trunk/arch/arm/mach-ixp4xx/include/mach/hardware.h index f9d1c43e4a54..f58a43a23966 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -18,13 +18,7 @@ #define __ASM_ARCH_HARDWARE_H__ #define PCIBIOS_MIN_IO 0x00001000 -#ifdef CONFIG_IXP4XX_INDIRECT_PCI -#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */ -#define PCIBIOS_MAX_MEM 0x4FFFFFFF -#else -#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */ -#define PCIBIOS_MAX_MEM 0x4BFFFFFF -#endif +#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) /* * We override the standard dma-mask routines for bouncing. @@ -43,4 +37,14 @@ /* Platform helper functions and definitions */ #include "platform.h" +/* Platform specific details */ +#include "ixdp425.h" +#include "avila.h" +#include "coyote.h" +#include "prpmc1100.h" +#include "nslu2.h" +#include "nas100d.h" +#include "dsmg600.h" +#include "fsg.h" + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/io.h b/trunk/arch/arm/mach-ixp4xx/include/mach/io.h index 6ea7e2fb2701..8a947d42a6f1 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/io.h @@ -26,20 +26,22 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); /* * IXP4xx provides two methods of accessing PCI memory space: * - * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). + * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). * To access PCI via this space, we simply ioremap() the BAR * into the kernel and we can use the standard read[bwl]/write[bwl] * macros. This is the preffered method due to speed but it - * limits the system to just 64MB of PCI memory. This can be - * problematic if using video cards and other memory-heavy targets. + * limits the system to just 64MB of PCI memory. This can be + * problamatic if using video cards and other memory-heavy + * targets. + * + * 2) If > 64MB of memory space is required, the IXP4xx can be configured + * to use indirect registers to access PCI (as we do below for I/O + * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) + * of memory on the bus. The disadvantage of this is that every + * PCI access requires three local register accesses plus a spinlock, + * but in some cases the performance hit is acceptable. In addition, + * you cannot mmap() PCI devices in this case. * - * 2) If > 64MB of memory space is required, the IXP4xx can use indirect - * registers to access the whole 4 GB of PCI memory space (as we do below - * for I/O transactions). This allows currently for up to 1 GB (0x10000000 - * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that - * every PCI access requires three local register accesses plus a spinlock, - * but in some cases the performance hit is acceptable. In addition, you - * cannot mmap() PCI devices in this case. */ #ifndef CONFIG_IXP4XX_INDIRECT_PCI @@ -53,52 +55,48 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ - -static inline int is_pci_memory(u32 addr) -{ - return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF); -} - -static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, - unsigned int mtype) +static inline void __iomem * +__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) { - if (!is_pci_memory(addr)) + if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) return __arm_ioremap(addr, size, mtype); return (void __iomem *)addr; } -static inline void __indirect_iounmap(void __iomem *addr) +static inline void +__ixp4xx_iounmap(void __iomem *addr) { - if (!is_pci_memory((__force u32)addr)) + if ((__force u32)addr >= VMALLOC_START) __iounmap(addr); } -#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) -#define __arch_iounmap(a) __indirect_iounmap(a) +#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) +#define __arch_iounmap(a) __ixp4xx_iounmap(a) -#define writeb(v, p) __indirect_writeb(v, p) -#define writew(v, p) __indirect_writew(v, p) -#define writel(v, p) __indirect_writel(v, p) +#define writeb(v, p) __ixp4xx_writeb(v, p) +#define writew(v, p) __ixp4xx_writew(v, p) +#define writel(v, p) __ixp4xx_writel(v, p) -#define writesb(p, v, l) __indirect_writesb(p, v, l) -#define writesw(p, v, l) __indirect_writesw(p, v, l) -#define writesl(p, v, l) __indirect_writesl(p, v, l) +#define writesb(p, v, l) __ixp4xx_writesb(p, v, l) +#define writesw(p, v, l) __ixp4xx_writesw(p, v, l) +#define writesl(p, v, l) __ixp4xx_writesl(p, v, l) + +#define readb(p) __ixp4xx_readb(p) +#define readw(p) __ixp4xx_readw(p) +#define readl(p) __ixp4xx_readl(p) + +#define readsb(p, v, l) __ixp4xx_readsb(p, v, l) +#define readsw(p, v, l) __ixp4xx_readsw(p, v, l) +#define readsl(p, v, l) __ixp4xx_readsl(p, v, l) -#define readb(p) __indirect_readb(p) -#define readw(p) __indirect_readw(p) -#define readl(p) __indirect_readl(p) - -#define readsb(p, v, l) __indirect_readsb(p, v, l) -#define readsw(p, v, l) __indirect_readsw(p, v, l) -#define readsl(p, v, l) __indirect_readsl(p, v, l) - -static inline void __indirect_writeb(u8 value, volatile void __iomem *p) +static inline void +__ixp4xx_writeb(u8 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; - if (!is_pci_memory(addr)) { + if (addr >= VMALLOC_START) { __raw_writeb(value, addr); return; } @@ -109,19 +107,20 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p) ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } -static inline void __indirect_writesb(volatile void __iomem *bus_addr, - const u8 *vaddr, int count) +static inline void +__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) { while (count--) writeb(*vaddr++, bus_addr); } -static inline void __indirect_writew(u16 value, volatile void __iomem *p) +static inline void +__ixp4xx_writew(u16 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; - if (!is_pci_memory(addr)) { + if (addr >= VMALLOC_START) { __raw_writew(value, addr); return; } @@ -132,18 +131,18 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p) ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } -static inline void __indirect_writesw(volatile void __iomem *bus_addr, - const u16 *vaddr, int count) +static inline void +__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) { while (count--) writew(*vaddr++, bus_addr); } -static inline void __indirect_writel(u32 value, volatile void __iomem *p) +static inline void +__ixp4xx_writel(u32 value, volatile void __iomem *p) { u32 addr = (__force u32)p; - - if (!is_pci_memory(addr)) { + if (addr >= VMALLOC_START) { __raw_writel(value, p); return; } @@ -151,19 +150,20 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p) ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); } -static inline void __indirect_writesl(volatile void __iomem *bus_addr, - const u32 *vaddr, int count) +static inline void +__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) { while (count--) writel(*vaddr++, bus_addr); } -static inline unsigned char __indirect_readb(const volatile void __iomem *p) +static inline unsigned char +__ixp4xx_readb(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; - if (!is_pci_memory(addr)) + if (addr >= VMALLOC_START) return __raw_readb(addr); n = addr % 4; @@ -174,19 +174,20 @@ static inline unsigned char __indirect_readb(const volatile void __iomem *p) return data >> (8*n); } -static inline void __indirect_readsb(const volatile void __iomem *bus_addr, - u8 *vaddr, u32 count) +static inline void +__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = readb(bus_addr); } -static inline unsigned short __indirect_readw(const volatile void __iomem *p) +static inline unsigned short +__ixp4xx_readw(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; - if (!is_pci_memory(addr)) + if (addr >= VMALLOC_START) return __raw_readw(addr); n = addr % 4; @@ -197,19 +198,20 @@ static inline unsigned short __indirect_readw(const volatile void __iomem *p) return data>>(8*n); } -static inline void __indirect_readsw(const volatile void __iomem *bus_addr, - u16 *vaddr, u32 count) +static inline void +__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = readw(bus_addr); } -static inline unsigned long __indirect_readl(const volatile void __iomem *p) +static inline unsigned long +__ixp4xx_readl(const volatile void __iomem *p) { u32 addr = (__force u32)p; u32 data; - if (!is_pci_memory(addr)) + if (addr >= VMALLOC_START) return __raw_readl(p); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) @@ -218,8 +220,8 @@ static inline unsigned long __indirect_readl(const volatile void __iomem *p) return data; } -static inline void __indirect_readsl(const volatile void __iomem *bus_addr, - u32 *vaddr, u32 count) +static inline void +__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = readl(bus_addr); @@ -233,7 +235,7 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr, #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) -#endif /* CONFIG_IXP4XX_INDIRECT_PCI */ +#endif #ifndef CONFIG_PCI @@ -248,8 +250,25 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr, * transaction. This means that we need to override the default * I/O functions. */ +#define outb(p, v) __ixp4xx_outb(p, v) +#define outw(p, v) __ixp4xx_outw(p, v) +#define outl(p, v) __ixp4xx_outl(p, v) + +#define outsb(p, v, l) __ixp4xx_outsb(p, v, l) +#define outsw(p, v, l) __ixp4xx_outsw(p, v, l) +#define outsl(p, v, l) __ixp4xx_outsl(p, v, l) -static inline void outb(u8 value, u32 addr) +#define inb(p) __ixp4xx_inb(p) +#define inw(p) __ixp4xx_inw(p) +#define inl(p) __ixp4xx_inl(p) + +#define insb(p, v, l) __ixp4xx_insb(p, v, l) +#define insw(p, v, l) __ixp4xx_insw(p, v, l) +#define insl(p, v, l) __ixp4xx_insl(p, v, l) + + +static inline void +__ixp4xx_outb(u8 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -258,13 +277,15 @@ static inline void outb(u8 value, u32 addr) ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } -static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count) +static inline void +__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) { while (count--) outb(*vaddr++, io_addr); } -static inline void outw(u16 value, u32 addr) +static inline void +__ixp4xx_outw(u16 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -273,24 +294,28 @@ static inline void outw(u16 value, u32 addr) ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } -static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count) +static inline void +__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) { while (count--) outw(cpu_to_le16(*vaddr++), io_addr); } -static inline void outl(u32 value, u32 addr) +static inline void +__ixp4xx_outl(u32 value, u32 addr) { ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); } -static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count) +static inline void +__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) { while (count--) - outl(cpu_to_le32(*vaddr++), io_addr); + outl(*vaddr++, io_addr); } -static inline u8 inb(u32 addr) +static inline u8 +__ixp4xx_inb(u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -301,13 +326,15 @@ static inline u8 inb(u32 addr) return data >> (8*n); } -static inline void insb(u32 io_addr, u8 *vaddr, u32 count) +static inline void +__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = inb(io_addr); } -static inline u16 inw(u32 addr) +static inline u16 +__ixp4xx_inw(u32 addr) { u32 n, byte_enables, data; n = addr % 4; @@ -318,13 +345,15 @@ static inline u16 inw(u32 addr) return data>>(8*n); } -static inline void insw(u32 io_addr, u16 *vaddr, u32 count) +static inline void +__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = le16_to_cpu(inw(io_addr)); } -static inline u32 inl(u32 addr) +static inline u32 +__ixp4xx_inl(u32 addr) { u32 data; if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) @@ -333,10 +362,11 @@ static inline u32 inl(u32 addr) return data; } -static inline void insl(u32 io_addr, u32 *vaddr, u32 count) +static inline void +__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) { while (count--) - *vaddr++ = le32_to_cpu(inl(io_addr)); + *vaddr++ = inl(io_addr); } #define PIO_OFFSET 0x10000UL @@ -344,183 +374,194 @@ static inline void insl(u32 io_addr, u32 *vaddr, u32 count) #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) - -#define ioread8(p) ioread8(p) -static inline unsigned int ioread8(const void __iomem *addr) +static inline unsigned int +__ixp4xx_ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)inb(port & PIO_MASK); + return (unsigned int)__ixp4xx_inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); #else - return (unsigned int)__indirect_readb(addr); + return (unsigned int)__ixp4xx_readb(addr); #endif } -#define ioread8_rep(p, v, c) ioread8_rep(p, v, c) -static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) +static inline void +__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - insb(port & PIO_MASK, vaddr, count); + __ixp4xx_insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else - __indirect_readsb(addr, vaddr, count); + __ixp4xx_readsb(addr, vaddr, count); #endif } -#define ioread16(p) ioread16(p) -static inline unsigned int ioread16(const void __iomem *addr) +static inline unsigned int +__ixp4xx_ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)inw(port & PIO_MASK); + return (unsigned int)__ixp4xx_inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); #else - return (unsigned int)__indirect_readw(addr); + return (unsigned int)__ixp4xx_readw(addr); #endif } -#define ioread16_rep(p, v, c) ioread16_rep(p, v, c) -static inline void ioread16_rep(const void __iomem *addr, void *vaddr, - u32 count) +static inline void +__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - insw(port & PIO_MASK, vaddr, count); + __ixp4xx_insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else - __indirect_readsw(addr, vaddr, count); + __ixp4xx_readsw(addr, vaddr, count); #endif } -#define ioread32(p) ioread32(p) -static inline unsigned int ioread32(const void __iomem *addr) +static inline unsigned int +__ixp4xx_ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)inl(port & PIO_MASK); + return (unsigned int)__ixp4xx_inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu((__force __le32)__raw_readl(addr)); #else - return (unsigned int)__indirect_readl(addr); + return (unsigned int)__ixp4xx_readl(addr); #endif } } -#define ioread32_rep(p, v, c) ioread32_rep(p, v, c) -static inline void ioread32_rep(const void __iomem *addr, void *vaddr, - u32 count) +static inline void +__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - insl(port & PIO_MASK, vaddr, count); + __ixp4xx_insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else - __indirect_readsl(addr, vaddr, count); + __ixp4xx_readsl(addr, vaddr, count); #endif } -#define iowrite8(v, p) iowrite8(v, p) -static inline void iowrite8(u8 value, void __iomem *addr) +static inline void +__ixp4xx_iowrite8(u8 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outb(value, port & PIO_MASK); + __ixp4xx_outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); #else - __indirect_writeb(value, addr); + __ixp4xx_writeb(value, addr); #endif } -#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) -static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, - u32 count) +static inline void +__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outsb(port & PIO_MASK, vaddr, count); + __ixp4xx_outsb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else - __indirect_writesb(addr, vaddr, count); + __ixp4xx_writesb(addr, vaddr, count); #endif } -#define iowrite16(v, p) iowrite16(v, p) -static inline void iowrite16(u16 value, void __iomem *addr) +static inline void +__ixp4xx_iowrite16(u16 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outw(value, port & PIO_MASK); + __ixp4xx_outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else - __indirect_writew(value, addr); + __ixp4xx_writew(value, addr); #endif } -#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) -static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, - u32 count) +static inline void +__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outsw(port & PIO_MASK, vaddr, count); + __ixp4xx_outsw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else - __indirect_writesw(addr, vaddr, count); + __ixp4xx_writesw(addr, vaddr, count); #endif } -#define iowrite32(v, p) iowrite32(v, p) -static inline void iowrite32(u32 value, void __iomem *addr) +static inline void +__ixp4xx_iowrite32(u32 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outl(value, port & PIO_MASK); + __ixp4xx_outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel((u32 __force)cpu_to_le32(value), addr); #else - __indirect_writel(value, addr); + __ixp4xx_writel(value, addr); #endif } -#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) -static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, - u32 count) +static inline void +__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - outsl(port & PIO_MASK, vaddr, count); + __ixp4xx_outsl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else - __indirect_writesl(addr, vaddr, count); + __ixp4xx_writesl(addr, vaddr, count); #endif } +#define ioread8(p) __ixp4xx_ioread8(p) +#define ioread16(p) __ixp4xx_ioread16(p) +#define ioread32(p) __ixp4xx_ioread32(p) + +#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) +#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) +#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) + +#define iowrite8(v,p) __ixp4xx_iowrite8(v,p) +#define iowrite16(v,p) __ixp4xx_iowrite16(v,p) +#define iowrite32(v,p) __ixp4xx_iowrite32(v,p) + +#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) +#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) +#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) + #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) #define ioport_unmap(addr) -#endif /* CONFIG_PCI */ +#endif // !CONFIG_PCI + +#endif // __ASM_ARM_ARCH_IO_H -#endif /* __ASM_ARM_ARCH_IO_H */ diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/irqs.h b/trunk/arch/arm/mach-ixp4xx/include/mach/irqs.h index 7e6d4cce7c27..f4d74de1566a 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/irqs.h @@ -15,6 +15,7 @@ #ifndef _ARCH_IXP4XX_IRQS_H_ #define _ARCH_IXP4XX_IRQS_H_ + #define IRQ_IXP4XX_NPEA 0 #define IRQ_IXP4XX_NPEB 1 #define IRQ_IXP4XX_NPEC 2 @@ -58,9 +59,6 @@ #define IRQ_IXP4XX_MCU_ECC 61 #define IRQ_IXP4XX_EXP_PE 62 -#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) -#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) - /* * Only first 32 sources are valid if running on IXP42x systems */ @@ -72,4 +70,69 @@ #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) +/* + * IXDP425 board IRQs + */ +#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 + +/* + * Gateworks Avila board IRQs + */ +#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 + + +/* + * PrPMC1100 Board IRQs + */ +#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 + +/* + * ADI Coyote Board IRQs + */ +#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 +#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 +#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 + +/* + * NSLU2 board IRQs + */ +#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 + +/* + * NAS100D board IRQs + */ +#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 +#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 + +/* + * D-Link DSM-G600 RevA board IRQs + */ +#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 +#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 +#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 +#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 +#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 +#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 + +/* + * Freecom FSG-3 Board IRQs + */ +#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 +#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 +#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 + #endif diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/trunk/arch/arm/mach-ixp4xx/include/mach/ixdp425.h new file mode 100644 index 000000000000..2cafe65ebfee --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/ixdp425.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/ixdp425.h + * + * IXDP425 platform specific definitions + * + * Author: Deepak Saxena + * + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define IXDP425_SDA_PIN 7 +#define IXDP425_SCL_PIN 6 + +/* + * IXDP425 PCI IRQs + */ +#define IXDP425_PCI_MAX_DEV 4 +#define IXDP425_PCI_IRQ_LINES 4 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define IXDP425_PCI_INTA_PIN 11 +#define IXDP425_PCI_INTB_PIN 10 +#define IXDP425_PCI_INTC_PIN 9 +#define IXDP425_PCI_INTD_PIN 8 + +/* NAND Flash pins */ +#define IXDP425_NAND_NCE_PIN 12 + +#define IXDP425_NAND_CMD_BYTE 0x01 +#define IXDP425_NAND_ADDR_BYTE 0x02 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/trunk/arch/arm/mach-ixp4xx/include/mach/nas100d.h new file mode 100644 index 000000000000..3771d62a9748 --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/nas100d.h @@ -0,0 +1,52 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/nas100d.h + * + * NAS100D platform specific definitions + * + * Copyright (c) 2005 Tower Technologies + * + * Author: Alessandro Zummo + * + * based on ixdp425.h: + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define NAS100D_SDA_PIN 5 +#define NAS100D_SCL_PIN 6 + +/* + * NAS100D PCI IRQs + */ +#define NAS100D_PCI_MAX_DEV 3 +#define NAS100D_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define NAS100D_PCI_INTA_PIN 11 +#define NAS100D_PCI_INTB_PIN 10 +#define NAS100D_PCI_INTC_PIN 9 +#define NAS100D_PCI_INTD_PIN 8 +#define NAS100D_PCI_INTE_PIN 7 + +/* Buttons */ + +#define NAS100D_PB_GPIO 14 /* power button */ +#define NAS100D_RB_GPIO 4 /* reset button */ + +/* Power control */ + +#define NAS100D_PO_GPIO 12 /* power off */ + +/* LEDs */ + +#define NAS100D_LED_WLAN_GPIO 0 +#define NAS100D_LED_DISK_GPIO 3 +#define NAS100D_LED_PWR_GPIO 15 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/npe.h b/trunk/arch/arm/mach-ixp4xx/include/mach/npe.h index e320db2457ae..37d0511689dc 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/npe.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/npe.h @@ -33,7 +33,7 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what); int npe_recv_message(struct npe *npe, void *msg, const char *what); int npe_send_recv_message(struct npe *npe, void *msg, const char *what); int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); -struct npe *npe_request(unsigned id); +struct npe *npe_request(int id); void npe_release(struct npe *npe); #endif /* __IXP4XX_NPE_H */ diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/trunk/arch/arm/mach-ixp4xx/include/mach/nslu2.h new file mode 100644 index 000000000000..85d00adbfb92 --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/nslu2.h @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/nslu2.h + * + * NSLU2 platform specific definitions + * + * Author: Mark Rakes + * Maintainers: http://www.nslu2-linux.org + * + * based on ixdp425.h: + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define NSLU2_SDA_PIN 7 +#define NSLU2_SCL_PIN 6 + +/* + * NSLU2 PCI IRQs + */ +#define NSLU2_PCI_MAX_DEV 3 +#define NSLU2_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define NSLU2_PCI_INTA_PIN 11 +#define NSLU2_PCI_INTB_PIN 10 +#define NSLU2_PCI_INTC_PIN 9 +#define NSLU2_PCI_INTD_PIN 8 + +/* NSLU2 Timer */ +#define NSLU2_FREQ 66000000 + +/* Buttons */ + +#define NSLU2_PB_GPIO 5 /* power button */ +#define NSLU2_PO_GPIO 8 /* power off */ +#define NSLU2_RB_GPIO 12 /* reset button */ + +/* Buzzer */ + +#define NSLU2_GPIO_BUZZ 4 + +/* LEDs */ + +#define NSLU2_LED_RED_GPIO 0 +#define NSLU2_LED_GRN_GPIO 1 +#define NSLU2_LED_DISK1_GPIO 3 +#define NSLU2_LED_DISK2_GPIO 2 diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/trunk/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h new file mode 100644 index 000000000000..17274a2e3dec --- /dev/null +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h + * + * Motorolla PrPMC1100 platform specific definitions + * + * Author: Deepak Saxena + * + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS +#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE + +#define PRPMC1100_PCI_MIN_DEVID 10 +#define PRPMC1100_PCI_MAX_DEVID 16 +#define PRPMC1100_PCI_IRQ_LINES 4 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define PRPMC1100_PCI_INTA_PIN 11 +#define PRPMC1100_PCI_INTB_PIN 10 +#define PRPMC1100_PCI_INTC_PIN 9 +#define PRPMC1100_PCI_INTD_PIN 8 + + diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/timex.h b/trunk/arch/arm/mach-ixp4xx/include/mach/timex.h index 2c3f93c3eb79..89ce3ee84698 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/timex.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/timex.h @@ -10,6 +10,6 @@ * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the * timer register ignores the bottom 2 bits of the LATCH value. */ -#define FREQ 66666000 +#define FREQ 66666666 #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) diff --git a/trunk/arch/arm/mach-ixp4xx/ixdp425-pci.c b/trunk/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a6edac..64c29aacaac9 100644 --- a/trunk/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-ixp4xx/ixdp425-pci.c + * arch/arm/mach-ixp4xx/ixdp425-pci.c * * IXDP425 board-level PCI initialization * @@ -19,43 +19,39 @@ #include #include #include + #include #include #include #include -#define MAX_DEV 4 -#define IRQ_LINES 4 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 11 -#define INTB 10 -#define INTC 9 -#define INTD 8 - - void __init ixdp425_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[IRQ_LINES] = { - IXP4XX_GPIO_IRQ(INTA), - IXP4XX_GPIO_IRQ(INTB), - IXP4XX_GPIO_IRQ(INTC), - IXP4XX_GPIO_IRQ(INTD) + static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = { + IRQ_IXDP425_PCI_INTA, + IRQ_IXDP425_PCI_INTB, + IRQ_IXDP425_PCI_INTC, + IRQ_IXDP425_PCI_INTD }; - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[(slot + pin - 2) % 4]; + int irq = -1; + + if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && + pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) { + irq = pci_irq_table[(slot + pin - 2) % 4]; + } - return -1; + return irq; } struct hw_pci ixdp425_pci __initdata = { @@ -76,3 +72,4 @@ int __init ixdp425_pci_init(void) } subsys_initcall(ixdp425_pci_init); + diff --git a/trunk/arch/arm/mach-ixp4xx/ixdp425-setup.c b/trunk/arch/arm/mach-ixp4xx/ixdp425-setup.c index bbb768988845..f4a0c1bc1331 100644 --- a/trunk/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-ixp4xx/ixdp425-setup.c * - * IXDP425/IXCDP1100 board-setup + * IXDP425/IXCDP1100 board-setup * * Copyright (C) 2003-2005 MontaVista Software, Inc. * @@ -21,6 +21,7 @@ #include #include #include + #include #include #include @@ -30,15 +31,6 @@ #include #include -#define IXDP425_SDA_PIN 7 -#define IXDP425_SCL_PIN 6 - -/* NAND Flash pins */ -#define IXDP425_NAND_NCE_PIN 12 - -#define IXDP425_NAND_CMD_BYTE 0x01 -#define IXDP425_NAND_ADDR_BYTE 0x02 - static struct flash_platform_data ixdp425_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c index e8bb25778166..47ac69c7ec78 100644 --- a/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/trunk/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -665,7 +665,7 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) } -struct npe *npe_request(unsigned id) +struct npe *npe_request(int id) { if (id < NPE_COUNT) if (npe_tab[id].valid) diff --git a/trunk/arch/arm/mach-ixp4xx/nas100d-pci.c b/trunk/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34cf61e..1088426fdcee 100644 --- a/trunk/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -18,42 +18,37 @@ #include #include #include + #include #include -#define MAX_DEV 3 -#define IRQ_LINES 3 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 11 -#define INTB 10 -#define INTC 9 -#define INTD 8 -#define INTE 7 - void __init nas100d_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[MAX_DEV][IRQ_LINES] = { - { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, - { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, - { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), - IXP4XX_GPIO_IRQ(INTE) }, + static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = + { + { IRQ_NAS100D_PCI_INTA, -1, -1 }, + { IRQ_NAS100D_PCI_INTB, -1, -1 }, + { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, }; - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[slot - 1][pin - 1]; + int irq = -1; + + if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && + pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) + irq = pci_irq_table[slot-1][pin-1]; - return -1; + return irq; } struct hw_pci __initdata nas100d_pci = { diff --git a/trunk/arch/arm/mach-ixp4xx/nas100d-setup.c b/trunk/arch/arm/mach-ixp4xx/nas100d-setup.c index e3ee880aa1e6..921c947b5b6b 100644 --- a/trunk/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -29,26 +29,12 @@ #include #include #include + #include #include #include #include -#define NAS100D_SDA_PIN 5 -#define NAS100D_SCL_PIN 6 - -/* Buttons */ -#define NAS100D_PB_GPIO 14 /* power button */ -#define NAS100D_RB_GPIO 4 /* reset button */ - -/* Power control */ -#define NAS100D_PO_GPIO 12 /* power off */ - -/* LEDs */ -#define NAS100D_LED_WLAN_GPIO 0 -#define NAS100D_LED_DISK_GPIO 3 -#define NAS100D_LED_PWR_GPIO 15 - static struct flash_platform_data nas100d_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-ixp4xx/nslu2-pci.c b/trunk/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90470bc..4429b8448b61 100644 --- a/trunk/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/trunk/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -18,38 +18,35 @@ #include #include #include + #include #include -#define MAX_DEV 3 -#define IRQ_LINES 3 - -/* PCI controller GPIO to IRQ pin mappings */ -#define INTA 11 -#define INTB 10 -#define INTC 9 -#define INTD 8 - void __init nslu2_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); } static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - static int pci_irq_table[IRQ_LINES] = { - IXP4XX_GPIO_IRQ(INTA), - IXP4XX_GPIO_IRQ(INTB), - IXP4XX_GPIO_IRQ(INTC), + static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = { + IRQ_NSLU2_PCI_INTA, + IRQ_NSLU2_PCI_INTB, + IRQ_NSLU2_PCI_INTC, }; - if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) - return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + int irq = -1; + + if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV && + pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) { + irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES]; + } - return -1; + return irq; } struct hw_pci __initdata nslu2_pci = { diff --git a/trunk/arch/arm/mach-ixp4xx/nslu2-setup.c b/trunk/arch/arm/mach-ixp4xx/nslu2-setup.c index c14e0034be4b..ff6a08d02cc4 100644 --- a/trunk/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -26,32 +26,13 @@ #include #include #include + #include #include #include #include #include -#define NSLU2_SDA_PIN 7 -#define NSLU2_SCL_PIN 6 - -/* NSLU2 Timer */ -#define NSLU2_FREQ 66000000 - -/* Buttons */ -#define NSLU2_PB_GPIO 5 /* power button */ -#define NSLU2_PO_GPIO 8 /* power off */ -#define NSLU2_RB_GPIO 12 /* reset button */ - -/* Buzzer */ -#define NSLU2_GPIO_BUZZ 4 - -/* LEDs */ -#define NSLU2_LED_RED_GPIO 0 -#define NSLU2_LED_GRN_GPIO 1 -#define NSLU2_LED_DISK1_GPIO 3 -#define NSLU2_LED_DISK2_GPIO 2 - static struct flash_platform_data nslu2_flash_data = { .map_name = "cfi_probe", .width = 2, diff --git a/trunk/arch/arm/mach-omap1/Makefile b/trunk/arch/arm/mach-omap1/Makefile index 9ce17f13d3f1..87e539aa8ad9 100644 --- a/trunk/arch/arm/mach-omap1/Makefile +++ b/trunk/arch/arm/mach-omap1/Makefile @@ -3,8 +3,7 @@ # # Common support -obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o -obj-y += clock.o clock_data.o opp_data.o +obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -18,9 +17,6 @@ obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o -i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o -obj-y += $(i2c-omap-m) $(i2c-omap-y) - led-y := leds.o # Specific board support @@ -52,7 +48,3 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o obj-$(CONFIG_LEDS) += $(led-y) - -ifneq ($(CONFIG_FB_OMAP),) -obj-y += lcd_dma.o -endif diff --git a/trunk/arch/arm/mach-omap1/board-fsample.c b/trunk/arch/arm/mach-omap1/board-fsample.c index 7e70c3c08da6..f4b72c1654f5 100644 --- a/trunk/arch/arm/mach-omap1/board-fsample.c +++ b/trunk/arch/arm/mach-omap1/board-fsample.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -31,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -100,12 +100,6 @@ static int fsample_keymap[] = { 0 }; -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource smc91x_resources[] = { [0] = { .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ @@ -173,40 +167,8 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - -#define FSAMPLE_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN); -} - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, - }, - .ctrl = { - .cmd_ctrl = nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, +static struct omap_nand_platform_data nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, }; static struct resource nand_resource = { @@ -216,7 +178,7 @@ static struct resource nand_resource = { }; static struct platform_device nand_device = { - .name = "gen_nand", + .name = "omapnand", .id = 0, .dev = { .platform_data = &nand_data, @@ -228,9 +190,6 @@ static struct platform_device nand_device = { static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; @@ -274,6 +233,13 @@ static struct platform_device *devices[] __initdata = { &lcd_device, }; +#define P2_NAND_RB_GPIO_PIN 62 + +static int nand_dev_ready(struct omap_nand_platform_data *data) +{ + return gpio_get_value(P2_NAND_RB_GPIO_PIN); +} + static struct omap_lcd_config fsample_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -284,9 +250,9 @@ static struct omap_board_config_kernel fsample_config[] = { static void __init omap_fsample_init(void) { - if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) + if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) BUG(); - gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); + nand_data.dev_ready = nand_dev_ready; omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); diff --git a/trunk/arch/arm/mach-omap1/board-h2.c b/trunk/arch/arm/mach-omap1/board-h2.c index fa7cecea19f9..89ba8ec4bbf4 100644 --- a/trunk/arch/arm/mach-omap1/board-h2.c +++ b/trunk/arch/arm/mach-omap1/board-h2.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -41,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -179,43 +179,11 @@ static struct mtd_partition h2_nand_partitions[] = { }, }; -static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - -#define H2_NAND_RB_GPIO_PIN 62 - -static int h2_nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(H2_NAND_RB_GPIO_PIN); -} - -static const char *h2_part_probes[] = { "cmdlinepart", NULL }; - -struct platform_nand_data h2_nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(h2_nand_partitions), - .partitions = h2_nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = h2_part_probes, - }, - .ctrl = { - .cmd_ctrl = h2_nand_cmd_ctl, - .dev_ready = h2_nand_dev_ready, - - }, +/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ +static struct omap_nand_platform_data h2_nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, + .parts = h2_nand_partitions, + .nr_parts = ARRAY_SIZE(h2_nand_partitions), }; static struct resource h2_nand_resource = { @@ -223,21 +191,15 @@ static struct resource h2_nand_resource = { }; static struct platform_device h2_nand_device = { - .name = "gen_nand", + .name = "omapnand", .id = 0, .dev = { - .platform_data = &h2_nand_platdata, + .platform_data = &h2_nand_data, }, .num_resources = 1, .resource = &h2_nand_resource, }; -static struct smc91x_platdata h2_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource h2_smc91x_resources[] = { [0] = { .start = OMAP1610_ETHR_START, /* Physical */ @@ -254,9 +216,6 @@ static struct resource h2_smc91x_resources[] = { static struct platform_device h2_smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &h2_smc91x_info, - }, .num_resources = ARRAY_SIZE(h2_smc91x_resources), .resource = h2_smc91x_resources, }; @@ -409,6 +368,8 @@ static struct omap_board_config_kernel h2_config[] __initdata = { { OMAP_TAG_LCD, &h2_lcd_config }, }; +#define H2_NAND_RB_GPIO_PIN 62 + static void __init h2_init(void) { /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped diff --git a/trunk/arch/arm/mach-omap1/board-h3.c b/trunk/arch/arm/mach-omap1/board-h3.c index 6a7f9c391cf1..f5cc0a730524 100644 --- a/trunk/arch/arm/mach-omap1/board-h3.c +++ b/trunk/arch/arm/mach-omap1/board-h3.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -43,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -181,43 +181,11 @@ static struct mtd_partition nand_partitions[] = { }, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - -#define H3_NAND_RB_GPIO_PIN 10 - -static int nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(H3_NAND_RB_GPIO_PIN); -} - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -struct platform_nand_data nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(nand_partitions), - .partitions = nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, - }, - .ctrl = { - .cmd_ctrl = nand_cmd_ctl, - .dev_ready = nand_dev_ready, - - }, +/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ +static struct omap_nand_platform_data nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, + .parts = nand_partitions, + .nr_parts = ARRAY_SIZE(nand_partitions), }; static struct resource nand_resource = { @@ -225,21 +193,15 @@ static struct resource nand_resource = { }; static struct platform_device nand_device = { - .name = "gen_nand", + .name = "omapnand", .id = 0, .dev = { - .platform_data = &nand_platdata, + .platform_data = &nand_data, }, .num_resources = 1, .resource = &nand_resource, }; -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource smc91x_resources[] = { [0] = { .start = OMAP1710_ETHR_START, /* Physical */ @@ -256,9 +218,6 @@ static struct resource smc91x_resources[] = { static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; @@ -373,6 +332,13 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = { }, }; +#define H3_NAND_RB_GPIO_PIN 10 + +static int nand_dev_ready(struct omap_nand_platform_data *data) +{ + return gpio_get_value(H3_NAND_RB_GPIO_PIN); +} + static void __init h3_init(void) { /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped @@ -390,7 +356,7 @@ static void __init h3_init(void) nand_resource.end += SZ_4K - 1; if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0) BUG(); - gpio_direction_input(H3_NAND_RB_GPIO_PIN); + nand_data.dev_ready = nand_dev_ready; /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ diff --git a/trunk/arch/arm/mach-omap1/board-htcherald.c b/trunk/arch/arm/mach-omap1/board-htcherald.c index e36639f66150..5f28a5ceacac 100644 --- a/trunk/arch/arm/mach-omap1/board-htcherald.c +++ b/trunk/arch/arm/mach-omap1/board-htcherald.c @@ -39,7 +39,6 @@ #include #include #include -#include #include @@ -141,15 +140,6 @@ static struct platform_device kp_device = { .resource = kp_resources, }; -/* USB Device */ -static struct omap_usb_config htcherald_usb_config __initdata = { - .otg = 0, - .register_host = 0, - .register_dev = 1, - .hmc_mode = 4, - .pins[0] = 2, -}; - /* LCD Device resources */ static struct platform_device lcd_device = { .name = "lcd_htcherald", @@ -224,57 +214,6 @@ static void __init htcherald_disable_watchdog(void) } } -#define HTCHERALD_GPIO_USB_EN1 33 -#define HTCHERALD_GPIO_USB_EN2 73 -#define HTCHERALD_GPIO_USB_DM 35 -#define HTCHERALD_GPIO_USB_DP 36 - -static void __init htcherald_usb_enable(void) -{ - unsigned int tries = 20; - unsigned int value = 0; - - /* Request the GPIOs we need to control here */ - if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0) - goto err1; - - if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0) - goto err2; - - if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0) - goto err3; - - if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0) - goto err4; - - /* force USB_EN GPIO to 0 */ - do { - /* output low */ - gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0); - } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 && - --tries); - - if (value == 1) - printk(KERN_WARNING "Unable to reset USB, trying to continue\n"); - - gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */ - gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */ - gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */ - - goto done; - -err4: - gpio_free(HTCHERALD_GPIO_USB_DM); -err3: - gpio_free(HTCHERALD_GPIO_USB_EN2); -err2: - gpio_free(HTCHERALD_GPIO_USB_EN1); -err1: - printk(KERN_ERR "Unabled to request GPIO for USB\n"); -done: - printk(KERN_INFO "USB setup complete.\n"); -} - static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); @@ -286,9 +225,6 @@ static void __init htcherald_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); htcherald_disable_watchdog(); - - htcherald_usb_enable(); - omap_usb_init(&htcherald_usb_config); } static void __init htcherald_init_irq(void) diff --git a/trunk/arch/arm/mach-omap1/board-innovator.c b/trunk/arch/arm/mach-omap1/board-innovator.c index 2133b006f6a3..cf0fdb9c182f 100644 --- a/trunk/arch/arm/mach-omap1/board-innovator.c +++ b/trunk/arch/arm/mach-omap1/board-innovator.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -143,11 +142,6 @@ static struct platform_device innovator_kp_device = { .resource = innovator_kp_resources, }; -static struct smc91x_platdata innovator_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; #ifdef CONFIG_ARCH_OMAP15XX @@ -181,9 +175,6 @@ static struct resource innovator1510_smc91x_resources[] = { static struct platform_device innovator1510_smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), .resource = innovator1510_smc91x_resources, }; @@ -250,9 +241,6 @@ static struct resource innovator1610_smc91x_resources[] = { static struct platform_device innovator1610_smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), .resource = innovator1610_smc91x_resources, }; diff --git a/trunk/arch/arm/mach-omap1/board-osk.c b/trunk/arch/arm/mach-omap1/board-osk.c index ccea4f448e9a..50c92c13e48a 100644 --- a/trunk/arch/arm/mach-omap1/board-osk.c +++ b/trunk/arch/arm/mach-omap1/board-osk.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include @@ -116,12 +115,6 @@ static struct platform_device osk5912_flash_device = { .resource = &osk_flash_resource, }; -static struct smc91x_platdata osk5912_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource osk5912_smc91x_resources[] = { [0] = { .start = OMAP_OSK_ETHR_START, /* Physical */ @@ -138,9 +131,6 @@ static struct resource osk5912_smc91x_resources[] = { static struct platform_device osk5912_smc91x_device = { .name = "smc91x", .id = -1, - .dev = { - .platform_data = &osk5912_smc91x_info, - }, .num_resources = ARRAY_SIZE(osk5912_smc91x_resources), .resource = osk5912_smc91x_resources, }; diff --git a/trunk/arch/arm/mach-omap1/board-perseus2.c b/trunk/arch/arm/mach-omap1/board-perseus2.c index 1387a4f15da9..ca7df1e93efc 100644 --- a/trunk/arch/arm/mach-omap1/board-perseus2.c +++ b/trunk/arch/arm/mach-omap1/board-perseus2.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -31,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -67,12 +67,6 @@ static int p2_keymap[] = { 0 }; -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource smc91x_resources[] = { [0] = { .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ @@ -140,40 +134,8 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - -#define P2_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(P2_NAND_RB_GPIO_PIN); -} - -static const char *part_probes[] = { "cmdlinepart", NULL }; - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - .part_probe_types = part_probes, - }, - .ctrl = { - .cmd_ctrl = nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, +static struct omap_nand_platform_data nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, }; static struct resource nand_resource = { @@ -183,7 +145,7 @@ static struct resource nand_resource = { }; static struct platform_device nand_device = { - .name = "gen_nand", + .name = "omapnand", .id = 0, .dev = { .platform_data = &nand_data, @@ -195,9 +157,6 @@ static struct platform_device nand_device = { static struct platform_device smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; @@ -242,6 +201,13 @@ static struct platform_device *devices[] __initdata = { &lcd_device, }; +#define P2_NAND_RB_GPIO_PIN 62 + +static int nand_dev_ready(struct omap_nand_platform_data *data) +{ + return gpio_get_value(P2_NAND_RB_GPIO_PIN); +} + static struct omap_lcd_config perseus2_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -254,7 +220,7 @@ static void __init omap_perseus2_init(void) { if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) BUG(); - gpio_direction_input(P2_NAND_RB_GPIO_PIN); + nand_data.dev_ready = nand_dev_ready; omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); diff --git a/trunk/arch/arm/mach-omap1/board-voiceblue.c b/trunk/arch/arm/mach-omap1/board-voiceblue.c index 169183537997..35c75c1bd0aa 100644 --- a/trunk/arch/arm/mach-omap1/board-voiceblue.c +++ b/trunk/arch/arm/mach-omap1/board-voiceblue.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -107,12 +106,6 @@ static struct platform_device voiceblue_flash_device = { .resource = &voiceblue_flash_resource, }; -static struct smc91x_platdata voiceblue_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource voiceblue_smc91x_resources[] = { [0] = { .start = OMAP_CS2_PHYS + 0x300, @@ -129,9 +122,6 @@ static struct resource voiceblue_smc91x_resources[] = { static struct platform_device voiceblue_smc91x_device = { .name = "smc91x", .id = 0, - .dev = { - .platform_data = &voiceblue_smc91x_info, - }, .num_resources = ARRAY_SIZE(voiceblue_smc91x_resources), .resource = voiceblue_smc91x_resources, }; diff --git a/trunk/arch/arm/mach-omap1/clock.c b/trunk/arch/arm/mach-omap1/clock.c index 2ba9ab953731..42cbe203da36 100644 --- a/trunk/arch/arm/mach-omap1/clock.c +++ b/trunk/arch/arm/mach-omap1/clock.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap1/clock.c * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation + * Copyright (C) 2004 - 2005 Nokia corporation * Written by Tuukka Tikkanen * * Modified to use omap shared clock framework by @@ -26,17 +26,12 @@ #include #include #include -#include -#include "clock.h" -#include "opp.h" - -__u32 arm_idlect1_mask; -struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; +static const struct clkops clkops_generic; +static const struct clkops clkops_uart; +static const struct clkops clkops_dspck; -/*------------------------------------------------------------------------- - * Omap1 specific clock functions - *-------------------------------------------------------------------------*/ +#include "clock.h" static int clk_omap1_dummy_enable(struct clk *clk) { @@ -47,24 +42,134 @@ static void clk_omap1_dummy_disable(struct clk *clk) { } -const struct clkops clkops_dummy = { - .enable = clk_omap1_dummy_enable, - .disable = clk_omap1_dummy_disable, +static const struct clkops clkops_dummy = { + .enable = clk_omap1_dummy_enable, + .disable = clk_omap1_dummy_disable, +}; + +static struct clk dummy_ck = { + .name = "dummy", + .ops = &clkops_dummy, + .flags = RATE_FIXED, +}; + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; }; -/* XXX can be replaced with a fixed_divisor_recalc */ -unsigned long omap1_watchdog_recalc(struct clk *clk) +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_310 (1 << 0) +#define CK_7XX (1 << 1) +#define CK_1510 (1 << 2) +#define CK_16XX (1 << 3) + +static struct omap_clk omap_clks[] = { + /* non-ULPD clocks */ + CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), + /* CK_GEN1 clocks */ + CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), + CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), + CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), + CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), + CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), + /* CK_GEN2 clocks */ + CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), + /* CK_GEN3 clocks */ + CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), + CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), + CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), + CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), + CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), + CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), + CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), + CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), + CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), + CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), + /* ULPD clocks */ + CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), + CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), + CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), + CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), + CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), + CLK(NULL, "mclk", &mclk_16xx, CK_16XX), + CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), + CLK(NULL, "bclk", &bclk_16xx, CK_16XX), + CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), + CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), + CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), + CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), + /* Virtual clocks */ + CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), + CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), + CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), + CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), +}; + +static int omap1_clk_enable_generic(struct clk * clk); +static int omap1_clk_enable(struct clk *clk); +static void omap1_clk_disable_generic(struct clk * clk); +static void omap1_clk_disable(struct clk *clk); + +__u32 arm_idlect1_mask; + +/*------------------------------------------------------------------------- + * Omap1 specific clock functions + *-------------------------------------------------------------------------*/ + +static unsigned long omap1_watchdog_recalc(struct clk *clk) { return clk->parent->rate / 14; } -unsigned long omap1_uart_recalc(struct clk *clk) +static unsigned long omap1_uart_recalc(struct clk *clk) { unsigned int val = __raw_readl(clk->enable_reg); return val & clk->enable_bit ? 48000000 : 12000000; } -unsigned long omap1_sossi_recalc(struct clk *clk) +static unsigned long omap1_sossi_recalc(struct clk *clk) { u32 div = omap_readl(MOD_CONF_CTRL_1); @@ -74,6 +179,64 @@ unsigned long omap1_sossi_recalc(struct clk *clk) return clk->parent->rate / div; } +static int omap1_clk_enable_dsp_domain(struct clk *clk) +{ + int retval; + + retval = omap1_clk_enable(&api_ck.clk); + if (!retval) { + retval = omap1_clk_enable_generic(clk); + omap1_clk_disable(&api_ck.clk); + } + + return retval; +} + +static void omap1_clk_disable_dsp_domain(struct clk *clk) +{ + if (omap1_clk_enable(&api_ck.clk) == 0) { + omap1_clk_disable_generic(clk); + omap1_clk_disable(&api_ck.clk); + } +} + +static const struct clkops clkops_dspck = { + .enable = &omap1_clk_enable_dsp_domain, + .disable = &omap1_clk_disable_dsp_domain, +}; + +static int omap1_clk_enable_uart_functional(struct clk *clk) +{ + int ret; + struct uart_clk *uclk; + + ret = omap1_clk_enable_generic(clk); + if (ret == 0) { + /* Set smart idle acknowledgement mode */ + uclk = (struct uart_clk *)clk; + omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, + uclk->sysc_addr); + } + + return ret; +} + +static void omap1_clk_disable_uart_functional(struct clk *clk) +{ + struct uart_clk *uclk; + + /* Set force idle acknowledgement mode */ + uclk = (struct uart_clk *)clk; + omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); + + omap1_clk_disable_generic(clk); +} + +static const struct clkops clkops_uart = { + .enable = &omap1_clk_enable_uart_functional, + .disable = &omap1_clk_disable_uart_functional, +}; + static void omap1_clk_allow_idle(struct clk *clk) { struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; @@ -181,7 +344,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) return dsor_exp; } -unsigned long omap1_ckctl_recalc(struct clk *clk) +static unsigned long omap1_ckctl_recalc(struct clk *clk) { /* Calculate divisor encoded as 2-bit exponent */ int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); @@ -189,7 +352,7 @@ unsigned long omap1_ckctl_recalc(struct clk *clk) return clk->parent->rate / dsor; } -unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) { int dsor; @@ -200,29 +363,28 @@ unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) * Note that DSP_CKCTL virt addr = phys addr, so * we must use __raw_readw() instead of omap_readw(). */ - omap1_clk_enable(api_ck_p); + omap1_clk_enable(&api_ck.clk); dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); - omap1_clk_disable(api_ck_p); + omap1_clk_disable(&api_ck.clk); return clk->parent->rate / dsor; } /* MPU virtual clock functions */ -int omap1_select_table_rate(struct clk *clk, unsigned long rate) +static int omap1_select_table_rate(struct clk * clk, unsigned long rate) { /* Find the highest supported frequency <= rate and switch to it */ struct mpu_rate * ptr; - unsigned long dpll1_rate, ref_rate; - dpll1_rate = clk_get_rate(ck_dpll1_p); - ref_rate = clk_get_rate(ck_ref_p); + if (clk != &virtual_ck_mpu) + return -EINVAL; - for (ptr = omap1_rate_table; ptr->rate; ptr++) { - if (ptr->xtal != ref_rate) + for (ptr = rate_table; ptr->rate; ptr++) { + if (ptr->xtal != ck_ref.rate) continue; /* DPLL1 cannot be reprogrammed without risking system crash */ - if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) + if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) continue; /* Can check only after xtal frequency check */ @@ -243,13 +405,11 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) else omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); - /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ - ck_dpll1_p->rate = ptr->pll_rate; - + ck_dpll1.rate = ptr->pll_rate; return 0; } -int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) +static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) { int dsor_exp; u16 regval; @@ -269,7 +429,7 @@ int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) return 0; } -long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) +static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) { int dsor_exp = calc_dsor_exp(clk, rate); if (dsor_exp < 0) @@ -279,7 +439,7 @@ long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) return clk->parent->rate / (1 << dsor_exp); } -int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) +static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) { int dsor_exp; u16 regval; @@ -299,19 +459,19 @@ int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) return 0; } -long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) +static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) { /* Find the highest supported frequency <= rate */ struct mpu_rate * ptr; - long highest_rate; - unsigned long ref_rate; + long highest_rate; - ref_rate = clk_get_rate(ck_ref_p); + if (clk != &virtual_ck_mpu) + return -EINVAL; highest_rate = -EINVAL; - for (ptr = omap1_rate_table; ptr->rate; ptr++) { - if (ptr->xtal != ref_rate) + for (ptr = rate_table; ptr->rate; ptr++) { + if (ptr->xtal != ck_ref.rate) continue; highest_rate = ptr->rate; @@ -346,8 +506,8 @@ static unsigned calc_ext_dsor(unsigned long rate) return dsor; } -/* XXX Only needed on 1510 */ -int omap1_set_uart_rate(struct clk *clk, unsigned long rate) +/* Only needed on 1510 */ +static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) { unsigned int val; @@ -365,7 +525,7 @@ int omap1_set_uart_rate(struct clk *clk, unsigned long rate) } /* External clock (MCLK & BCLK) functions */ -int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) +static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) { unsigned dsor; __u16 ratio_bits; @@ -383,7 +543,7 @@ int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) return 0; } -int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) { u32 l; int div; @@ -406,12 +566,12 @@ int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) return 0; } -long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) +static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) { return 96000000 / calc_ext_dsor(rate); } -void omap1_init_ext_clk(struct clk *clk) +static void omap1_init_ext_clk(struct clk * clk) { unsigned dsor; __u16 ratio_bits; @@ -429,7 +589,7 @@ void omap1_init_ext_clk(struct clk *clk) clk-> rate = 96000000 / dsor; } -int omap1_clk_enable(struct clk *clk) +static int omap1_clk_enable(struct clk *clk) { int ret = 0; @@ -457,7 +617,7 @@ int omap1_clk_enable(struct clk *clk) return ret; } -void omap1_clk_disable(struct clk *clk) +static void omap1_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { clk->ops->disable(clk); @@ -512,70 +672,12 @@ static void omap1_clk_disable_generic(struct clk *clk) } } -const struct clkops clkops_generic = { - .enable = omap1_clk_enable_generic, - .disable = omap1_clk_disable_generic, -}; - -static int omap1_clk_enable_dsp_domain(struct clk *clk) -{ - int retval; - - retval = omap1_clk_enable(api_ck_p); - if (!retval) { - retval = omap1_clk_enable_generic(clk); - omap1_clk_disable(api_ck_p); - } - - return retval; -} - -static void omap1_clk_disable_dsp_domain(struct clk *clk) -{ - if (omap1_clk_enable(api_ck_p) == 0) { - omap1_clk_disable_generic(clk); - omap1_clk_disable(api_ck_p); - } -} - -const struct clkops clkops_dspck = { - .enable = omap1_clk_enable_dsp_domain, - .disable = omap1_clk_disable_dsp_domain, -}; - -static int omap1_clk_enable_uart_functional(struct clk *clk) -{ - int ret; - struct uart_clk *uclk; - - ret = omap1_clk_enable_generic(clk); - if (ret == 0) { - /* Set smart idle acknowledgement mode */ - uclk = (struct uart_clk *)clk; - omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, - uclk->sysc_addr); - } - - return ret; -} - -static void omap1_clk_disable_uart_functional(struct clk *clk) -{ - struct uart_clk *uclk; - - /* Set force idle acknowledgement mode */ - uclk = (struct uart_clk *)clk; - omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); - - omap1_clk_disable_generic(clk); -} - -const struct clkops clkops_uart = { - .enable = omap1_clk_enable_uart_functional, - .disable = omap1_clk_disable_uart_functional, +static const struct clkops clkops_generic = { + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, }; -long omap1_clk_round_rate(struct clk *clk, unsigned long rate) +static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) { if (clk->flags & RATE_FIXED) return clk->rate; @@ -586,7 +688,7 @@ long omap1_clk_round_rate(struct clk *clk, unsigned long rate) return clk->rate; } -int omap1_clk_set_rate(struct clk *clk, unsigned long rate) +static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) { int ret = -EINVAL; @@ -601,7 +703,7 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) #ifdef CONFIG_OMAP_RESET_CLOCKS -void __init omap1_clk_disable_unused(struct clk *clk) +static void __init omap1_clk_disable_unused(struct clk *clk) { __u32 regval32; @@ -622,9 +724,184 @@ void __init omap1_clk_disable_unused(struct clk *clk) if ((regval32 & (1 << clk->enable_bit)) == 0) return; + /* FIXME: This clock seems to be necessary but no-one + * has asked for its activation. */ + if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */ + || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */ + || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */ + ) { + printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", + clk->name); + return; + } + printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); clk->ops->disable(clk); printk(" done\n"); } +#else +#define omap1_clk_disable_unused NULL #endif + +static struct clk_functions omap1_clk_functions = { + .clk_enable = omap1_clk_enable, + .clk_disable = omap1_clk_disable, + .clk_round_rate = omap1_clk_round_rate, + .clk_set_rate = omap1_clk_set_rate, + .clk_disable_unused = omap1_clk_disable_unused, +}; + +int __init omap1_clk_init(void) +{ + struct omap_clk *c; + const struct omap_clock_config *info; + int crystal_type = 0; /* Default 12 MHz */ + u32 reg, cpu_mask; + +#ifdef CONFIG_DEBUG_LL + /* Resets some clocks that may be left on from bootloader, + * but leaves serial clocks on. + */ + omap_writel(0x3 << 29, MOD_CONF_CTRL_0); +#endif + + /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ + reg = omap_readw(SOFT_REQ_REG) & (1 << 4); + omap_writew(reg, SOFT_REQ_REG); + if (!cpu_is_omap15xx()) + omap_writew(0, SOFT_REQ_REG2); + + clk_init(&omap1_clk_functions); + + /* By default all idlect1 clocks are allowed to idle */ + arm_idlect1_mask = ~0; + + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + clk_preinit(c->lk.clk); + + cpu_mask = 0; + if (cpu_is_omap16xx()) + cpu_mask |= CK_16XX; + if (cpu_is_omap1510()) + cpu_mask |= CK_1510; + if (cpu_is_omap7xx()) + cpu_mask |= CK_7XX; + if (cpu_is_omap310()) + cpu_mask |= CK_310; + + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + if (c->cpu & cpu_mask) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + } + + info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); + if (info != NULL) { + if (!cpu_is_omap15xx()) + crystal_type = info->system_clock_type; + } + +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) + ck_ref.rate = 13000000; +#elif defined(CONFIG_ARCH_OMAP16XX) + if (crystal_type == 2) + ck_ref.rate = 19200000; +#endif + + printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", + omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + omap_readw(ARM_CKCTL)); + + /* We want to be in syncronous scalable mode */ + omap_writew(0x1000, ARM_SYSST); + +#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER + /* Use values set by bootloader. Determine PLL rate and recalculate + * dependent clocks as if kernel had changed PLL or divisors. + */ + { + unsigned pll_ctl_val = omap_readw(DPLL_CTL); + + ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ + if (pll_ctl_val & 0x10) { + /* PLL enabled, apply multiplier and divisor */ + if (pll_ctl_val & 0xf80) + ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; + ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; + } else { + /* PLL disabled, apply bypass divisor */ + switch (pll_ctl_val & 0xc) { + case 0: + break; + case 0x4: + ck_dpll1.rate /= 2; + break; + default: + ck_dpll1.rate /= 4; + break; + } + } + } +#else + /* Find the highest supported frequency and enable it */ + if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { + printk(KERN_ERR "System frequencies not set. Check your config.\n"); + /* Guess sane values (60MHz) */ + omap_writew(0x2290, DPLL_CTL); + omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); + ck_dpll1.rate = 60000000; + } +#endif + propagate_rate(&ck_dpll1); + /* Cache rates for clocks connected to ck_ref (not dpll1) */ + propagate_rate(&ck_ref); + printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " + "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); + +#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) + /* Select slicer output as OMAP input clock */ + omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); +#endif + + /* Amstrad Delta wants BCLK high when inactive */ + if (machine_is_ams_delta()) + omap_writel(omap_readl(ULPD_CLOCK_CTRL) | + (1 << SDW_MCLK_INV_BIT), + ULPD_CLOCK_CTRL); + + /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ + /* (on 730, bit 13 must not be cleared) */ + if (cpu_is_omap7xx()) + omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); + else + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + + /* Put DSP/MPUI into reset until needed */ + omap_writew(0, ARM_RSTCT1); + omap_writew(1, ARM_RSTCT2); + omap_writew(0x400, ARM_IDLECT1); + + /* + * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) + * of the ARM_IDLECT2 register must be set to zero. The power-on + * default value of this bit is one. + */ + omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable(&armper_ck.clk); + clk_enable(&armxor_ck.clk); + clk_enable(&armtim_ck.clk); /* This should be done by timer code */ + + if (cpu_is_omap15xx()) + clk_enable(&arm_gpio_ck); + + return 0; +} diff --git a/trunk/arch/arm/mach-omap1/clock.h b/trunk/arch/arm/mach-omap1/clock.h index a4190afb8614..29ffa97dc7f3 100644 --- a/trunk/arch/arm/mach-omap1/clock.h +++ b/trunk/arch/arm/mach-omap1/clock.h @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap1/clock.h * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation + * Copyright (C) 2004 - 2005 Nokia corporation * Written by Tuukka Tikkanen * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc * @@ -13,36 +13,30 @@ #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H #define __ARCH_ARM_MACH_OMAP1_CLOCK_H -#include - -#include - -extern int __init omap1_clk_init(void); -extern int omap1_clk_enable(struct clk *clk); -extern void omap1_clk_disable(struct clk *clk); -extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_ckctl_recalc(struct clk *clk); -extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_sossi_recalc(struct clk *clk); -extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); -extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); -extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_uart_recalc(struct clk *clk); -extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); -extern void omap1_init_ext_clk(struct clk *clk); -extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern unsigned long omap1_watchdog_recalc(struct clk *clk); - -#ifdef CONFIG_OMAP_RESET_CLOCKS -extern void __init omap1_clk_disable_unused(struct clk *clk); -#else -#define omap1_clk_disable_unused NULL -#endif +static unsigned long omap1_ckctl_recalc(struct clk *clk); +static unsigned long omap1_watchdog_recalc(struct clk *clk); +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); +static unsigned long omap1_sossi_recalc(struct clk *clk); +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); +static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); +static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); +static unsigned long omap1_uart_recalc(struct clk *clk); +static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); +static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); +static void omap1_init_ext_clk(struct clk * clk); +static int omap1_select_table_rate(struct clk * clk, unsigned long rate); +static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); + +static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); +static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); + +struct mpu_rate { + unsigned long rate; + unsigned long xtal; + unsigned long pll_rate; + __u16 ckctl_val; + __u16 dpllctl_val; +}; struct uart_clk { struct clk clk; @@ -102,12 +96,596 @@ struct arm_idlect1_clk { #define SOFT_REQ_REG 0xfffe0834 #define SOFT_REQ_REG2 0xfffe0880 -extern __u32 arm_idlect1_mask; -extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; +/*------------------------------------------------------------------------- + * Omap1 MPU rate table + *-------------------------------------------------------------------------*/ +static struct mpu_rate rate_table[] = { + /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL + * NOTE: Comment order here is different from bits in CKCTL value: + * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv + */ +#if defined(CONFIG_OMAP_ARM_216MHZ) + { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_195MHZ) + { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_192MHZ) + { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ + { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ + { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ + { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ + { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_182MHZ) + { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_168MHZ) + { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ +#endif +#if defined(CONFIG_OMAP_ARM_150MHZ) + { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ +#endif +#if defined(CONFIG_OMAP_ARM_120MHZ) + { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ +#endif +#if defined(CONFIG_OMAP_ARM_96MHZ) + { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ +#endif +#if defined(CONFIG_OMAP_ARM_60MHZ) + { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ +#endif +#if defined(CONFIG_OMAP_ARM_30MHZ) + { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ +#endif + { 0, 0, 0, 0, 0 }, +}; + +/*------------------------------------------------------------------------- + * Omap1 clocks + *-------------------------------------------------------------------------*/ + +static struct clk ck_ref = { + .name = "ck_ref", + .ops = &clkops_null, + .rate = 12000000, +}; + +static struct clk ck_dpll1 = { + .name = "ck_dpll1", + .ops = &clkops_null, + .parent = &ck_ref, +}; + +static struct arm_idlect1_clk ck_dpll1out = { + .clk = { + .name = "ck_dpll1out", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_CKOUT_ARM, + .recalc = &followparent_recalc, + }, + .idlect_shift = 12, +}; + +static struct clk sossi_ck = { + .name = "ck_sossi", + .ops = &clkops_generic, + .parent = &ck_dpll1out.clk, + .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), + .enable_bit = 16, + .recalc = &omap1_sossi_recalc, + .set_rate = &omap1_set_sossi_rate, +}; + +static struct clk arm_ck = { + .name = "arm_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .rate_offset = CKCTL_ARMDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct arm_idlect1_clk armper_ck = { + .clk = { + .name = "armper_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = 2, +}; + +static struct clk arm_gpio_ck = { + .name = "arm_gpio_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_GPIOCK, + .recalc = &followparent_recalc, +}; + +static struct arm_idlect1_clk armxor_ck = { + .clk = { + .name = "armxor_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = 1, +}; + +static struct arm_idlect1_clk armtim_ck = { + .clk = { + .name = "armtim_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_TIMCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = 9, +}; + +static struct arm_idlect1_clk armwdt_ck = { + .clk = { + .name = "armwdt_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_WDTCK, + .recalc = &omap1_watchdog_recalc, + }, + .idlect_shift = 0, +}; + +static struct clk arminth_ck16xx = { + .name = "arminth_ck", + .ops = &clkops_null, + .parent = &arm_ck, + .recalc = &followparent_recalc, + /* Note: On 16xx the frequency can be divided by 2 by programming + * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 + * + * 1510 version is in TC clocks. + */ +}; + +static struct clk dsp_ck = { + .name = "dsp_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), + .enable_bit = EN_DSPCK, + .rate_offset = CKCTL_DSPDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct clk dspmmu_ck = { + .name = "dspmmu_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .rate_offset = CKCTL_DSPMMUDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct clk dspper_ck = { + .name = "dspper_ck", + .ops = &clkops_dspck, + .parent = &ck_dpll1, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc_dsp_domain, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = &omap1_clk_set_rate_dsp_domain, +}; + +static struct clk dspxor_ck = { + .name = "dspxor_ck", + .ops = &clkops_dspck, + .parent = &ck_ref, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, +}; + +static struct clk dsptim_ck = { + .name = "dsptim_ck", + .ops = &clkops_dspck, + .parent = &ck_ref, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_DSPTIMCK, + .recalc = &followparent_recalc, +}; + +/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ +static struct arm_idlect1_clk tc_ck = { + .clk = { + .name = "tc_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .rate_offset = CKCTL_TCDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = 6, +}; + +static struct clk arminth_ck1510 = { + .name = "arminth_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, + /* Note: On 1510 the frequency follows TC_CK + * + * 16xx version is in MPU clocks. + */ +}; + +static struct clk tipb_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "tipb_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk l3_ocpi_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "l3_ocpi_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_OCPI_CK, + .recalc = &followparent_recalc, +}; + +static struct clk tc1_ck = { + .name = "tc1_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_TC1_CK, + .recalc = &followparent_recalc, +}; -extern const struct clkops clkops_dspck; -extern const struct clkops clkops_dummy; -extern const struct clkops clkops_uart; -extern const struct clkops clkops_generic; +static struct clk tc2_ck = { + .name = "tc2_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_TC2_CK, + .recalc = &followparent_recalc, +}; + +static struct clk dma_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "dma_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk dma_lcdfree_ck = { + .name = "dma_lcdfree_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct arm_idlect1_clk api_ck = { + .clk = { + .name = "api_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_APICK, + .recalc = &followparent_recalc, + }, + .idlect_shift = 8, +}; + +static struct arm_idlect1_clk lb_ck = { + .clk = { + .name = "lb_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LBCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = 4, +}; + +static struct clk rhea1_ck = { + .name = "rhea1_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk rhea2_ck = { + .name = "rhea2_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk lcd_ck_16xx = { + .name = "lcd_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct arm_idlect1_clk lcd_ck_1510 = { + .clk = { + .name = "lcd_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = 3, +}; + +static struct clk uart1_1510 = { + .name = "uart1_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +static struct uart_clk uart1_16xx = { + .clk = { + .name = "uart1_ck", + .ops = &clkops_uart, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT | + CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 29, + }, + .sysc_addr = 0xfffb0054, +}; + +static struct clk uart2_ck = { + .name = "uart2_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +static struct clk uart3_1510 = { + .name = "uart3_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +static struct uart_clk uart3_16xx = { + .clk = { + .name = "uart3_ck", + .ops = &clkops_uart, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT | + CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 31, + }, + .sysc_addr = 0xfffb9854, +}; + +static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ + .name = "usb_clko", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 6000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), + .enable_bit = USB_MCLK_EN_BIT, +}; + +static struct clk usb_hhc_ck1510 = { + .name = "usb_hhc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ + .flags = RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = USB_HOST_HHC_UHOST_EN, +}; + +static struct clk usb_hhc_ck16xx = { + .name = "usb_hhc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, + /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ + .flags = RATE_FIXED | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ + .enable_bit = 8 /* UHOST_EN */, +}; + +static struct clk usb_dc_ck = { + .name = "usb_dc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, + .flags = RATE_FIXED, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 4, +}; + +static struct clk usb_dc_ck7xx = { + .name = "usb_dc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, + .flags = RATE_FIXED, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 8, +}; + +static struct clk mclk_1510 = { + .name = "mclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, + .flags = RATE_FIXED, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 6, +}; + +static struct clk mclk_16xx = { + .name = "mclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), + .enable_bit = COM_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, +}; + +static struct clk bclk_1510 = { + .name = "bclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, + .flags = RATE_FIXED, +}; + +static struct clk bclk_16xx = { + .name = "bclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), + .enable_bit = SWD_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, +}; + +static struct clk mmc1_ck = { + .name = "mmc_ck", + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 23, +}; + +static struct clk mmc2_ck = { + .name = "mmc_ck", + .id = 1, + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 20, +}; + +static struct clk mmc3_ck = { + .name = "mmc_ck", + .id = 2, + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 12, +}; + +static struct clk virtual_ck_mpu = { + .name = "mpu", + .ops = &clkops_null, + .parent = &arm_ck, /* Is smarter alias for */ + .recalc = &followparent_recalc, + .set_rate = &omap1_select_table_rate, + .round_rate = &omap1_round_to_table_rate, +}; + +/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK +remains active during MPU idle whenever this is enabled */ +static struct clk i2c_fck = { + .name = "i2c_fck", + .id = 1, + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, + .parent = &armxor_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c_ick = { + .name = "i2c_ick", + .id = 1, + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, + .parent = &armper_ck.clk, + .recalc = &followparent_recalc, +}; #endif diff --git a/trunk/arch/arm/mach-omap1/clock_data.c b/trunk/arch/arm/mach-omap1/clock_data.c deleted file mode 100644 index ab995a9c606c..000000000000 --- a/trunk/arch/arm/mach-omap1/clock_data.c +++ /dev/null @@ -1,843 +0,0 @@ -/* - * linux/arch/arm/mach-omap1/clock_data.c - * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include /* for machine_is_* */ - -#include -#include -#include -#include /* for OTG_BASE */ - -#include "clock.h" - -/*------------------------------------------------------------------------ - * Omap1 clocks - *-------------------------------------------------------------------------*/ - -/* XXX is this necessary? */ -static struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_dummy, - .flags = RATE_FIXED, -}; - -static struct clk ck_ref = { - .name = "ck_ref", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk ck_dpll1 = { - .name = "ck_dpll1", - .ops = &clkops_null, - .parent = &ck_ref, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ FIX: SoSSI, SSR ] - */ -static struct arm_idlect1_clk ck_dpll1out = { - .clk = { - .name = "ck_dpll1out", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | - ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_CKOUT_ARM, - .recalc = &followparent_recalc, - }, - .idlect_shift = 12, -}; - -static struct clk sossi_ck = { - .name = "ck_sossi", - .ops = &clkops_generic, - .parent = &ck_dpll1out.clk, - .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), - .enable_bit = 16, - .recalc = &omap1_sossi_recalc, - .set_rate = &omap1_set_sossi_rate, -}; - -static struct clk arm_ck = { - .name = "arm_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .rate_offset = CKCTL_ARMDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct arm_idlect1_clk armper_ck = { - .clk = { - .name = "armper_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = 2, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ GPIO code for 1510 ] - */ -static struct clk arm_gpio_ck = { - .name = "arm_gpio_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_GPIOCK, - .recalc = &followparent_recalc, -}; - -static struct arm_idlect1_clk armxor_ck = { - .clk = { - .name = "armxor_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = 1, -}; - -static struct arm_idlect1_clk armtim_ck = { - .clk = { - .name = "armtim_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_TIMCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = 9, -}; - -static struct arm_idlect1_clk armwdt_ck = { - .clk = { - .name = "armwdt_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_WDTCK, - .recalc = &omap1_watchdog_recalc, - }, - .idlect_shift = 0, -}; - -static struct clk arminth_ck16xx = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &arm_ck, - .recalc = &followparent_recalc, - /* Note: On 16xx the frequency can be divided by 2 by programming - * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 - * - * 1510 version is in TC clocks. - */ -}; - -static struct clk dsp_ck = { - .name = "dsp_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), - .enable_bit = EN_DSPCK, - .rate_offset = CKCTL_DSPDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct clk dspmmu_ck = { - .name = "dspmmu_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .rate_offset = CKCTL_DSPMMUDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct clk dspper_ck = { - .name = "dspper_ck", - .ops = &clkops_dspck, - .parent = &ck_dpll1, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc_dsp_domain, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = &omap1_clk_set_rate_dsp_domain, -}; - -static struct clk dspxor_ck = { - .name = "dspxor_ck", - .ops = &clkops_dspck, - .parent = &ck_ref, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, -}; - -static struct clk dsptim_ck = { - .name = "dsptim_ck", - .ops = &clkops_dspck, - .parent = &ck_ref, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_DSPTIMCK, - .recalc = &followparent_recalc, -}; - -/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ -static struct arm_idlect1_clk tc_ck = { - .clk = { - .name = "tc_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .rate_offset = CKCTL_TCDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = 6, -}; - -static struct clk arminth_ck1510 = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, - /* Note: On 1510 the frequency follows TC_CK - * - * 16xx version is in MPU clocks. - */ -}; - -static struct clk tipb_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "tipb_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk l3_ocpi_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_OCPI_CK, - .recalc = &followparent_recalc, -}; - -static struct clk tc1_ck = { - .name = "tc1_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_TC1_CK, - .recalc = &followparent_recalc, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ pm.c (SRAM), CCP, Camera ] - */ -static struct clk tc2_ck = { - .name = "tc2_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_TC2_CK, - .recalc = &followparent_recalc, -}; - -static struct clk dma_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct arm_idlect1_clk api_ck = { - .clk = { - .name = "api_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_APICK, - .recalc = &followparent_recalc, - }, - .idlect_shift = 8, -}; - -static struct arm_idlect1_clk lb_ck = { - .clk = { - .name = "lb_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LBCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = 4, -}; - -static struct clk rhea1_ck = { - .name = "rhea1_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk rhea2_ck = { - .name = "rhea2_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk lcd_ck_16xx = { - .name = "lcd_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct arm_idlect1_clk lcd_ck_1510 = { - .clk = { - .name = "lcd_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = 3, -}; - -static struct clk uart1_1510 = { - .name = "uart1_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -static struct uart_clk uart1_16xx = { - .clk = { - .name = "uart1_ck", - .ops = &clkops_uart, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 29, - }, - .sysc_addr = 0xfffb0054, -}; - -static struct clk uart2_ck = { - .name = "uart2_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -static struct clk uart3_1510 = { - .name = "uart3_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -static struct uart_clk uart3_16xx = { - .clk = { - .name = "uart3_ck", - .ops = &clkops_uart, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | - CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 31, - }, - .sysc_addr = 0xfffb9854, -}; - -static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ - .name = "usb_clko", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 6000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), - .enable_bit = USB_MCLK_EN_BIT, -}; - -static struct clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = USB_HOST_HHC_UHOST_EN, -}; - -static struct clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = RATE_FIXED | ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ - .enable_bit = 8 /* UHOST_EN */, -}; - -static struct clk usb_dc_ck = { - .name = "usb_dc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - .flags = RATE_FIXED, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 4, -}; - -static struct clk usb_dc_ck7xx = { - .name = "usb_dc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - .flags = RATE_FIXED, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 8, -}; - -static struct clk mclk_1510 = { - .name = "mclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = RATE_FIXED, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 6, -}; - -static struct clk mclk_16xx = { - .name = "mclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), - .enable_bit = COM_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, -}; - -static struct clk bclk_1510 = { - .name = "bclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .flags = RATE_FIXED, -}; - -static struct clk bclk_16xx = { - .name = "bclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), - .enable_bit = SWD_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, -}; - -static struct clk mmc1_ck = { - .name = "mmc_ck", - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 23, -}; - -static struct clk mmc2_ck = { - .name = "mmc_ck", - .id = 1, - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 20, -}; - -static struct clk mmc3_ck = { - .name = "mmc_ck", - .id = 2, - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 12, -}; - -static struct clk virtual_ck_mpu = { - .name = "mpu", - .ops = &clkops_null, - .parent = &arm_ck, /* Is smarter alias for */ - .recalc = &followparent_recalc, - .set_rate = &omap1_select_table_rate, - .round_rate = &omap1_round_to_table_rate, -}; - -/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK -remains active during MPU idle whenever this is enabled */ -static struct clk i2c_fck = { - .name = "i2c_fck", - .id = 1, - .ops = &clkops_null, - .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armxor_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c_ick = { - .name = "i2c_ick", - .id = 1, - .ops = &clkops_null, - .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armper_ck.clk, - .recalc = &followparent_recalc, -}; - -/* - * clkdev integration - */ - -static struct omap_clk omap_clks[] = { - /* non-ULPD clocks */ - CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), - /* CK_GEN1 clocks */ - CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), - CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), - CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), - CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), - CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), - /* CK_GEN2 clocks */ - CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), - /* CK_GEN3 clocks */ - CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), - CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), - CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), - CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), - CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), - CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), - CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), - CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), - CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), - CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), - /* ULPD clocks */ - CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), - CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), - CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), - CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), - CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), - CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), - CLK(NULL, "mclk", &mclk_16xx, CK_16XX), - CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), - CLK(NULL, "bclk", &bclk_16xx, CK_16XX), - CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), - CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), - CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), - CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), - /* Virtual clocks */ - CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), - CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), - CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), - CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), -}; - -/* - * init - */ - -static struct clk_functions omap1_clk_functions __initdata = { - .clk_enable = omap1_clk_enable, - .clk_disable = omap1_clk_disable, - .clk_round_rate = omap1_clk_round_rate, - .clk_set_rate = omap1_clk_set_rate, - .clk_disable_unused = omap1_clk_disable_unused, -}; - -int __init omap1_clk_init(void) -{ - struct omap_clk *c; - const struct omap_clock_config *info; - int crystal_type = 0; /* Default 12 MHz */ - u32 reg, cpu_mask; - -#ifdef CONFIG_DEBUG_LL - /* - * Resets some clocks that may be left on from bootloader, - * but leaves serial clocks on. - */ - omap_writel(0x3 << 29, MOD_CONF_CTRL_0); -#endif - - /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ - reg = omap_readw(SOFT_REQ_REG) & (1 << 4); - omap_writew(reg, SOFT_REQ_REG); - if (!cpu_is_omap15xx()) - omap_writew(0, SOFT_REQ_REG2); - - clk_init(&omap1_clk_functions); - - /* By default all idlect1 clocks are allowed to idle */ - arm_idlect1_mask = ~0; - - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_preinit(c->lk.clk); - - cpu_mask = 0; - if (cpu_is_omap16xx()) - cpu_mask |= CK_16XX; - if (cpu_is_omap1510()) - cpu_mask |= CK_1510; - if (cpu_is_omap7xx()) - cpu_mask |= CK_7XX; - if (cpu_is_omap310()) - cpu_mask |= CK_310; - - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - if (c->cpu & cpu_mask) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - } - - /* Pointers to these clocks are needed by code in clock.c */ - api_ck_p = clk_get(NULL, "api_ck"); - ck_dpll1_p = clk_get(NULL, "ck_dpll1"); - ck_ref_p = clk_get(NULL, "ck_ref"); - - info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); - if (info != NULL) { - if (!cpu_is_omap15xx()) - crystal_type = info->system_clock_type; - } - -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - ck_ref.rate = 13000000; -#elif defined(CONFIG_ARCH_OMAP16XX) - if (crystal_type == 2) - ck_ref.rate = 19200000; -#endif - - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " - "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), - omap_readw(ARM_CKCTL)); - - /* We want to be in syncronous scalable mode */ - omap_writew(0x1000, ARM_SYSST); - -#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER - /* Use values set by bootloader. Determine PLL rate and recalculate - * dependent clocks as if kernel had changed PLL or divisors. - */ - { - unsigned pll_ctl_val = omap_readw(DPLL_CTL); - - ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ - if (pll_ctl_val & 0x10) { - /* PLL enabled, apply multiplier and divisor */ - if (pll_ctl_val & 0xf80) - ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; - ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; - } else { - /* PLL disabled, apply bypass divisor */ - switch (pll_ctl_val & 0xc) { - case 0: - break; - case 0x4: - ck_dpll1.rate /= 2; - break; - default: - ck_dpll1.rate /= 4; - break; - } - } - } -#else - /* Find the highest supported frequency and enable it */ - if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { - printk(KERN_ERR "System frequencies not set. Check your config.\n"); - /* Guess sane values (60MHz) */ - omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); - ck_dpll1.rate = 60000000; - } -#endif - propagate_rate(&ck_dpll1); - /* Cache rates for clocks connected to ck_ref (not dpll1) */ - propagate_rate(&ck_ref); - printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " - "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); - -#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) - /* Select slicer output as OMAP input clock */ - omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); -#endif - - /* Amstrad Delta wants BCLK high when inactive */ - if (machine_is_ams_delta()) - omap_writel(omap_readl(ULPD_CLOCK_CTRL) | - (1 << SDW_MCLK_INV_BIT), - ULPD_CLOCK_CTRL); - - /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - /* (on 730, bit 13 must not be cleared) */ - if (cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); - else - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); - - /* Put DSP/MPUI into reset until needed */ - omap_writew(0, ARM_RSTCT1); - omap_writew(1, ARM_RSTCT2); - omap_writew(0x400, ARM_IDLECT1); - - /* - * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) - * of the ARM_IDLECT2 register must be set to zero. The power-on - * default value of this bit is one. - */ - omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable(&armper_ck.clk); - clk_enable(&armxor_ck.clk); - clk_enable(&armtim_ck.clk); /* This should be done by timer code */ - - if (cpu_is_omap15xx()) - clk_enable(&arm_gpio_ck); - - return 0; -} diff --git a/trunk/arch/arm/mach-omap1/i2c.c b/trunk/arch/arm/mach-omap1/i2c.c deleted file mode 100644 index 1bf4735e27a6..000000000000 --- a/trunk/arch/arm/mach-omap1/i2c.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Helper module for board specific I2C bus registration - * - * Copyright (C) 2009 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include -#include -#include - -int __init omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len) -{ - if (cpu_is_omap7xx()) { - omap_cfg_reg(I2C_7XX_SDA); - omap_cfg_reg(I2C_7XX_SCL); - } else { - omap_cfg_reg(I2C_SDA); - omap_cfg_reg(I2C_SCL); - } - - return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); -} diff --git a/trunk/arch/arm/mach-omap1/include/mach/lcd_dma.h b/trunk/arch/arm/mach-omap1/include/mach/lcd_dma.h deleted file mode 100644 index d7a457bbcb7f..000000000000 --- a/trunk/arch/arm/mach-omap1/include/mach/lcd_dma.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/lcd_dma.h - * - * Extracted from arch/arm/plat-omap/include/plat/dma.h - * Copyright (C) 2003 Nokia Corporation - * Author: Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __MACH_OMAP1_LCD_DMA_H__ -#define __MACH_OMAP1_LCD_DMA_H__ - -/* Hardware registers for LCD DMA */ -#define OMAP1510_DMA_LCD_BASE (0xfffedb00) -#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) -#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) -#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) -#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) -#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) - -#define OMAP1610_DMA_LCD_BASE (0xfffee300) -#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) -#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) -#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) -#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) -#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) -#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) -#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) -#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) -#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) -#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) -#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) -#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) -#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) -#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) -#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) -#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) -#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) - -/* LCD DMA block numbers */ -enum { - OMAP_LCD_DMA_B1_TOP, - OMAP_LCD_DMA_B1_BOTTOM, - OMAP_LCD_DMA_B2_TOP, - OMAP_LCD_DMA_B2_BOTTOM -}; - -/* LCD DMA functions */ -extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), - void *data); -extern void omap_free_lcd_dma(void); -extern void omap_setup_lcd_dma(void); -extern void omap_enable_lcd_dma(void); -extern void omap_stop_lcd_dma(void); -extern void omap_set_lcd_dma_ext_controller(int external); -extern void omap_set_lcd_dma_single_transfer(int single); -extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, - int data_type); -extern void omap_set_lcd_dma_b1_rotation(int rotate); -extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); -extern void omap_set_lcd_dma_b1_mirror(int mirror); -extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); - -extern int omap_lcd_dma_running(void); - -#endif /* __MACH_OMAP1_LCD_DMA_H__ */ diff --git a/trunk/arch/arm/mach-omap1/include/mach/lcdc.h b/trunk/arch/arm/mach-omap1/include/mach/lcdc.h deleted file mode 100644 index 89bd703adaf6..000000000000 --- a/trunk/arch/arm/mach-omap1/include/mach/lcdc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/lcdc.h - * - * Extracted from drivers/video/omap/lcdc.c - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __MACH_LCDC_H__ -#define __MACH_LCDC_H__ - -#define OMAP_LCDC_BASE 0xfffec000 -#define OMAP_LCDC_SIZE 256 -#define OMAP_LCDC_IRQ INT_LCD_CTRL - -#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) -#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) -#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) -#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) -#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) -#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) -#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) -#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) - -#define OMAP_LCDC_STAT_DONE (1 << 0) -#define OMAP_LCDC_STAT_VSYNC (1 << 1) -#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) -#define OMAP_LCDC_STAT_ABC (1 << 3) -#define OMAP_LCDC_STAT_LINE_INT (1 << 4) -#define OMAP_LCDC_STAT_FUF (1 << 5) -#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) - -#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) -#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) -#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) - -#define OMAP_LCDC_IRQ_VSYNC (1 << 2) -#define OMAP_LCDC_IRQ_DONE (1 << 3) -#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) -#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) -#define OMAP_LCDC_IRQ_LINE (1 << 6) -#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) - -#endif /* __MACH_LCDC_H__ */ diff --git a/trunk/arch/arm/mach-omap1/io.c b/trunk/arch/arm/mach-omap1/io.c index d9b8d82530ae..2a6d68aa3489 100644 --- a/trunk/arch/arm/mach-omap1/io.c +++ b/trunk/arch/arm/mach-omap1/io.c @@ -18,8 +18,7 @@ #include #include -#include "clock.h" - +extern int omap1_clk_init(void); extern void omap_check_revision(void); extern void omap_sram_init(void); extern void omapfb_reserve_sdram(void); diff --git a/trunk/arch/arm/mach-omap1/lcd_dma.c b/trunk/arch/arm/mach-omap1/lcd_dma.c deleted file mode 100644 index 3be11af687bb..000000000000 --- a/trunk/arch/arm/mach-omap1/lcd_dma.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * linux/arch/arm/mach-omap1/lcd_dma.c - * - * Extracted from arch/arm/plat-omap/dma.c - * Copyright (C) 2003 - 2008 Nokia Corporation - * Author: Juha Yrjölä - * DMA channel linking for 1610 by Samuel Ortiz - * Graphics DMA and LCD DMA graphics tranformations - * by Imre Deak - * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. - * Merged to support both OMAP1 and OMAP2 by Tony Lindgren - * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar - * - * Support functions for the OMAP internal DMA channels. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include - -#include -#include -#include - -int omap_lcd_dma_running(void) -{ - /* - * On OMAP1510, internal LCD controller will start the transfer - * when it gets enabled, so assume DMA running if LCD enabled. - */ - if (cpu_is_omap1510()) - if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN) - return 1; - - /* Check if LCD DMA is running */ - if (cpu_is_omap16xx()) - if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) - return 1; - - return 0; -} - -static struct lcd_dma_info { - spinlock_t lock; - int reserved; - void (*callback)(u16 status, void *data); - void *cb_data; - - int active; - unsigned long addr, size; - int rotate, data_type, xres, yres; - int vxres; - int mirror; - int xscale, yscale; - int ext_ctrl; - int src_port; - int single_transfer; -} lcd_dma; - -void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, - int data_type) -{ - lcd_dma.addr = addr; - lcd_dma.data_type = data_type; - lcd_dma.xres = fb_xres; - lcd_dma.yres = fb_yres; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1); - -void omap_set_lcd_dma_src_port(int port) -{ - lcd_dma.src_port = port; -} - -void omap_set_lcd_dma_ext_controller(int external) -{ - lcd_dma.ext_ctrl = external; -} -EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); - -void omap_set_lcd_dma_single_transfer(int single) -{ - lcd_dma.single_transfer = single; -} -EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); - -void omap_set_lcd_dma_b1_rotation(int rotate) -{ - if (cpu_is_omap1510()) { - printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); - BUG(); - return; - } - lcd_dma.rotate = rotate; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); - -void omap_set_lcd_dma_b1_mirror(int mirror) -{ - if (cpu_is_omap1510()) { - printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n"); - BUG(); - } - lcd_dma.mirror = mirror; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); - -void omap_set_lcd_dma_b1_vxres(unsigned long vxres) -{ - if (cpu_is_omap1510()) { - printk(KERN_ERR "DMA virtual resulotion is not supported " - "in 1510 mode\n"); - BUG(); - } - lcd_dma.vxres = vxres; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); - -void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) -{ - if (cpu_is_omap1510()) { - printk(KERN_ERR "DMA scale is not supported in 1510 mode\n"); - BUG(); - } - lcd_dma.xscale = xscale; - lcd_dma.yscale = yscale; -} -EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); - -static void set_b1_regs(void) -{ - unsigned long top, bottom; - int es; - u16 w; - unsigned long en, fn; - long ei, fi; - unsigned long vxres; - unsigned int xscale, yscale; - - switch (lcd_dma.data_type) { - case OMAP_DMA_DATA_TYPE_S8: - es = 1; - break; - case OMAP_DMA_DATA_TYPE_S16: - es = 2; - break; - case OMAP_DMA_DATA_TYPE_S32: - es = 4; - break; - default: - BUG(); - return; - } - - vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres; - xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; - yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; - BUG_ON(vxres < lcd_dma.xres); - -#define PIXADDR(x, y) (lcd_dma.addr + \ - ((y) * vxres * yscale + (x) * xscale) * es) -#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) - - switch (lcd_dma.rotate) { - case 0: - if (!lcd_dma.mirror) { - top = PIXADDR(0, 0); - bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - /* 1510 DMA requires the bottom address to be 2 more - * than the actual last memory access location. */ - if (cpu_is_omap1510() && - lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) - bottom += 2; - ei = PIXSTEP(0, 0, 1, 0); - fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); - } else { - top = PIXADDR(lcd_dma.xres - 1, 0); - bottom = PIXADDR(0, lcd_dma.yres - 1); - ei = PIXSTEP(1, 0, 0, 0); - fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1); - } - en = lcd_dma.xres; - fn = lcd_dma.yres; - break; - case 90: - if (!lcd_dma.mirror) { - top = PIXADDR(0, lcd_dma.yres - 1); - bottom = PIXADDR(lcd_dma.xres - 1, 0); - ei = PIXSTEP(0, 1, 0, 0); - fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1); - } else { - top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - bottom = PIXADDR(0, 0); - ei = PIXSTEP(0, 1, 0, 0); - fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1); - } - en = lcd_dma.yres; - fn = lcd_dma.xres; - break; - case 180: - if (!lcd_dma.mirror) { - top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - bottom = PIXADDR(0, 0); - ei = PIXSTEP(1, 0, 0, 0); - fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0); - } else { - top = PIXADDR(0, lcd_dma.yres - 1); - bottom = PIXADDR(lcd_dma.xres - 1, 0); - ei = PIXSTEP(0, 0, 1, 0); - fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0); - } - en = lcd_dma.xres; - fn = lcd_dma.yres; - break; - case 270: - if (!lcd_dma.mirror) { - top = PIXADDR(lcd_dma.xres - 1, 0); - bottom = PIXADDR(0, lcd_dma.yres - 1); - ei = PIXSTEP(0, 0, 0, 1); - fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0); - } else { - top = PIXADDR(0, 0); - bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); - ei = PIXSTEP(0, 0, 0, 1); - fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0); - } - en = lcd_dma.yres; - fn = lcd_dma.xres; - break; - default: - BUG(); - return; /* Suppress warning about uninitialized vars */ - } - - if (cpu_is_omap1510()) { - omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); - omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); - omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); - omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); - - return; - } - - /* 1610 regs */ - omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); - omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); - omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); - omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); - - omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); - omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); - - w = omap_readw(OMAP1610_DMA_LCD_CSDP); - w &= ~0x03; - w |= lcd_dma.data_type; - omap_writew(w, OMAP1610_DMA_LCD_CSDP); - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - /* Always set the source port as SDRAM for now*/ - w &= ~(0x03 << 6); - if (lcd_dma.callback != NULL) - w |= 1 << 1; /* Block interrupt enable */ - else - w &= ~(1 << 1); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - - if (!(lcd_dma.rotate || lcd_dma.mirror || - lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale)) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - /* Set the double-indexed addressing mode */ - w |= (0x03 << 12); - omap_writew(w, OMAP1610_DMA_LCD_CCR); - - omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); - omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); - omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); -} - -static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) -{ - u16 w; - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - if (unlikely(!(w & (1 << 3)))) { - printk(KERN_WARNING "Spurious LCD DMA IRQ\n"); - return IRQ_NONE; - } - /* Ack the IRQ */ - w |= (1 << 3); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - lcd_dma.active = 0; - if (lcd_dma.callback != NULL) - lcd_dma.callback(w, lcd_dma.cb_data); - - return IRQ_HANDLED; -} - -int omap_request_lcd_dma(void (*callback)(u16 status, void *data), - void *data) -{ - spin_lock_irq(&lcd_dma.lock); - if (lcd_dma.reserved) { - spin_unlock_irq(&lcd_dma.lock); - printk(KERN_ERR "LCD DMA channel already reserved\n"); - BUG(); - return -EBUSY; - } - lcd_dma.reserved = 1; - spin_unlock_irq(&lcd_dma.lock); - lcd_dma.callback = callback; - lcd_dma.cb_data = data; - lcd_dma.active = 0; - lcd_dma.single_transfer = 0; - lcd_dma.rotate = 0; - lcd_dma.vxres = 0; - lcd_dma.mirror = 0; - lcd_dma.xscale = 0; - lcd_dma.yscale = 0; - lcd_dma.ext_ctrl = 0; - lcd_dma.src_port = 0; - - return 0; -} -EXPORT_SYMBOL(omap_request_lcd_dma); - -void omap_free_lcd_dma(void) -{ - spin_lock(&lcd_dma.lock); - if (!lcd_dma.reserved) { - spin_unlock(&lcd_dma.lock); - printk(KERN_ERR "LCD DMA is not reserved\n"); - BUG(); - return; - } - if (!cpu_is_omap1510()) - omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, - OMAP1610_DMA_LCD_CCR); - lcd_dma.reserved = 0; - spin_unlock(&lcd_dma.lock); -} -EXPORT_SYMBOL(omap_free_lcd_dma); - -void omap_enable_lcd_dma(void) -{ - u16 w; - - /* - * Set the Enable bit only if an external controller is - * connected. Otherwise the OMAP internal controller will - * start the transfer when it gets enabled. - */ - if (cpu_is_omap1510() || !lcd_dma.ext_ctrl) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w |= 1 << 8; - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - - lcd_dma.active = 1; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - w |= 1 << 7; - omap_writew(w, OMAP1610_DMA_LCD_CCR); -} -EXPORT_SYMBOL(omap_enable_lcd_dma); - -void omap_setup_lcd_dma(void) -{ - BUG_ON(lcd_dma.active); - if (!cpu_is_omap1510()) { - /* Set some reasonable defaults */ - omap_writew(0x5440, OMAP1610_DMA_LCD_CCR); - omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); - omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); - } - set_b1_regs(); - if (!cpu_is_omap1510()) { - u16 w; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - /* - * If DMA was already active set the end_prog bit to have - * the programmed register set loaded into the active - * register set. - */ - w |= 1 << 11; /* End_prog */ - if (!lcd_dma.single_transfer) - w |= (3 << 8); /* Auto_init, repeat */ - omap_writew(w, OMAP1610_DMA_LCD_CCR); - } -} -EXPORT_SYMBOL(omap_setup_lcd_dma); - -void omap_stop_lcd_dma(void) -{ - u16 w; - - lcd_dma.active = 0; - if (cpu_is_omap1510() || !lcd_dma.ext_ctrl) - return; - - w = omap_readw(OMAP1610_DMA_LCD_CCR); - w &= ~(1 << 7); - omap_writew(w, OMAP1610_DMA_LCD_CCR); - - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w &= ~(1 << 8); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); -} -EXPORT_SYMBOL(omap_stop_lcd_dma); - -static int __init omap_init_lcd_dma(void) -{ - int r; - - if (cpu_is_omap16xx()) { - u16 w; - - /* this would prevent OMAP sleep */ - w = omap_readw(OMAP1610_DMA_LCD_CTRL); - w &= ~(1 << 8); - omap_writew(w, OMAP1610_DMA_LCD_CTRL); - } - - spin_lock_init(&lcd_dma.lock); - - r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, - "LCD DMA", NULL); - if (r != 0) - printk(KERN_ERR "unable to request IRQ for LCD DMA " - "(error %d)\n", r); - - return r; -} - -arch_initcall(omap_init_lcd_dma); - diff --git a/trunk/arch/arm/mach-omap1/mux.c b/trunk/arch/arm/mach-omap1/mux.c index 07212cc621ae..785371e982fc 100644 --- a/trunk/arch/arm/mach-omap1/mux.c +++ b/trunk/arch/arm/mach-omap1/mux.c @@ -50,18 +50,12 @@ MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) -MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0) -MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0) -MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0) +MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0) /* MMC Pins */ MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0) MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0) MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0) - -/* I2C interface */ -MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0) -MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0) }; #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) #else diff --git a/trunk/arch/arm/mach-omap1/opp.h b/trunk/arch/arm/mach-omap1/opp.h deleted file mode 100644 index 07074d79adce..000000000000 --- a/trunk/arch/arm/mach-omap1/opp.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/mach-omap1/opp.h - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H -#define __ARCH_ARM_MACH_OMAP1_OPP_H - -#include - -struct mpu_rate { - unsigned long rate; - unsigned long xtal; - unsigned long pll_rate; - __u16 ckctl_val; - __u16 dpllctl_val; -}; - -extern struct mpu_rate omap1_rate_table[]; - -#endif diff --git a/trunk/arch/arm/mach-omap1/opp_data.c b/trunk/arch/arm/mach-omap1/opp_data.c deleted file mode 100644 index 75a546514994..000000000000 --- a/trunk/arch/arm/mach-omap1/opp_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * linux/arch/arm/mach-omap1/opp_data.c - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "opp.h" - -/*------------------------------------------------------------------------- - * Omap1 MPU rate table - *-------------------------------------------------------------------------*/ -struct mpu_rate omap1_rate_table[] = { - /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL - * NOTE: Comment order here is different from bits in CKCTL value: - * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv - */ -#if defined(CONFIG_OMAP_ARM_216MHZ) - { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_195MHZ) - { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_192MHZ) - { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ - { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ - { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ - { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ - { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_182MHZ) - { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_168MHZ) - { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ -#endif -#if defined(CONFIG_OMAP_ARM_150MHZ) - { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_120MHZ) - { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ -#endif -#if defined(CONFIG_OMAP_ARM_96MHZ) - { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_60MHZ) - { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ -#endif -#if defined(CONFIG_OMAP_ARM_30MHZ) - { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ -#endif - { 0, 0, 0, 0, 0 }, -}; - diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 76c11ee113e9..7309aab305a9 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -24,18 +24,6 @@ config ARCH_OMAP3430 depends on ARCH_OMAP3 && ARCH_OMAP34XX select ARCH_OMAP_OTG -config OMAP_PACKAGE_CBC - bool - -config OMAP_PACKAGE_CBB - bool - -config OMAP_PACKAGE_CUS - bool - -config OMAP_PACKAGE_CBP - bool - comment "OMAP Board Type" depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 @@ -64,17 +52,14 @@ config MACH_OMAP_2430SDP config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP_LDP bool "OMAP3 LDP board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP3EVM bool "OMAP 3530 EVM board" @@ -83,22 +68,14 @@ config MACH_OMAP3EVM config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB - -config MACH_OMAP3_TOUCHBOOK - bool "OMAP3 Touch Book" - depends on ARCH_OMAP3 && ARCH_OMAP34XX - select BACKLIGHT_CLASS_DEVICE config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_NOKIA_N800 bool @@ -119,33 +96,26 @@ config MACH_NOKIA_N8X0 config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM2 bool "OMAP3 Zoom2 board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBP config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CUS - select OMAP_MUX config MACH_IGEP0020 bool "IGEP0020" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBP config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" @@ -158,15 +128,3 @@ config OMAP3_EMU help Say Y here to enable debugging hardware of omap3 -config OMAP3_SDRC_AC_TIMING - bool "Enable SDRC AC timing register changes" - depends on ARCH_OMAP3 && ARCH_OMAP34XX - default n - help - If you know that none of your system initiators will attempt to - access SDRAM during CORE DVFS, select Y here. This should boost - SDRAM performance at lower CORE OPPs. There are relatively few - users who will wish to say yes at this point - almost everyone will - wish to say no. Selecting yes without understanding what is - going on could result in system crashes; - diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index b32678b848bc..32548a4510c5 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -6,14 +6,11 @@ obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o omap-2-3-common = irq.o sdrc.o omap_hwmod.o -omap-3-4-common = dpll.o prcm-common = prcm.o powerdomain.o -clock-common = clock.o clock_common_data.o clockdomain.o +clock-common = clock.o clockdomain.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ - $(omap-3-4-common) -obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o @@ -26,9 +23,6 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o -# Pin multiplexing -obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o - # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o @@ -47,11 +41,8 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o -obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o -obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o -obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o +obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o @@ -64,9 +55,6 @@ iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) -i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o -obj-y += $(i2c-omap-m) $(i2c-omap-y) - # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o @@ -105,8 +93,7 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ mmc-twl4030.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ mmc-twl4030.o -obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ - mmc-twl4030.o + obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 4cfb7b68dfad..5bda9fdbee9e 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -41,7 +42,6 @@ #include #include -#include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" #include "mmc-twl4030.h" @@ -625,9 +625,7 @@ static inline void board_smc91x_init(void) static void enable_board_wakeup_source(void) { - /* T2 interrupt line (keypad) */ - omap_mux_init_signal("sys_nirq", - OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ } static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -642,17 +640,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap_3430sdp_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3430_i2c_init(); platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); if (omap_rev() > OMAP3430_REV_ES1_0) diff --git a/trunk/arch/arm/mach-omap2/board-3630sdp.c b/trunk/arch/arm/mach-omap2/board-3630sdp.c index 739059632811..348b70b98336 100755 --- a/trunk/arch/arm/mach-omap2/board-3630sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3630sdp.c @@ -23,7 +23,6 @@ #include -#include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) @@ -49,9 +48,7 @@ static inline void board_smc91x_init(void) static void enable_board_wakeup_source(void) { - /* T2 interrupt line (keypad) */ - omap_mux_init_signal("sys_nirq", - OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ } static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -85,17 +82,8 @@ static void __init omap_sdp_init_irq(void) omap_gpio_init(); } -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap_sdp_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); board_smc91x_init(); enable_board_wakeup_source(); diff --git a/trunk/arch/arm/mach-omap2/board-am3517evm.c b/trunk/arch/arm/mach-omap2/board-am3517evm.c index b4e6eca0e8a9..415a13d767cc 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517evm.c +++ b/trunk/arch/arm/mach-omap2/board-am3517evm.c @@ -30,8 +30,6 @@ #include #include -#include "mux.h" - /* * Board initialization */ @@ -62,17 +60,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init am3517_evm_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); platform_add_devices(am3517_evm_devices, ARRAY_SIZE(am3517_evm_devices)); diff --git a/trunk/arch/arm/mach-omap2/board-apollon.c b/trunk/arch/arm/mach-omap2/board-apollon.c index fbbd68d69cc8..8a2ce77a02ec 100644 --- a/trunk/arch/arm/mach-omap2/board-apollon.c +++ b/trunk/arch/arm/mach-omap2/board-apollon.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -121,12 +120,6 @@ static void __init apollon_flash_init(void) apollon_flash_resource[0].end = base + SZ_128K - 1; } -static struct smc91x_platdata appolon_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource apollon_smc91x_resources[] = { [0] = { .flags = IORESOURCE_MEM, @@ -141,9 +134,6 @@ static struct resource apollon_smc91x_resources[] = { static struct platform_device apollon_smc91x_device = { .name = "smc91x", .id = -1, - .dev = { - .platform_data = &appolon_smc91x_info, - }, .num_resources = ARRAY_SIZE(apollon_smc91x_resources), .resource = apollon_smc91x_resources, }; diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index 1591aae64500..22c45290db63 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -38,13 +38,13 @@ #include #include +#include #include #include #include #include -#include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" @@ -482,102 +482,8 @@ static void __init cm_t35_map_io(void) omap2_map_common_io(); } -static struct omap_board_mux board_mux[] __initdata = { - /* nCS and IRQ for CM-T35 ethernet */ - OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), - OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - - /* nCS and IRQ for SB-T35 ethernet */ - OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), - OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - - /* PENDOWN GPIO */ - OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), - - /* mUSB */ - OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - - /* MMC 2 */ - OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - - /* McSPI 1 */ - OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - - /* McSPI 4 */ - OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), - - /* McBSP 2 */ - OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - - /* serial ports */ - OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), - OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), - OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - - /* DSS */ - OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - - /* TPS IRQ */ - OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ - OMAP_PIN_INPUT_PULLUP), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - static void __init cm_t35_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); cm_t35_init_i2c(); cm_t35_init_nand(); @@ -586,6 +492,8 @@ static void __init cm_t35_init(void) cm_t35_init_led(); usb_musb_init(); + + omap_cfg_reg(AF26_34XX_SYS_NIRQ); } MACHINE_START(CM_T35, "Compulab CM-T35") diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 44239e3ec02e..fa62e80c13b7 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -27,9 +27,9 @@ #include #include #include +#include #include -#include "mux.h" #include "mmc-twl4030.h" #define IGEP2_SMSC911X_CS 5 @@ -203,17 +203,8 @@ static int __init igep2_i2c_init(void) return 0; } -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init igep2_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); igep2_i2c_init(); omap_serial_init(); usb_musb_init(); diff --git a/trunk/arch/arm/mach-omap2/board-ldp.c b/trunk/arch/arm/mach-omap2/board-ldp.c index 37431738f1c2..c062238fe881 100644 --- a/trunk/arch/arm/mach-omap2/board-ldp.c +++ b/trunk/arch/arm/mach-omap2/board-ldp.c @@ -43,7 +43,6 @@ #include #include -#include "mux.h" #include "mmc-twl4030.h" #define LDP_SMSC911X_CS 1 @@ -375,17 +374,8 @@ static struct platform_device *ldp_devices[] __initdata = { &ldp_gpio_keys_device, }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap_ldp_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); ts_gpio = 54; diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 6ada8029f9a8..41480bd0e58a 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -41,10 +41,10 @@ #include #include #include +#include #include #include -#include "mux.h" #include "mmc-twl4030.h" #define GPMC_CS0_BASE 0x60 @@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { if (system_rev >= 0x20 && system_rev <= 0x34301000) { - omap_mux_init_gpio(23, OMAP_PIN_INPUT); + omap_cfg_reg(AG9_34XX_GPIO23); mmc[0].gpio_wp = 23; } else { - omap_mux_init_gpio(29, OMAP_PIN_INPUT); + omap_cfg_reg(AH8_34XX_GPIO29); } /* gpio + 0 is "mmc0_cd" (input/IRQ) */ mmc[0].gpio_cd = gpio + 0; @@ -422,23 +422,14 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap3_beagle_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); omap_serial_init(); - omap_mux_init_gpio(170, OMAP_PIN_INPUT); + omap_cfg_reg(J25_34XX_GPIO170); gpio_request(170, "DVI_nPD"); /* REVISIT leave DVI powered down until it's needed ... */ gpio_direction_output(170, true); @@ -448,8 +439,8 @@ static void __init omap3_beagle_init(void) omap3beagle_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + omap_cfg_reg(H16_34XX_SDRC_CKE0); + omap_cfg_reg(H17_34XX_SDRC_CKE1); } static void __init omap3_beagle_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index 18913e96e34d..5efc2e9068db 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -38,11 +38,11 @@ #include #include +#include #include #include #include -#include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" @@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { /* gpio + 0 is "mmc0_cd" (input/IRQ) */ - omap_mux_init_gpio(63, OMAP_PIN_INPUT); + omap_cfg_reg(L8_34XX_GPIO63); mmc[0].gpio_cd = gpio + 0; twl4030_mmc_init(mmc); @@ -422,18 +422,9 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap3_evm_init(void) { omap3_evm_get_revision(); - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3_evm_i2c_init(); @@ -449,24 +440,24 @@ static void __init omap3_evm_init(void) #endif if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { /* enable EHCI VBUS using GPIO22 */ - omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AF9_34XX_GPIO22); gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS"); gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0); gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1); /* Select EHCI port on main board */ - omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(U3_34XX_GPIO61); gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port"); gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0); gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0); /* setup EHCI phy reset config */ - omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AH14_34XX_GPIO21); ehci_pdata.reset_gpio_port[1] = 21; } else { /* setup EHCI phy reset on MDC */ - omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); + omap_cfg_reg(AF4_34XX_GPIO135_OUT); ehci_pdata.reset_gpio_port[1] = 135; } usb_musb_init(); diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index 6f6c601eeab7..2db5ba5b3bf7 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -40,8 +40,8 @@ #include #include #include +#include -#include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" @@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = { GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), - GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), - GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), - GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), + GPIO_BUTTON_LOW(111, BTN_A, "a"), + GPIO_BUTTON_LOW(106, BTN_B, "b"), + GPIO_BUTTON_LOW(109, BTN_X, "x"), + GPIO_BUTTON_LOW(101, BTN_Y, "y"), GPIO_BUTTON_LOW(102, BTN_TL, "l"), GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), GPIO_BUTTON_LOW(105, BTN_TR, "r"), @@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void) omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo, ARRAY_SIZE(omap3pandora_i2c_boardinfo)); /* i2c2 pins are not connected */ - omap_register_i2c_bus(3, 100, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); return 0; } @@ -368,8 +368,23 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { } }; +static struct platform_device omap3pandora_lcd_device = { + .name = "pandora_lcd", + .id = -1, +}; + +static struct omap_lcd_config omap3pandora_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_board_config_kernel omap3pandora_config[] __initdata = { + { OMAP_TAG_LCD, &omap3pandora_lcd_config }, +}; + static void __init omap3pandora_init_irq(void) { + omap_board_config = omap3pandora_config; + omap_board_config_size = ARRAY_SIZE(omap3pandora_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); @@ -377,6 +392,7 @@ static void __init omap3pandora_init_irq(void) } static struct platform_device *omap3pandora_devices[] __initdata = { + &omap3pandora_lcd_device, &pandora_leds_gpio, &pandora_keys_gpio, }; @@ -393,17 +409,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap3pandora_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3pandora_i2c_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); @@ -416,8 +423,8 @@ static void __init omap3pandora_init(void) usb_musb_init(); /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + omap_cfg_reg(H16_34XX_SDRC_CKE0); + omap_cfg_reg(H17_34XX_SDRC_CKE1); } static void __init omap3pandora_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c deleted file mode 100644 index c9e5ebb4d91d..000000000000 --- a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c +++ /dev/null @@ -1,572 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/board-omap3touchbook.c - * - * Copyright (C) 2009 Always Innovating - * - * Modified from mach-omap2/board-omap3beagleboard.c - * - * Initial code: Grégoire Gentil, Tim Yamin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "mux.h" -#include "mmc-twl4030.h" - -#include - -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - -#define NAND_BLOCK_SIZE SZ_128K - -#define OMAP3_AC_GPIO 136 -#define OMAP3_TS_GPIO 162 -#define TB_BL_PWM_TIMER 9 -#define TB_KILL_POWER_GPIO 168 - -unsigned long touchbook_revision; - -static struct mtd_partition omap3touchbook_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { - .name = "X-Loader", - .offset = 0, - .size = 4 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot Env", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ - .size = 1 * NAND_BLOCK_SIZE, - }, - { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ - .size = 32 * NAND_BLOCK_SIZE, - }, - { - .name = "File System", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct omap_nand_platform_data omap3touchbook_nand_data = { - .options = NAND_BUSWIDTH_16, - .parts = omap3touchbook_nand_partitions, - .nr_parts = ARRAY_SIZE(omap3touchbook_nand_partitions), - .dma_channel = -1, /* disable DMA in OMAP NAND driver */ - .nand_setup = NULL, - .dev_ready = NULL, -}; - -static struct resource omap3touchbook_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3touchbook_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3touchbook_nand_data, - }, - .num_resources = 1, - .resource = &omap3touchbook_nand_resource, -}; - -#include "sdram-micron-mt46h32m32lf-6.h" - -static struct twl4030_hsmmc_info mmc[] = { - { - .mmc = 1, - .wires = 8, - .gpio_wp = 29, - }, - {} /* Terminator */ -}; - -static struct platform_device omap3_touchbook_lcd_device = { - .name = "omap3touchbook_lcd", - .id = -1, -}; - -static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = { - .ctrl_name = "internal", -}; - -static struct regulator_consumer_supply touchbook_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply touchbook_vsim_supply = { - .supply = "vmmc_aux", -}; - -static struct gpio_led gpio_leds[]; - -static int touchbook_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) -{ - if (system_rev >= 0x20 && system_rev <= 0x34301000) { - omap_mux_init_gpio(23, OMAP_PIN_INPUT); - mmc[0].gpio_wp = 23; - } else { - omap_mux_init_gpio(29, OMAP_PIN_INPUT); - } - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ - mmc[0].gpio_cd = gpio + 0; - twl4030_mmc_init(mmc); - - /* link regulators to MMC adapters */ - touchbook_vmmc1_supply.dev = mmc[0].dev; - touchbook_vsim_supply.dev = mmc[0].dev; - - /* REVISIT: need ehci-omap hooks for external VBUS - * power switch and overcurrent detect - */ - - gpio_request(gpio + 1, "EHCI_nOC"); - gpio_direction_input(gpio + 1); - - /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ - gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - - return 0; -} - -static struct twl4030_gpio_platform_data touchbook_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = true, - .pullups = BIT(1), - .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) - | BIT(15) | BIT(16) | BIT(17), - .setup = touchbook_twl_gpio_setup, -}; - -static struct regulator_consumer_supply touchbook_vdac_supply = { - .supply = "vdac", - .dev = &omap3_touchbook_lcd_device.dev, -}; - -static struct regulator_consumer_supply touchbook_vdvi_supply = { - .supply = "vdvi", - .dev = &omap3_touchbook_lcd_device.dev, -}; - -/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ -static struct regulator_init_data touchbook_vmmc1 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vmmc1_supply, -}; - -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data touchbook_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vsim_supply, -}; - -/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ -static struct regulator_init_data touchbook_vdac = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vdac_supply, -}; - -/* VPLL2 for digital video outputs */ -static struct regulator_init_data touchbook_vpll2 = { - .constraints = { - .name = "VDVI", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &touchbook_vdvi_supply, -}; - -static struct twl4030_usb_data touchbook_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, -}; - -static struct twl4030_codec_audio_data touchbook_audio_data = { - .audio_mclk = 26000000, -}; - -static struct twl4030_codec_data touchbook_codec_data = { - .audio_mclk = 26000000, - .audio = &touchbook_audio_data, -}; - -static struct twl4030_platform_data touchbook_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .usb = &touchbook_usb_data, - .gpio = &touchbook_gpio_data, - .codec = &touchbook_codec_data, - .vmmc1 = &touchbook_vmmc1, - .vsim = &touchbook_vsim, - .vdac = &touchbook_vdac, - .vpll2 = &touchbook_vpll2, -}; - -static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &touchbook_twldata, - }, -}; - -static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("bq27200", 0x55), - }, -}; - -static int __init omap3_touchbook_i2c_init(void) -{ - /* Standard TouchBook bus */ - omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo, - ARRAY_SIZE(touchbook_i2c_boardinfo)); - - /* Additional TouchBook bus */ - omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo, - ARRAY_SIZE(touchBook_i2c_boardinfo)); - - return 0; -} - -static void __init omap3_ads7846_init(void) -{ - if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) { - printk(KERN_ERR "Failed to request GPIO %d for " - "ads7846 pen down IRQ\n", OMAP3_TS_GPIO); - return; - } - - gpio_direction_input(OMAP3_TS_GPIO); - omap_set_gpio_debounce(OMAP3_TS_GPIO, 1); - omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa); -} - -static struct ads7846_platform_data ads7846_config = { - .x_min = 100, - .y_min = 265, - .x_max = 3950, - .y_max = 3750, - .x_plate_ohms = 40, - .pressure_max = 255, - .debounce_max = 10, - .debounce_tol = 5, - .debounce_rep = 1, - .gpio_pendown = OMAP3_TS_GPIO, - .keep_vref_on = 1, -}; - -static struct omap2_mcspi_device_config ads7846_mcspi_config = { - .turbo_mode = 0, - .single_channel = 1, /* 0: slave, 1: master */ -}; - -static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = { - { - .modalias = "ads7846", - .bus_num = 4, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &ads7846_mcspi_config, - .irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO), - .platform_data = &ads7846_config, - } -}; - -static struct gpio_led gpio_leds[] = { - { - .name = "touchbook::usr0", - .default_trigger = "heartbeat", - .gpio = 150, - }, - { - .name = "touchbook::usr1", - .default_trigger = "mmc0", - .gpio = 149, - }, - { - .name = "touchbook::pmu_stat", - .gpio = -EINVAL, /* gets replaced */ - .active_low = true, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - -static struct gpio_keys_button gpio_buttons[] = { - { - .code = BTN_EXTRA, - .gpio = 7, - .desc = "user", - .wakeup = 1, - }, - { - .code = KEY_POWER, - .gpio = 183, - .desc = "power", - .wakeup = 1, - }, -}; - -static struct gpio_keys_platform_data gpio_key_info = { - .buttons = gpio_buttons, - .nbuttons = ARRAY_SIZE(gpio_buttons), -}; - -static struct platform_device keys_gpio = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &gpio_key_info, - }, -}; - -static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { - { OMAP_TAG_LCD, &omap3_touchbook_lcd_config }, -}; - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static void __init omap3_touchbook_init_irq(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = omap3_touchbook_config; - omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); -#ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -#endif - omap_gpio_init(); -} - -static struct platform_device *omap3_touchbook_devices[] __initdata = { - &omap3_touchbook_lcd_device, - &leds_gpio, - &keys_gpio, -}; - -static void __init omap3touchbook_flash_init(void) -{ - u8 cs = 0; - u8 nandcs = GPMC_CS_NUM + 1; - - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - - /* find out the chip-select on which NAND exists */ - while (cs < GPMC_CS_NUM) { - u32 ret = 0; - ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); - - if ((ret & 0xC00) == 0x800) { - printk(KERN_INFO "Found NAND on CS%d\n", cs); - if (nandcs > GPMC_CS_NUM) - nandcs = cs; - } - cs++; - } - - if (nandcs > GPMC_CS_NUM) { - printk(KERN_INFO "NAND: Unable to find configuration " - "in GPMC\n "); - return; - } - - if (nandcs < GPMC_CS_NUM) { - omap3touchbook_nand_data.cs = nandcs; - omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3touchbook_nand_data.gpmc_baseaddr = - (void *) (gpmc_base_add); - - printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3touchbook_nand_device) < 0) - printk(KERN_ERR "Unable to register NAND device\n"); - } -} - -static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - - .phy_reset = true, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = 147, - .reset_gpio_port[2] = -EINVAL -}; - -static void omap3_touchbook_poweroff(void) -{ - int r; - - r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset"); - if (r < 0) { - printk(KERN_ERR "Unable to get kill power GPIO\n"); - return; - } - - gpio_direction_output(TB_KILL_POWER_GPIO, 0); -} - -static void __init early_touchbook_revision(char **p) -{ - if (!*p) - return; - - strict_strtoul(*p, 10, &touchbook_revision); -} -__early_param("tbr=", early_touchbook_revision); - -static void __init omap3_touchbook_init(void) -{ - pm_power_off = omap3_touchbook_poweroff; - - omap3_touchbook_i2c_init(); - platform_add_devices(omap3_touchbook_devices, - ARRAY_SIZE(omap3_touchbook_devices)); - omap_serial_init(); - - omap_mux_init_gpio(170, OMAP_PIN_INPUT); - gpio_request(176, "DVI_nPD"); - /* REVISIT leave DVI powered down until it's needed ... */ - gpio_direction_output(176, true); - - /* Touchscreen and accelerometer */ - spi_register_board_info(omap3_ads7846_spi_board_info, - ARRAY_SIZE(omap3_ads7846_spi_board_info)); - omap3_ads7846_init(); - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3touchbook_flash_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -} - -static void __init omap3_touchbook_map_io(void) -{ - omap2_set_globals_343x(); - omap2_map_common_io(); -} - -MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") - /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_touchbook_map_io, - .init_irq = omap3_touchbook_init_irq, - .init_machine = omap3_touchbook_init, - .timer = &omap_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index 5b78a87217e0..52dfd51a938e 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -44,9 +44,9 @@ #include #include #include +#include #include -#include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "mmc-twl4030.h" @@ -405,17 +405,9 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif static void __init overo_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); overo_i2c_init(); platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); omap_serial_init(); @@ -426,8 +418,8 @@ static void __init overo_init(void) overo_init_smsc911x(); /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + omap_cfg_reg(H16_34XX_SDRC_CKE0); + omap_cfg_reg(H17_34XX_SDRC_CKE1); if ((gpio_request(OVERO_GPIO_W2W_NRESET, "OVERO_GPIO_W2W_NRESET") == 0) && diff --git a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c index bf26ad31f9ba..15ce6514c5fd 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -33,7 +33,6 @@ #include #include -#include "mux.h" #include "mmc-twl4030.h" #define SYSTEM_REV_B_USES_VAUX3 0x1699 @@ -60,7 +59,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .bus_num = 4, .chip_select = 0, .max_speed_hz = 48000000, - .mode = SPI_MODE_3, + .mode = SPI_MODE_2, .controller_data = &wl1251_mcspi_config, .platform_data = &wl1251_pdata, }, @@ -631,9 +630,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = { static void __init board_smc91x_init(void) { - omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_gpio(86, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(164, OMAP_PIN_OUTPUT); + omap_cfg_reg(U8_34XX_GPIO54_DOWN); + omap_cfg_reg(G25_34XX_GPIO86_OUT); + omap_cfg_reg(H19_34XX_GPIO164_OUT); gpmc_smc91x_init(&board_smc91x_data); } diff --git a/trunk/arch/arm/mach-omap2/board-rx51.c b/trunk/arch/arm/mach-omap2/board-rx51.c index 67bb3476b707..1bb1de245917 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51.c +++ b/trunk/arch/arm/mach-omap2/board-rx51.c @@ -23,14 +23,13 @@ #include #include +#include #include #include #include #include #include -#include "mux.h" - struct omap_sdrc_params *rx51_get_sdram_timings(void); static struct omap_lcd_config rx51_lcd_config = { @@ -70,24 +69,15 @@ static void __init rx51_init_irq(void) extern void __init rx51_peripherals_init(void); -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init rx51_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); usb_musb_init(); rx51_peripherals_init(); /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); + omap_cfg_reg(H16_34XX_SDRC_CKE0); + omap_cfg_reg(H17_34XX_SDRC_CKE1); } static void __init rx51_map_io(void) diff --git a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c index 258794db488f..f14baa392760 100755 --- a/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/trunk/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -152,20 +152,14 @@ static struct regulator_init_data zoom_vsim = { static struct twl4030_hsmmc_info mmc[] __initdata = { { - .name = "external", .mmc = 1, .wires = 4, .gpio_wp = -EINVAL, - .power_saving = true, }, { - .name = "internal", .mmc = 2, - .wires = 8, - .gpio_cd = -EINVAL, + .wires = 4, .gpio_wp = -EINVAL, - .nonremovable = true, - .power_saving = true, }, {} /* Terminator */ }; @@ -173,8 +167,11 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { static int zoom_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + /* gpio + 0 is "mmc0_cd" (input/IRQ), + * gpio + 1 is "mmc1_cd" (input/IRQ) + */ mmc[0].gpio_cd = gpio + 0; + mmc[1].gpio_cd = gpio + 1; twl4030_mmc_init(mmc); /* link regulators to MMC adapters ... we "know" the @@ -239,7 +236,6 @@ static struct twl4030_platform_data zoom_twldata = { .gpio = &zoom_gpio_data, .keypad = &zoom_kp_twl4030_data, .codec = &zoom_codec_data, - .vmmc1 = &zoom_vmmc1, .vmmc2 = &zoom_vmmc2, .vsim = &zoom_vsim, diff --git a/trunk/arch/arm/mach-omap2/board-zoom2.c b/trunk/arch/arm/mach-omap2/board-zoom2.c index bb87cf7878ff..d94d047c7dce 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom2.c +++ b/trunk/arch/arm/mach-omap2/board-zoom2.c @@ -23,7 +23,6 @@ #include -#include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" static void __init omap_zoom2_init_irq(void) @@ -69,17 +68,8 @@ static struct twl4030_platform_data zoom2_twldata = { #endif -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap_zoom2_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); zoom_debugboard_init(); } diff --git a/trunk/arch/arm/mach-omap2/board-zoom3.c b/trunk/arch/arm/mach-omap2/board-zoom3.c index a9fe9181b010..8d965a6516c8 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom3.c +++ b/trunk/arch/arm/mach-omap2/board-zoom3.c @@ -21,7 +21,6 @@ #include #include -#include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" static void __init omap_zoom_map_io(void) @@ -43,17 +42,8 @@ static void __init omap_zoom_init_irq(void) omap_gpio_init(); } -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - static void __init omap_zoom_init(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); zoom_debugboard_init(); } diff --git a/trunk/arch/arm/mach-omap2/clock.c b/trunk/arch/arm/mach-omap2/clock.c index 759c72a48f7f..4716206547ac 100644 --- a/trunk/arch/arm/mach-omap2/clock.c +++ b/trunk/arch/arm/mach-omap2/clock.c @@ -70,41 +70,9 @@ u8 cpu_mask; /*------------------------------------------------------------------------- - * OMAP2/3/4 specific clock functions + * OMAP2/3 specific clock functions *-------------------------------------------------------------------------*/ -void omap2_init_dpll_parent(struct clk *clk) -{ - u32 v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return; - - /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* Reparent in case the dpll is in bypass */ - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - clk_reparent(clk, dd->clk_bypass); - } - return; -} - /** * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware * @clk: struct clk * @@ -181,7 +149,6 @@ static int _dpll_test_fint(struct clk *clk, u8 n) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; @@ -199,7 +166,6 @@ void omap2_init_clk_clkdm(struct clk *clk) "clkdm %s\n", clk->name, clk->clkdm_name); } } -#endif /** * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware @@ -281,11 +247,6 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return dd->clk_bypass->rate; - } else if (cpu_is_omap44xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return dd->clk_bypass->rate; } v = __raw_readl(dd->mult_div1_reg); @@ -476,10 +437,8 @@ void omap2_clk_disable(struct clk *clk) _omap2_clk_disable(clk); if (clk->parent) omap2_clk_disable(clk->parent); -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif } } @@ -489,10 +448,8 @@ int omap2_clk_enable(struct clk *clk) int ret = 0; if (clk->usecount++ == 0) { -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_enable(clk->clkdm, clk); -#endif if (clk->parent) { ret = omap2_clk_enable(clk->parent); @@ -511,10 +468,8 @@ int omap2_clk_enable(struct clk *clk) return ret; err: -#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); -#endif clk->usecount--; return ret; } diff --git a/trunk/arch/arm/mach-omap2/clock.h b/trunk/arch/arm/mach-omap2/clock.h index 93c48df3b5b1..43b6bedaafd6 100644 --- a/trunk/arch/arm/mach-omap2/clock.h +++ b/trunk/arch/arm/mach-omap2/clock.h @@ -1,8 +1,8 @@ /* * linux/arch/arm/mach-omap2/clock.h * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2008 Nokia Corporation * * Contacts: * Richard Woodruff @@ -36,17 +36,6 @@ #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP3XXX_EN_DPLL_LOCKED 0x7 -/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ -#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 -#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 -#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 -#define OMAP4XXX_EN_DPLL_LOCKED 0x7 - -/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ -#define DPLL_LOW_POWER_STOP 0x1 -#define DPLL_LOW_POWER_BYPASS 0x5 -#define DPLL_LOCKED 0x7 - int omap2_clk_init(void); int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); @@ -55,14 +44,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap3_dpll_recalc(struct clk *clk); -unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); -int omap3_noncore_dpll_enable(struct clk *clk); -void omap3_noncore_dpll_disable(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); @@ -82,7 +63,6 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); void omap2_clk_prepare_for_reboot(void); int omap2_dflt_clk_enable(struct clk *clk); @@ -92,17 +72,29 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, u8 *idlest_bit); -extern u8 cpu_mask; - extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt; -extern struct clk_functions omap2_clk_functions; -extern struct clk *vclk, *sclk; +extern u8 cpu_mask; -extern const struct clksel_rate gpt_32k_rates[]; -extern const struct clksel_rate gpt_sys_rates[]; -extern const struct clksel_rate gfx_l3_rates[]; +/* clksel_rate data common to 24xx/343x */ +static const struct clksel_rate gpt_32k_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate gpt_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate gfx_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, + { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, + { .div = 0 } +}; #endif diff --git a/trunk/arch/arm/mach-omap2/clock24xx.c b/trunk/arch/arm/mach-omap2/clock24xx.c new file mode 100644 index 000000000000..845b478ebeee --- /dev/null +++ b/trunk/arch/arm/mach-omap2/clock24xx.c @@ -0,0 +1,805 @@ +/* + * linux/arch/arm/mach-omap2/clock.c + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2008 Nokia Corporation + * + * Contacts: + * Richard Woodruff + * Paul Walmsley + * + * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, + * Gordon McNutt and RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include "clock.h" +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "cm.h" +#include "cm-regbits-24xx.h" + +static const struct clkops clkops_oscck; +static const struct clkops clkops_fixed; + +static void omap2430_clk_i2chs_find_idlest(struct clk *clk, + void __iomem **idlest_reg, + u8 *idlest_bit); + +/* 2430 I2CHS has non-standard IDLEST register */ +static const struct clkops clkops_omap2430_i2chs_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap2430_clk_i2chs_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +#include "clock24xx.h" + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_243X RATE_IN_243X +#define CK_242X RATE_IN_242X + +static struct omap_clk omap24xx_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), + CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), + CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), + CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), + CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), + CLK(NULL, "emul_ck", &emul_ck, CK_242X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), + CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), + /* Modem domain clocks */ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ + CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), + CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), + CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), + CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), + CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), + CLK(NULL, "icr_ick", &icr_ick, CK_243X), + CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), + CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), + CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), + CLK(NULL, "eac_ick", &eac_ick, CK_242X), + CLK(NULL, "eac_fck", &eac_fck, CK_242X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), + CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), + CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), + CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), + CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), + CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), + CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), + CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), + CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), + CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), + CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), + CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), + CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), + CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), + CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), + CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), +}; + +/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ +#define EN_APLL_STOPPED 0 +#define EN_APLL_LOCKED 3 + +/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ +#define APLLS_CLKIN_19_2MHZ 0 +#define APLLS_CLKIN_13MHZ 2 +#define APLLS_CLKIN_12MHZ 3 + +/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ + +static struct prcm_config *curr_prcm_set; +static struct clk *vclk; +static struct clk *sclk; + +static void __iomem *prcm_clksrc_ctrl; + +/*------------------------------------------------------------------------- + * Omap24xx specific clock functions + *-------------------------------------------------------------------------*/ + +/** + * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * + * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the + * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function + * passes back the correct CM_IDLEST register address for I2CHS + * modules. No return value. + */ +static void omap2430_clk_i2chs_find_idlest(struct clk *clk, + void __iomem **idlest_reg, + u8 *idlest_bit) +{ + *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); + *idlest_bit = clk->enable_bit; +} + + +/** + * omap2xxx_clk_get_core_rate - return the CORE_CLK rate + * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") + * + * Returns the CORE_CLK rate. CORE_CLK can have one of three rate + * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz + * (the latter is unusual). This currently should be called with + * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * core_ck. + */ +static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) +{ + long long core_clk; + u32 v; + + core_clk = omap2_get_dpll_rate(clk); + + v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (v == CORE_CLK_SRC_32K) + core_clk = 32768; + else + core_clk *= v; + + return core_clk; +} + +static int omap2_enable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(prcm_clksrc_ctrl); + + __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + + return 0; +} + +static void omap2_disable_osc_ck(struct clk *clk) +{ + u32 pcc; + + pcc = __raw_readl(prcm_clksrc_ctrl); + + __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); +} + +static const struct clkops clkops_oscck = { + .enable = &omap2_enable_osc_ck, + .disable = &omap2_disable_osc_ck, +}; + +#ifdef OLD_CK +/* Recalculate SYST_CLK */ +static void omap2_sys_clk_recalc(struct clk * clk) +{ + u32 div = PRCM_CLKSRC_CTRL; + div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ + div >>= clk->rate_offset; + clk->rate = (clk->parent->rate / div); + propagate_rate(clk); +} +#endif /* OLD_CK */ + +/* Enable an APLL if off */ +static int omap2_clk_fixed_enable(struct clk *clk) +{ + u32 cval, apll_mask; + + apll_mask = EN_APLL_LOCKED << clk->enable_bit; + + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + + if ((cval & apll_mask) == apll_mask) + return 0; /* apll already enabled */ + + cval &= ~apll_mask; + cval |= apll_mask; + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + + if (clk == &apll96_ck) + cval = OMAP24XX_ST_96M_APLL; + else if (clk == &apll54_ck) + cval = OMAP24XX_ST_54M_APLL; + + omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, + clk->name); + + /* + * REVISIT: Should we return an error code if omap2_wait_clock_ready() + * fails? + */ + return 0; +} + +/* Stop APLL */ +static void omap2_clk_fixed_disable(struct clk *clk) +{ + u32 cval; + + cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval &= ~(EN_APLL_LOCKED << clk->enable_bit); + cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); +} + +static const struct clkops clkops_fixed = { + .enable = &omap2_clk_fixed_enable, + .disable = &omap2_clk_fixed_disable, +}; + +/* + * Uses the current prcm set to tell if a rate is valid. + * You can go slower, but not faster within a given rate set. + */ +static long omap2_dpllcore_round_rate(unsigned long target_rate) +{ + u32 high, low, core_clk_src; + + core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ + high = curr_prcm_set->dpll_speed * 2; + low = curr_prcm_set->dpll_speed; + } else { /* DPLL clockout x 2 */ + high = curr_prcm_set->dpll_speed; + low = curr_prcm_set->dpll_speed / 2; + } + +#ifdef DOWN_VARIABLE_DPLL + if (target_rate > high) + return high; + else + return target_rate; +#else + if (target_rate > low) + return high; + else + return low; +#endif + +} + +static unsigned long omap2_dpllcore_recalc(struct clk *clk) +{ + return omap2xxx_clk_get_core_rate(clk); +} + +static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) +{ + u32 cur_rate, low, mult, div, valid_rate, done_rate; + u32 bypass = 0; + struct prcm_config tmpset; + const struct dpll_data *dd; + + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); + mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult &= OMAP24XX_CORE_CLK_SRC_MASK; + + if ((rate == (cur_rate / 2)) && (mult == 2)) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); + } else if ((rate == (cur_rate * 2)) && (mult == 1)) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + } else if (rate != cur_rate) { + valid_rate = omap2_dpllcore_round_rate(rate); + if (valid_rate != rate) + return -EINVAL; + + if (mult == 1) + low = curr_prcm_set->dpll_speed; + else + low = curr_prcm_set->dpll_speed / 2; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); + tmpset.cm_clksel1_pll &= ~(dd->mult_mask | + dd->div1_mask); + div = ((curr_prcm_set->xtal_speed / 1000000) - 1); + tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; + if (rate > low) { + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; + mult = ((rate / 2) / 1000000); + done_rate = CORE_CLK_SRC_DPLL_X2; + } else { + tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; + mult = (rate / 1000000); + done_rate = CORE_CLK_SRC_DPLL; + } + tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); + tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); + + /* Worst case */ + tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; + + if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ + bypass = 1; + + /* For omap2xxx_sdrc_init_params() */ + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + + /* Force dll lock mode */ + omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, + bypass); + + /* Errata: ret dll entry state */ + omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); + omap2xxx_sdrc_reprogram(done_rate, 0); + } + + return 0; +} + +/** + * omap2_table_mpu_recalc - just return the MPU speed + * @clk: virt_prcm_set struct clk + * + * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. + */ +static unsigned long omap2_table_mpu_recalc(struct clk *clk) +{ + return curr_prcm_set->mpu_speed; +} + +/* + * Look for a rate equal or less than the target rate given a configuration set. + * + * What's not entirely clear is "which" field represents the key field. + * Some might argue L3-DDR, others ARM, others IVA. This code is simple and + * just uses the ARM rates. + */ +static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) +{ + struct prcm_config *ptr; + long highest_rate; + + if (clk != &virt_prcm_set) + return -EINVAL; + + highest_rate = -EINVAL; + + for (ptr = rate_table; ptr->mpu_speed; ptr++) { + if (!(ptr->flags & cpu_mask)) + continue; + if (ptr->xtal_speed != sys_ck.rate) + continue; + + highest_rate = ptr->mpu_speed; + + /* Can check only after xtal frequency check */ + if (ptr->mpu_speed <= rate) + break; + } + return highest_rate; +} + +/* Sets basic clocks based on the specified rate */ +static int omap2_select_table_rate(struct clk *clk, unsigned long rate) +{ + u32 cur_rate, done_rate, bypass = 0, tmp; + struct prcm_config *prcm; + unsigned long found_speed = 0; + unsigned long flags; + + if (clk != &virt_prcm_set) + return -EINVAL; + + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + + if (prcm->xtal_speed != sys_ck.rate) + continue; + + if (prcm->mpu_speed <= rate) { + found_speed = prcm->mpu_speed; + break; + } + } + + if (!found_speed) { + printk(KERN_INFO "Could not set MPU rate to %luMHz\n", + rate / 1000000); + return -EINVAL; + } + + curr_prcm_set = prcm; + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); + + if (prcm->dpll_speed == cur_rate / 2) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); + } else if (prcm->dpll_speed == cur_rate * 2) { + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + } else if (prcm->dpll_speed != cur_rate) { + local_irq_save(flags); + + if (prcm->dpll_speed == prcm->xtal_speed) + bypass = 1; + + if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == + CORE_CLK_SRC_DPLL_X2) + done_rate = CORE_CLK_SRC_DPLL_X2; + else + done_rate = CORE_CLK_SRC_DPLL; + + /* MPU divider */ + cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + + /* dsp + iva1 div(2420), iva2.1(2430) */ + cm_write_mod_reg(prcm->cm_clksel_dsp, + OMAP24XX_DSP_MOD, CM_CLKSEL); + + cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + + /* Major subsystem dividers */ + tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + CM_CLKSEL1); + + if (cpu_is_omap2430()) + cm_write_mod_reg(prcm->cm_clksel_mdm, + OMAP2430_MDM_MOD, CM_CLKSEL); + + /* x2 to enter omap2xxx_sdrc_init_params() */ + omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); + + omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, + bypass); + + omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); + omap2xxx_sdrc_reprogram(done_rate, 0); + + local_irq_restore(flags); + } + + return 0; +} + +#ifdef CONFIG_CPU_FREQ +/* + * Walk PRCM rate table and fillout cpufreq freq_table + */ +static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; + +void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) +{ + struct prcm_config *prcm; + int i = 0; + + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck.rate) + continue; + + /* don't put bypass rates in table */ + if (prcm->dpll_speed == prcm->xtal_speed) + continue; + + freq_table[i].index = i; + freq_table[i].frequency = prcm->mpu_speed / 1000; + i++; + } + + if (i == 0) { + printk(KERN_WARNING "%s: failed to initialize frequency " + "table\n", __func__); + return; + } + + freq_table[i].index = i; + freq_table[i].frequency = CPUFREQ_TABLE_END; + + *table = &freq_table[0]; +} +#endif + +static struct clk_functions omap2_clk_functions = { + .clk_enable = omap2_clk_enable, + .clk_disable = omap2_clk_disable, + .clk_round_rate = omap2_clk_round_rate, + .clk_set_rate = omap2_clk_set_rate, + .clk_set_parent = omap2_clk_set_parent, + .clk_disable_unused = omap2_clk_disable_unused, +#ifdef CONFIG_CPU_FREQ + .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, +#endif +}; + +static u32 omap2_get_apll_clkin(void) +{ + u32 aplls, srate = 0; + + aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls &= OMAP24XX_APLLS_CLKIN_MASK; + aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; + + if (aplls == APLLS_CLKIN_19_2MHZ) + srate = 19200000; + else if (aplls == APLLS_CLKIN_13MHZ) + srate = 13000000; + else if (aplls == APLLS_CLKIN_12MHZ) + srate = 12000000; + + return srate; +} + +static u32 omap2_get_sysclkdiv(void) +{ + u32 div; + + div = __raw_readl(prcm_clksrc_ctrl); + div &= OMAP_SYSCLKDIV_MASK; + div >>= OMAP_SYSCLKDIV_SHIFT; + + return div; +} + +static unsigned long omap2_osc_clk_recalc(struct clk *clk) +{ + return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); +} + +static unsigned long omap2_sys_clk_recalc(struct clk *clk) +{ + return clk->parent->rate / omap2_get_sysclkdiv(); +} + +/* + * Set clocks for bypass mode for reboot to work. + */ +void omap2_clk_prepare_for_reboot(void) +{ + u32 rate; + + if (vclk == NULL || sclk == NULL) + return; + + rate = clk_get_rate(sclk); + clk_set_rate(vclk, rate); +} + +/* + * Switch the MPU rate if specified on cmdline. + * We cannot do this early until cmdline is parsed. + */ +static int __init omap2_clk_arch_init(void) +{ + if (!mpurate) + return -EINVAL; + + if (clk_set_rate(&virt_prcm_set, mpurate)) + printk(KERN_ERR "Could not find matching MPU rate\n"); + + recalculate_root_clocks(); + + printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " + "%ld.%01ld/%ld/%ld MHz\n", + (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, + (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; + + return 0; +} +arch_initcall(omap2_clk_arch_init); + +int __init omap2_clk_init(void) +{ + struct prcm_config *prcm; + struct omap_clk *c; + u32 clkrate; + + if (cpu_is_omap242x()) { + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_242X; + } else if (cpu_is_omap2430()) { + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_243X; + } + + clk_init(&omap2_clk_functions); + + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + clk_preinit(c->lk.clk); + + osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); + propagate_rate(&osc_ck); + sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); + propagate_rate(&sys_ck); + + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + if (c->cpu & cpu_mask) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + omap2_init_clk_clkdm(c->lk.clk); + } + + /* Check the MPU rate set by bootloader */ + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck.rate) + continue; + if (prcm->dpll_speed <= clkrate) + break; + } + curr_prcm_set = prcm; + + recalculate_root_clocks(); + + printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " + "%ld.%01ld/%ld/%ld MHz\n", + (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, + (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable_init_clocks(); + + /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ + vclk = clk_get(NULL, "virt_prcm_set"); + sclk = clk_get(NULL, "sys_ck"); + + return 0; +} diff --git a/trunk/arch/arm/mach-omap2/clock2xxx_data.c b/trunk/arch/arm/mach-omap2/clock24xx.h similarity index 73% rename from trunk/arch/arm/mach-omap2/clock2xxx_data.c rename to trunk/arch/arm/mach-omap2/clock24xx.h index 97dc7cf7751d..d19cf7a7d8db 100644 --- a/trunk/arch/arm/mach-omap2/clock2xxx_data.c +++ b/trunk/arch/arm/mach-omap2/clock24xx.h @@ -1,8 +1,8 @@ /* - * linux/arch/arm/mach-omap2/clock2xxx_data.c + * linux/arch/arm/mach-omap2/clock24xx.h * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2008 Nokia Corporation * * Contacts: * Richard Woodruff @@ -13,21 +13,600 @@ * published by the Free Software Foundation. */ -#include -#include -#include - -#include +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H #include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" + #include "prm.h" #include "cm.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" +/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ +#ifdef CONFIG_ARCH_OMAP2420 +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL +#else +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL +#endif + +static unsigned long omap2_table_mpu_recalc(struct clk *clk); +static int omap2_select_table_rate(struct clk *clk, unsigned long rate); +static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_osc_clk_recalc(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_dpllcore_recalc(struct clk *clk); +static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); + +/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. + * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP + * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM + */ +struct prcm_config { + unsigned long xtal_speed; /* crystal rate */ + unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ + unsigned long mpu_speed; /* speed of MPU */ + unsigned long cm_clksel_mpu; /* mpu divider */ + unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ + unsigned long cm_clksel_gfx; /* gfx dividers */ + unsigned long cm_clksel1_core; /* major subsystem dividers */ + unsigned long cm_clksel1_pll; /* m,n */ + unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ + unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ + unsigned long base_sdrc_rfr; /* base refresh timing for a set */ + unsigned char flags; +}; + +/* + * The OMAP2 processor can be run at several discrete 'PRCM configurations'. + * These configurations are characterized by voltage and speed for clocks. + * The device is only validated for certain combinations. One way to express + * these combinations is via the 'ratio's' which the clocks operate with + * respect to each other. These ratio sets are for a given voltage/DPLL + * setting. All configurations can be described by a DPLL setting and a ratio + * There are 3 ratio sets for the 2430 and X ratio sets for 2420. + * + * 2430 differs from 2420 in that there are no more phase synchronizers used. + * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs + * 2430 (iva2.1, NOdsp, mdm) + */ + +/* Core fields for cm_clksel, not ratio governed */ +#define RX_CLKSEL_DSS1 (0x10 << 8) +#define RX_CLKSEL_DSS2 (0x0 << 13) +#define RX_CLKSEL_SSI (0x5 << 20) + +/*------------------------------------------------------------------------- + * Voltage/DPLL ratios + *-------------------------------------------------------------------------*/ + +/* 2430 Ratio's, 2430-Ratio Config 1 */ +#define R1_CLKSEL_L3 (4 << 0) +#define R1_CLKSEL_L4 (2 << 5) +#define R1_CLKSEL_USB (4 << 25) +#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + R1_CLKSEL_L4 | R1_CLKSEL_L3 +#define R1_CLKSEL_MPU (2 << 0) +#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU +#define R1_CLKSEL_DSP (2 << 0) +#define R1_CLKSEL_DSP_IF (2 << 5) +#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF +#define R1_CLKSEL_GFX (2 << 0) +#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX +#define R1_CLKSEL_MDM (4 << 0) +#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM + +/* 2430-Ratio Config 2 */ +#define R2_CLKSEL_L3 (6 << 0) +#define R2_CLKSEL_L4 (2 << 5) +#define R2_CLKSEL_USB (2 << 25) +#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + R2_CLKSEL_L4 | R2_CLKSEL_L3 +#define R2_CLKSEL_MPU (2 << 0) +#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU +#define R2_CLKSEL_DSP (2 << 0) +#define R2_CLKSEL_DSP_IF (3 << 5) +#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF +#define R2_CLKSEL_GFX (2 << 0) +#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX +#define R2_CLKSEL_MDM (6 << 0) +#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM + +/* 2430-Ratio Bootm (BYPASS) */ +#define RB_CLKSEL_L3 (1 << 0) +#define RB_CLKSEL_L4 (1 << 5) +#define RB_CLKSEL_USB (1 << 25) +#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + RB_CLKSEL_L4 | RB_CLKSEL_L3 +#define RB_CLKSEL_MPU (1 << 0) +#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU +#define RB_CLKSEL_DSP (1 << 0) +#define RB_CLKSEL_DSP_IF (1 << 5) +#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF +#define RB_CLKSEL_GFX (1 << 0) +#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX +#define RB_CLKSEL_MDM (1 << 0) +#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM + +/* 2420 Ratio Equivalents */ +#define RXX_CLKSEL_VLYNQ (0x12 << 15) +#define RXX_CLKSEL_SSI (0x8 << 20) + +/* 2420-PRCM III 532MHz core */ +#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ +#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ +#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ +#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ + RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ + RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ + RIII_CLKSEL_L3 +#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ +#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU +#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ +#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ +#define RIII_SYNC_DSP (1 << 7) /* Enable sync */ +#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ +#define RIII_SYNC_IVA (1 << 13) /* Enable sync */ +#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ + RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ + RIII_CLKSEL_DSP +#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ +#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX + +/* 2420-PRCM II 600MHz core */ +#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ +#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ +#define RII_CLKSEL_USB (2 << 25) /* 50MHz */ +#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ + RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + RII_CLKSEL_L4 | RII_CLKSEL_L3 +#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ +#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU +#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ +#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ +#define RII_SYNC_DSP (0 << 7) /* Bypass sync */ +#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ +#define RII_SYNC_IVA (0 << 13) /* Bypass sync */ +#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ + RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ + RII_CLKSEL_DSP +#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ +#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX + +/* 2420-PRCM I 660MHz core */ +#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ +#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ +#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ +#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ + RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ + RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ + RI_CLKSEL_L4 | RI_CLKSEL_L3 +#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ +#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU +#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ +#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ +#define RI_SYNC_DSP (1 << 7) /* Activate sync */ +#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ +#define RI_SYNC_IVA (0 << 13) /* Bypass sync */ +#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ + RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ + RI_CLKSEL_DSP +#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ +#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX + +/* 2420-PRCM VII (boot) */ +#define RVII_CLKSEL_L3 (1 << 0) +#define RVII_CLKSEL_L4 (1 << 5) +#define RVII_CLKSEL_DSS1 (1 << 8) +#define RVII_CLKSEL_DSS2 (0 << 13) +#define RVII_CLKSEL_VLYNQ (1 << 15) +#define RVII_CLKSEL_SSI (1 << 20) +#define RVII_CLKSEL_USB (1 << 25) + +#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ + RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ + RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 + +#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ +#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU + +#define RVII_CLKSEL_DSP (1 << 0) +#define RVII_CLKSEL_DSP_IF (1 << 5) +#define RVII_SYNC_DSP (0 << 7) +#define RVII_CLKSEL_IVA (1 << 8) +#define RVII_SYNC_IVA (0 << 13) +#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ + RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP + +#define RVII_CLKSEL_GFX (1 << 0) +#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX + +/*------------------------------------------------------------------------- + * 2430 Target modes: Along with each configuration the CPU has several + * modes which goes along with them. Modes mainly are the addition of + * describe DPLL combinations to go along with a ratio. + *-------------------------------------------------------------------------*/ + +/* Hardware governed */ +#define MX_48M_SRC (0 << 3) +#define MX_54M_SRC (0 << 5) +#define MX_APLLS_CLIKIN_12 (3 << 23) +#define MX_APLLS_CLIKIN_13 (2 << 23) +#define MX_APLLS_CLIKIN_19_2 (0 << 23) + +/* + * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed + * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz + */ +#define M5A_DPLL_MULT_12 (133 << 12) +#define M5A_DPLL_DIV_12 (5 << 8) +#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 +#define M5A_DPLL_MULT_13 (61 << 12) +#define M5A_DPLL_DIV_13 (2 << 8) +#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 +#define M5A_DPLL_MULT_19 (55 << 12) +#define M5A_DPLL_DIV_19 (3 << 8) +#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 +/* #5b (ratio1) target DPLL = 200*2 = 400MHz */ +#define M5B_DPLL_MULT_12 (50 << 12) +#define M5B_DPLL_DIV_12 (2 << 8) +#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 +#define M5B_DPLL_MULT_13 (200 << 12) +#define M5B_DPLL_DIV_13 (12 << 8) + +#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 +#define M5B_DPLL_MULT_19 (125 << 12) +#define M5B_DPLL_DIV_19 (31 << 8) +#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 +/* + * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz + */ +#define M4_DPLL_MULT_12 (133 << 12) +#define M4_DPLL_DIV_12 (3 << 8) +#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + +#define M4_DPLL_MULT_13 (399 << 12) +#define M4_DPLL_DIV_13 (12 << 8) +#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +#define M4_DPLL_MULT_19 (145 << 12) +#define M4_DPLL_DIV_19 (6 << 8) +#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 + +/* + * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz + */ +#define M3_DPLL_MULT_12 (55 << 12) +#define M3_DPLL_DIV_12 (1 << 8) +#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 +#define M3_DPLL_MULT_13 (76 << 12) +#define M3_DPLL_DIV_13 (2 << 8) +#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 +#define M3_DPLL_MULT_19 (17 << 12) +#define M3_DPLL_DIV_19 (0 << 8) +#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 + +/* + * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz + */ +#define M2_DPLL_MULT_12 (55 << 12) +#define M2_DPLL_DIV_12 (1 << 8) +#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + +/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, + * relock time issue */ +/* Core frequency changed from 330/165 to 329/164 MHz*/ +#define M2_DPLL_MULT_13 (76 << 12) +#define M2_DPLL_DIV_13 (2 << 8) +#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +#define M2_DPLL_MULT_19 (17 << 12) +#define M2_DPLL_DIV_19 (0 << 8) +#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ + M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ + MX_APLLS_CLIKIN_19_2 + +/* boot (boot) */ +#define MB_DPLL_MULT (1 << 12) +#define MB_DPLL_DIV (0 << 8) +#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ + MB_DPLL_MULT | MX_APLLS_CLIKIN_12 + +#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ + MB_DPLL_MULT | MX_APLLS_CLIKIN_13 + +#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ + MB_DPLL_MULT | MX_APLLS_CLIKIN_19 + +/* + * 2430 - chassis (sedna) + * 165 (ratio1) same as above #2 + * 150 (ratio1) + * 133 (ratio2) same as above #4 + * 110 (ratio2) same as above #3 + * 104 (ratio2) + * boot (boot) + */ + +/* PRCM I target DPLL = 2*330MHz = 660MHz */ +#define MI_DPLL_MULT_12 (55 << 12) +#define MI_DPLL_DIV_12 (1 << 8) +#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 + +/* + * 2420 Equivalent - mode registers + * PRCM II , target DPLL = 2*300MHz = 600MHz + */ +#define MII_DPLL_MULT_12 (50 << 12) +#define MII_DPLL_DIV_12 (1 << 8) +#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 +#define MII_DPLL_MULT_13 (300 << 12) +#define MII_DPLL_DIV_13 (12 << 8) +#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +/* PRCM III target DPLL = 2*266 = 532MHz*/ +#define MIII_DPLL_MULT_12 (133 << 12) +#define MIII_DPLL_DIV_12 (5 << 8) +#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ + MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ + MX_APLLS_CLIKIN_12 +#define MIII_DPLL_MULT_13 (266 << 12) +#define MIII_DPLL_DIV_13 (12 << 8) +#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ + MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ + MX_APLLS_CLIKIN_13 + +/* PRCM VII (boot bypass) */ +#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL +#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL + +/* High and low operation value */ +#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) +#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) + +/* MPU speed defines */ +#define S12M 12000000 +#define S13M 13000000 +#define S19M 19200000 +#define S26M 26000000 +#define S100M 100000000 +#define S133M 133000000 +#define S150M 150000000 +#define S164M 164000000 +#define S165M 165000000 +#define S199M 199000000 +#define S200M 200000000 +#define S266M 266000000 +#define S300M 300000000 +#define S329M 329000000 +#define S330M 330000000 +#define S399M 399000000 +#define S400M 400000000 +#define S532M 532000000 +#define S600M 600000000 +#define S658M 658000000 +#define S660M 660000000 +#define S798M 798000000 + +/*------------------------------------------------------------------------- + * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. + * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, + * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, + * CM_CLKSEL2_PLL, CM_CLKSEL_MDM + * + * Filling in table based on H4 boards and 2430-SDPs variants available. + * There are quite a few more rates combinations which could be defined. + * + * When multiple values are defined the start up will try and choose the + * fastest one. If a 'fast' value is defined, then automatically, the /2 + * one should be included as it can be used. Generally having more that + * one fast set does not make sense, as static timings need to be changed + * to change the set. The exception is the bypass setting which is + * availble for low power bypass. + * + * Note: This table needs to be sorted, fastest to slowest. + *-------------------------------------------------------------------------*/ +static struct prcm_config rate_table[] = { + /* PRCM I - FAST */ + {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ + RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, + RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, + RATE_IN_242X}, + + /* PRCM II - FAST */ + {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ + RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, + RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, + RATE_IN_242X}, + + {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ + RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, + RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, + RATE_IN_242X}, + + /* PRCM III - FAST */ + {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ + RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, + RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, + RATE_IN_242X}, + + {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ + RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, + RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, + RATE_IN_242X}, + + /* PRCM II - SLOW */ + {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ + RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, + RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, + RATE_IN_242X}, + + {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ + RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, + RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, + RATE_IN_242X}, + + /* PRCM III - SLOW */ + {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ + RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, + RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, + RATE_IN_242X}, + + {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ + RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, + RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, + RATE_IN_242X}, + + /* PRCM-VII (boot-bypass) */ + {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ + RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, + RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, + RATE_IN_242X}, + + /* PRCM-VII (boot-bypass) */ + {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ + RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, + RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, + RATE_IN_242X}, + + /* PRCM #4 - ratio2 (ES2.1) - FAST */ + {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ + R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, + R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #2 - ratio1 (ES2) - FAST */ + {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_165MHz, + RATE_IN_243X}, + + /* PRCM #5a - ratio1 - FAST */ + {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #5b - ratio1 - FAST */ + {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_100MHz, + RATE_IN_243X}, + + /* PRCM #4 - ratio1 (ES2.1) - SLOW */ + {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ + R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, + R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #2 - ratio1 (ES2) - SLOW */ + {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_165MHz, + RATE_IN_243X}, + + /* PRCM #5a - ratio1 - SLOW */ + {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_133MHz, + RATE_IN_243X}, + + /* PRCM #5b - ratio1 - SLOW*/ + {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ + R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, + R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_100MHz, + RATE_IN_243X}, + + /* PRCM-boot/bypass */ + {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ + RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, + RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, + MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_BYPASS, + RATE_IN_243X}, + + /* PRCM-boot/bypass */ + {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ + RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, + RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, + MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, + SDRC_RFR_CTRL_BYPASS, + RATE_IN_243X}, + + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; + /*------------------------------------------------------------------------- * 24xx clock tree. * @@ -129,7 +708,7 @@ static struct clk dpll_ck = { static struct clk apll96_ck = { .name = "apll96_ck", - .ops = &clkops_apll96, + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 96000000, .flags = RATE_FIXED | ENABLE_ON_INIT, @@ -140,7 +719,7 @@ static struct clk apll96_ck = { static struct clk apll54_ck = { .name = "apll54_ck", - .ops = &clkops_apll54, + .ops = &clkops_fixed, .parent = &sys_ck, .rate = 54000000, .flags = RATE_FIXED | ENABLE_ON_INIT, @@ -2074,236 +2653,5 @@ static struct clk virt_prcm_set = { .round_rate = &omap2_round_to_table_rate, }; - -/* - * clkdev integration - */ - -static struct omap_clk omap24xx_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), - CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), - CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), - CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), - CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), - CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), - CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), - CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), - CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), - CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), - CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), - CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), - CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), - CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), - CLK(NULL, "emul_ck", &emul_ck, CK_242X), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), - CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), - CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), - CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), - CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), - /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), - /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), - CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), - CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), - CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), - CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), - CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), - CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), - CLK(NULL, "icr_ick", &icr_ick, CK_243X), - CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), - CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), - CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), - CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), - CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), - CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), - CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), - CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), - CLK(NULL, "eac_ick", &eac_ick, CK_242X), - CLK(NULL, "eac_fck", &eac_fck, CK_242X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), - CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), - CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), - CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), - CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), - CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), - CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), - CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), - CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), - CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), - CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), - CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), - CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), - CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), - CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), - CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), - CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), - CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), - CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), - CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), - CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), -}; - -/* - * init code - */ - -int __init omap2_clk_init(void) -{ - const struct prcm_config *prcm; - struct omap_clk *c; - u32 clkrate; - u16 cpu_clkflg; - - if (cpu_is_omap242x()) { - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; - cpu_mask = RATE_IN_242X; - cpu_clkflg = CK_242X; - rate_table = omap2420_rate_table; - } else if (cpu_is_omap2430()) { - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; - cpu_mask = RATE_IN_243X; - cpu_clkflg = CK_243X; - rate_table = omap2430_rate_table; - } - - clk_init(&omap2_clk_functions); - - for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - clk_preinit(c->lk.clk); - - osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); - propagate_rate(&osc_ck); - sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); - propagate_rate(&sys_ck); - - for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* Check the MPU rate set by bootloader */ - clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - if (prcm->dpll_speed <= clkrate) - break; - } - curr_prcm_set = prcm; - - recalculate_root_clocks(); - - printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, - (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ - vclk = clk_get(NULL, "virt_prcm_set"); - sclk = clk_get(NULL, "sys_ck"); - dclk = clk_get(NULL, "dpll_ck"); - - return 0; -} +#endif diff --git a/trunk/arch/arm/mach-omap2/clock2xxx.c b/trunk/arch/arm/mach-omap2/clock2xxx.c deleted file mode 100644 index d0e3fb7f9298..000000000000 --- a/trunk/arch/arm/mach-omap2/clock2xxx.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/clock.c - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2008 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" - - -/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ -#define EN_APLL_STOPPED 0 -#define EN_APLL_LOCKED 3 - -/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ -#define APLLS_CLKIN_19_2MHZ 0 -#define APLLS_CLKIN_13MHZ 2 -#define APLLS_CLKIN_12MHZ 3 - -/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ - -const struct prcm_config *curr_prcm_set; -const struct prcm_config *rate_table; - -struct clk *vclk, *sclk, *dclk; - -void __iomem *prcm_clksrc_ctrl; - -/*------------------------------------------------------------------------- - * Omap24xx specific clock functions - *-------------------------------------------------------------------------*/ - -/** - * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * - * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the - * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function - * passes back the correct CM_IDLEST register address for I2CHS - * modules. No return value. - */ -static void omap2430_clk_i2chs_find_idlest(struct clk *clk, - void __iomem **idlest_reg, - u8 *idlest_bit) -{ - *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); - *idlest_bit = clk->enable_bit; -} - -/* 2430 I2CHS has non-standard IDLEST register */ -const struct clkops clkops_omap2430_i2chs_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap2xxx_clk_get_core_rate - return the CORE_CLK rate - * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") - * - * Returns the CORE_CLK rate. CORE_CLK can have one of three rate - * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz - * (the latter is unusual). This currently should be called with - * struct clk *dpll_ck, which is a composite clock of dpll_ck and - * core_ck. - */ -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) -{ - long long core_clk; - u32 v; - - core_clk = omap2_get_dpll_rate(clk); - - v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - v &= OMAP24XX_CORE_CLK_SRC_MASK; - - if (v == CORE_CLK_SRC_32K) - core_clk = 32768; - else - core_clk *= v; - - return core_clk; -} - -static int omap2_enable_osc_ck(struct clk *clk) -{ - u32 pcc; - - pcc = __raw_readl(prcm_clksrc_ctrl); - - __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); - - return 0; -} - -static void omap2_disable_osc_ck(struct clk *clk) -{ - u32 pcc; - - pcc = __raw_readl(prcm_clksrc_ctrl); - - __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); -} - -const struct clkops clkops_oscck = { - .enable = omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, -}; - -#ifdef OLD_CK -/* Recalculate SYST_CLK */ -static void omap2_sys_clk_recalc(struct clk *clk) -{ - u32 div = PRCM_CLKSRC_CTRL; - div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ - div >>= clk->rate_offset; - clk->rate = (clk->parent->rate / div); - propagate_rate(clk); -} -#endif /* OLD_CK */ - -/* Enable an APLL if off */ -static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) -{ - u32 cval, apll_mask; - - apll_mask = EN_APLL_LOCKED << clk->enable_bit; - - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); - - if ((cval & apll_mask) == apll_mask) - return 0; /* apll already enabled */ - - cval &= ~apll_mask; - cval |= apll_mask; - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); - - omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask, - clk->name); - - /* - * REVISIT: Should we return an error code if omap2_wait_clock_ready() - * fails? - */ - return 0; -} - -static int omap2_clk_apll96_enable(struct clk *clk) -{ - return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); -} - -static int omap2_clk_apll54_enable(struct clk *clk) -{ - return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); -} - -/* Stop APLL */ -static void omap2_clk_apll_disable(struct clk *clk) -{ - u32 cval; - - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); - cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); -} - -const struct clkops clkops_apll96 = { - .enable = omap2_clk_apll96_enable, - .disable = omap2_clk_apll_disable, -}; - -const struct clkops clkops_apll54 = { - .enable = omap2_clk_apll54_enable, - .disable = omap2_clk_apll_disable, -}; - -/* - * Uses the current prcm set to tell if a rate is valid. - * You can go slower, but not faster within a given rate set. - */ -long omap2_dpllcore_round_rate(unsigned long target_rate) -{ - u32 high, low, core_clk_src; - - core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; - - if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ - high = curr_prcm_set->dpll_speed * 2; - low = curr_prcm_set->dpll_speed; - } else { /* DPLL clockout x 2 */ - high = curr_prcm_set->dpll_speed; - low = curr_prcm_set->dpll_speed / 2; - } - -#ifdef DOWN_VARIABLE_DPLL - if (target_rate > high) - return high; - else - return target_rate; -#else - if (target_rate > low) - return high; - else - return low; -#endif - -} - -unsigned long omap2_dpllcore_recalc(struct clk *clk) -{ - return omap2xxx_clk_get_core_rate(clk); -} - -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) -{ - u32 cur_rate, low, mult, div, valid_rate, done_rate; - u32 bypass = 0; - struct prcm_config tmpset; - const struct dpll_data *dd; - - cur_rate = omap2xxx_clk_get_core_rate(dclk); - mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - mult &= OMAP24XX_CORE_CLK_SRC_MASK; - - if ((rate == (cur_rate / 2)) && (mult == 2)) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); - } else if ((rate == (cur_rate * 2)) && (mult == 1)) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - } else if (rate != cur_rate) { - valid_rate = omap2_dpllcore_round_rate(rate); - if (valid_rate != rate) - return -EINVAL; - - if (mult == 1) - low = curr_prcm_set->dpll_speed; - else - low = curr_prcm_set->dpll_speed / 2; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); - tmpset.cm_clksel1_pll &= ~(dd->mult_mask | - dd->div1_mask); - div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; - if (rate > low) { - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; - mult = ((rate / 2) / 1000000); - done_rate = CORE_CLK_SRC_DPLL_X2; - } else { - tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; - mult = (rate / 1000000); - done_rate = CORE_CLK_SRC_DPLL; - } - tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); - tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); - - /* Worst case */ - tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; - - if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ - bypass = 1; - - /* For omap2xxx_sdrc_init_params() */ - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - - /* Force dll lock mode */ - omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, - bypass); - - /* Errata: ret dll entry state */ - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); - omap2xxx_sdrc_reprogram(done_rate, 0); - } - - return 0; -} - -/** - * omap2_table_mpu_recalc - just return the MPU speed - * @clk: virt_prcm_set struct clk - * - * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. - */ -unsigned long omap2_table_mpu_recalc(struct clk *clk) -{ - return curr_prcm_set->mpu_speed; -} - -/* - * Look for a rate equal or less than the target rate given a configuration set. - * - * What's not entirely clear is "which" field represents the key field. - * Some might argue L3-DDR, others ARM, others IVA. This code is simple and - * just uses the ARM rates. - */ -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) -{ - const struct prcm_config *ptr; - long highest_rate; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); - - highest_rate = -EINVAL; - - for (ptr = rate_table; ptr->mpu_speed; ptr++) { - if (!(ptr->flags & cpu_mask)) - continue; - if (ptr->xtal_speed != sys_ck_rate) - continue; - - highest_rate = ptr->mpu_speed; - - /* Can check only after xtal frequency check */ - if (ptr->mpu_speed <= rate) - break; - } - return highest_rate; -} - -/* Sets basic clocks based on the specified rate */ -int omap2_select_table_rate(struct clk *clk, unsigned long rate) -{ - u32 cur_rate, done_rate, bypass = 0, tmp; - const struct prcm_config *prcm; - unsigned long found_speed = 0; - unsigned long flags; - long sys_ck_rate; - - sys_ck_rate = clk_get_rate(sclk); - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - - if (prcm->xtal_speed != sys_ck_rate) - continue; - - if (prcm->mpu_speed <= rate) { - found_speed = prcm->mpu_speed; - break; - } - } - - if (!found_speed) { - printk(KERN_INFO "Could not set MPU rate to %luMHz\n", - rate / 1000000); - return -EINVAL; - } - - curr_prcm_set = prcm; - cur_rate = omap2xxx_clk_get_core_rate(dclk); - - if (prcm->dpll_speed == cur_rate / 2) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); - } else if (prcm->dpll_speed == cur_rate * 2) { - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - } else if (prcm->dpll_speed != cur_rate) { - local_irq_save(flags); - - if (prcm->dpll_speed == prcm->xtal_speed) - bypass = 1; - - if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == - CORE_CLK_SRC_DPLL_X2) - done_rate = CORE_CLK_SRC_DPLL_X2; - else - done_rate = CORE_CLK_SRC_DPLL; - - /* MPU divider */ - cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); - - /* dsp + iva1 div(2420), iva2.1(2430) */ - cm_write_mod_reg(prcm->cm_clksel_dsp, - OMAP24XX_DSP_MOD, CM_CLKSEL); - - cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); - - /* Major subsystem dividers */ - tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, - CM_CLKSEL1); - - if (cpu_is_omap2430()) - cm_write_mod_reg(prcm->cm_clksel_mdm, - OMAP2430_MDM_MOD, CM_CLKSEL); - - /* x2 to enter omap2xxx_sdrc_init_params() */ - omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); - - omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, - bypass); - - omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); - omap2xxx_sdrc_reprogram(done_rate, 0); - - local_irq_restore(flags); - } - - return 0; -} - -#ifdef CONFIG_CPU_FREQ -/* - * Walk PRCM rate table and fillout cpufreq freq_table - */ -static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; - -void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - struct prcm_config *prcm; - int i = 0; - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - freq_table[i].index = i; - freq_table[i].frequency = prcm->mpu_speed / 1000; - i++; - } - - if (i == 0) { - printk(KERN_WARNING "%s: failed to initialize frequency " - "table\n", __func__); - return; - } - - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - - *table = &freq_table[0]; -} -#endif - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -#ifdef CONFIG_CPU_FREQ - .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, -#endif -}; - -static u32 omap2_get_apll_clkin(void) -{ - u32 aplls, srate = 0; - - aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); - aplls &= OMAP24XX_APLLS_CLKIN_MASK; - aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; - - if (aplls == APLLS_CLKIN_19_2MHZ) - srate = 19200000; - else if (aplls == APLLS_CLKIN_13MHZ) - srate = 13000000; - else if (aplls == APLLS_CLKIN_12MHZ) - srate = 12000000; - - return srate; -} - -static u32 omap2_get_sysclkdiv(void) -{ - u32 div; - - div = __raw_readl(prcm_clksrc_ctrl); - div &= OMAP_SYSCLKDIV_MASK; - div >>= OMAP_SYSCLKDIV_SHIFT; - - return div; -} - -unsigned long omap2_osc_clk_recalc(struct clk *clk) -{ - return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); -} - -unsigned long omap2_sys_clk_recalc(struct clk *clk) -{ - return clk->parent->rate / omap2_get_sysclkdiv(); -} - -/* - * Set clocks for bypass mode for reboot to work. - */ -void omap2_clk_prepare_for_reboot(void) -{ - u32 rate; - - if (vclk == NULL || sclk == NULL) - return; - - rate = clk_get_rate(sclk); - clk_set_rate(vclk, rate); -} - -/* - * Switch the MPU rate if specified on cmdline. - * We cannot do this early until cmdline is parsed. - */ -static int __init omap2_clk_arch_init(void) -{ - struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; - unsigned long sys_ck_rate; - - if (!mpurate) - return -EINVAL; - - virt_prcm_set = clk_get(NULL, "virt_prcm_set"); - sys_ck = clk_get(NULL, "sys_ck"); - dpll_ck = clk_get(NULL, "dpll_ck"); - mpu_ck = clk_get(NULL, "mpu_ck"); - - if (clk_set_rate(virt_prcm_set, mpurate)) - printk(KERN_ERR "Could not find matching MPU rate\n"); - - recalculate_root_clocks(); - - sys_ck_rate = clk_get_rate(sys_ck); - - pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10, - (clk_get_rate(dpll_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); - - return 0; -} -arch_initcall(omap2_clk_arch_init); - - diff --git a/trunk/arch/arm/mach-omap2/clock2xxx.h b/trunk/arch/arm/mach-omap2/clock2xxx.h deleted file mode 100644 index e35efde4bd80..000000000000 --- a/trunk/arch/arm/mach-omap2/clock2xxx.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * OMAP2 clock function prototypes and macros - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H - -unsigned long omap2_table_mpu_recalc(struct clk *clk); -int omap2_select_table_rate(struct clk *clk, unsigned long rate); -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -unsigned long omap2_sys_clk_recalc(struct clk *clk); -unsigned long omap2_osc_clk_recalc(struct clk *clk); -unsigned long omap2_sys_clk_recalc(struct clk *clk); -unsigned long omap2_dpllcore_recalc(struct clk *clk); -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); - -/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */ -#ifdef CONFIG_ARCH_OMAP2420 -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR -#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL -#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL -#else -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR -#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL -#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL -#endif - -extern void __iomem *prcm_clksrc_ctrl; - -extern struct clk *dclk; - -extern const struct clkops clkops_omap2430_i2chs_wait; -extern const struct clkops clkops_oscck; -extern const struct clkops clkops_apll96; -extern const struct clkops clkops_apll54; - -#endif diff --git a/trunk/arch/arm/mach-omap2/clock34xx.c b/trunk/arch/arm/mach-omap2/clock34xx.c index ded32364f32b..ecbb5cd8eec8 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.c +++ b/trunk/arch/arm/mach-omap2/clock34xx.c @@ -30,21 +30,314 @@ #include #include #include -#include #include #include #include #include "clock.h" -#include "clock34xx.h" -#include "sdrc.h" #include "prm.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "cm-regbits-34xx.h" +static const struct clkops clkops_noncore_dpll_ops; + +static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, + void __iomem **idlest_reg, + u8 *idlest_bit); +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, + void __iomem **idlest_reg, + u8 *idlest_bit); +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, + void __iomem **idlest_reg, + u8 *idlest_bit); + +static const struct clkops clkops_omap3430es2_ssi_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +static const struct clkops clkops_omap3430es2_hsotgusb_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +static const struct clkops clkops_omap3430es2_dss_usbhost_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +#include "clock34xx.h" + +struct omap_clk { + u32 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +#define CK_343X (1 << 0) +#define CK_3430ES1 (1 << 1) +#define CK_3430ES2 (1 << 2) + +static struct omap_clk omap34xx_clks[] = { + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), + CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), + CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), + CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), + CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), + CLK(NULL, "sys_ck", &sys_ck, CK_343X), + CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), + CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), + CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), + CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), + CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), + CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), + CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), + CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), + CLK(NULL, "core_ck", &core_ck, CK_343X), + CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), + CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), + CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), + CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), + CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), + CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), + CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), + CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), + CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), + CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), + CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), + CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), + CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), + CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), + CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), + CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), + CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), + CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), + CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), + CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), + CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), + CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), + CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), + CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), + CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), + CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), + CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), + CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), + CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), + CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), + CLK(NULL, "arm_fck", &arm_fck, CK_343X), + CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), + CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), + CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), + CLK(NULL, "l3_ick", &l3_ick, CK_343X), + CLK(NULL, "l4_ick", &l4_ick, CK_343X), + CLK(NULL, "rm_ick", &rm_ick, CK_343X), + CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), + CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), + CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), + CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), + CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), + CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), + CLK(NULL, "modem_fck", &modem_fck, CK_343X), + CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), + CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), + CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), + CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), + CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), + CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), + CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), + CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), + CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), + CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), + CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), + CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), + CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), + CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), + CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), + CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), + CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), + CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), + CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), + CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), + CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), + CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), + CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), + CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), + CLK(NULL, "pka_ick", &pka_ick, CK_343X), + CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), + CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), + CLK(NULL, "icr_ick", &icr_ick, CK_343X), + CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), + CLK(NULL, "des2_ick", &des2_ick, CK_343X), + CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), + CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), + CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), + CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), + CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), + CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), + CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), + CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), + CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), + CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), + CLK("omap_rng", "ick", &rng_ick, CK_343X), + CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), + CLK(NULL, "des1_ick", &des1_ick, CK_343X), + CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), + CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), + CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), + CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), + CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), + CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), + CLK(NULL, "cam_ick", &cam_ick, CK_343X), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), + CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), + CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), + CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), + CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), + CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), + CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), + CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), + CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), + CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), + CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), + CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), + CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), + CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), + CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), + CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), + CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), + CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), + CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), + CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), + CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), + CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), + CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), + CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), + CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), + CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), + CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), + CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), + CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), + CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), + CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), + CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), +}; + +/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ +#define DPLL_AUTOIDLE_DISABLE 0x0 +#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 + +#define MAX_DPLL_WAIT_TRIES 1000000 + +#define MIN_SDRC_DLL_LOCK_FREQ 83000000 + #define CYCLES_PER_MHZ 1000000 +/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ +#define SDRC_MPURATE_SCALE 8 + +/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ +#define SDRC_MPURATE_BASE_SHIFT 9 + +/* + * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at + * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize + */ +#define SDRC_MPURATE_LOOPS 96 + /* * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks * that are sourced by DPLL5, and both of these require this clock @@ -52,9 +345,6 @@ */ #define DPLL5_FREQ_FOR_USBHOST 120000000 -/* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; - /** * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI * @clk: struct clk * being enabled @@ -76,13 +366,6 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; } -const struct clkops clkops_omap3430es2_ssi_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - /** * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST * @clk: struct clk * being enabled @@ -108,13 +391,6 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; } -const struct clkops clkops_omap3430es2_dss_usbhost_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - /** * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB * @clk: struct clk * being enabled @@ -136,19 +412,395 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; } -const struct clkops clkops_omap3430es2_hsotgusb_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; +/** + * omap3_dpll_recalc - recalculate DPLL rate + * @clk: DPLL struct clk + * + * Recalculate and propagate the DPLL rate. + */ +static unsigned long omap3_dpll_recalc(struct clk *clk) +{ + return omap2_get_dpll_rate(clk); +} -const struct clkops clkops_noncore_dpll_ops = { - .enable = omap3_noncore_dpll_enable, - .disable = omap3_noncore_dpll_disable, -}; +/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ +static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +{ + const struct dpll_data *dd; + u32 v; + + dd = clk->dpll_data; + + v = __raw_readl(dd->control_reg); + v &= ~dd->enable_mask; + v |= clken_bits << __ffs(dd->enable_mask); + __raw_writel(v, dd->control_reg); +} + +/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ +static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +{ + const struct dpll_data *dd; + int i = 0; + int ret = -EINVAL; + + dd = clk->dpll_data; + + state <<= __ffs(dd->idlest_mask); + + while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && + i < MAX_DPLL_WAIT_TRIES) { + i++; + udelay(1); + } + + if (i == MAX_DPLL_WAIT_TRIES) { + printk(KERN_ERR "clock: %s failed transition to '%s'\n", + clk->name, (state) ? "locked" : "bypassed"); + } else { + pr_debug("clock: %s transition to '%s' in %d loops\n", + clk->name, (state) ? "locked" : "bypassed", i); + + ret = 0; + } + + return ret; +} + +/* From 3430 TRM ES2 4.7.6.2 */ +static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +{ + unsigned long fint; + u16 f = 0; + + fint = clk->dpll_data->clk_ref->rate / n; + + pr_debug("clock: fint is %lu\n", fint); + + if (fint >= 750000 && fint <= 1000000) + f = 0x3; + else if (fint > 1000000 && fint <= 1250000) + f = 0x4; + else if (fint > 1250000 && fint <= 1500000) + f = 0x5; + else if (fint > 1500000 && fint <= 1750000) + f = 0x6; + else if (fint > 1750000 && fint <= 2100000) + f = 0x7; + else if (fint > 7500000 && fint <= 10000000) + f = 0xB; + else if (fint > 10000000 && fint <= 12500000) + f = 0xC; + else if (fint > 12500000 && fint <= 15000000) + f = 0xD; + else if (fint > 15000000 && fint <= 17500000) + f = 0xE; + else if (fint > 17500000 && fint <= 21000000) + f = 0xF; + else + pr_debug("clock: unknown freqsel setting for %d\n", n); + + return f; +} + +/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ + +/* + * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report + * readiness before returning. Will save and restore the DPLL's + * autoidle state across the enable, per the CDP code. If the DPLL + * locked successfully, return 0; if the DPLL did not lock in the time + * allotted, or DPLL3 was passed in, return -EINVAL. + */ +static int _omap3_noncore_dpll_lock(struct clk *clk) +{ + u8 ai; + int r; + + if (clk == &dpll3_ck) + return -EINVAL; + + pr_debug("clock: locking DPLL %s\n", clk->name); + + ai = omap3_dpll_autoidle_read(clk); + + omap3_dpll_deny_idle(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOCKED); + + r = _omap3_wait_dpll_status(clk, 1); + + if (ai) + omap3_dpll_allow_idle(clk); + + return r; +} + +/* + * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enter low-power bypass mode. In + * bypass mode, the DPLL's rate is set equal to its parent clock's + * rate. Waits for the DPLL to report readiness before returning. + * Will save and restore the DPLL's autoidle state across the enable, + * per the CDP code. If the DPLL entered bypass mode successfully, + * return 0; if the DPLL did not enter bypass in the time allotted, or + * DPLL3 was passed in, or the DPLL does not support low-power bypass, + * return -EINVAL. + */ +static int _omap3_noncore_dpll_bypass(struct clk *clk) +{ + int r; + u8 ai; + + if (clk == &dpll3_ck) + return -EINVAL; + + if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) + return -EINVAL; + + pr_debug("clock: configuring DPLL %s for low-power bypass\n", + clk->name); + + ai = omap3_dpll_autoidle_read(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); + + r = _omap3_wait_dpll_status(clk, 0); + + if (ai) + omap3_dpll_allow_idle(clk); + else + omap3_dpll_deny_idle(clk); + + return r; +} + +/* + * _omap3_noncore_dpll_stop - instruct a DPLL to stop + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enter low-power stop. Will save and + * restore the DPLL's autoidle state across the stop, per the CDP + * code. If DPLL3 was passed in, or the DPLL does not support + * low-power stop, return -EINVAL; otherwise, return 0. + */ +static int _omap3_noncore_dpll_stop(struct clk *clk) +{ + u8 ai; + + if (clk == &dpll3_ck) + return -EINVAL; + + if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) + return -EINVAL; + + pr_debug("clock: stopping DPLL %s\n", clk->name); + + ai = omap3_dpll_autoidle_read(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); + + if (ai) + omap3_dpll_allow_idle(clk); + else + omap3_dpll_deny_idle(clk); + + return 0; +} + +/** + * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. + * The choice of modes depends on the DPLL's programmed rate: if it is + * the same as the DPLL's parent clock, it will enter bypass; + * otherwise, it will enter lock. This code will wait for the DPLL to + * indicate readiness before returning, unless the DPLL takes too long + * to enter the target state. Intended to be used as the struct clk's + * enable function. If DPLL3 was passed in, or the DPLL does not + * support low-power stop, or if the DPLL took too long to enter + * bypass or lock, return -EINVAL; otherwise, return 0. + */ +static int omap3_noncore_dpll_enable(struct clk *clk) +{ + int r; + struct dpll_data *dd; + + if (clk == &dpll3_ck) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (clk->rate == dd->clk_bypass->rate) { + WARN_ON(clk->parent != dd->clk_bypass); + r = _omap3_noncore_dpll_bypass(clk); + } else { + WARN_ON(clk->parent != dd->clk_ref); + r = _omap3_noncore_dpll_lock(clk); + } + /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ + if (!r) + clk->rate = omap2_get_dpll_rate(clk); + + return r; +} + +/** + * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. + * The choice of modes depends on the DPLL's programmed rate: if it is + * the same as the DPLL's parent clock, it will enter bypass; + * otherwise, it will enter lock. This code will wait for the DPLL to + * indicate readiness before returning, unless the DPLL takes too long + * to enter the target state. Intended to be used as the struct clk's + * enable function. If DPLL3 was passed in, or the DPLL does not + * support low-power stop, or if the DPLL took too long to enter + * bypass or lock, return -EINVAL; otherwise, return 0. + */ +static void omap3_noncore_dpll_disable(struct clk *clk) +{ + if (clk == &dpll3_ck) + return; + + _omap3_noncore_dpll_stop(clk); +} + + +/* Non-CORE DPLL rate set code */ + +/* + * omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * @clk: struct clk * of DPLL to set + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * @freqsel: FREQSEL value to set + * + * Program the DPLL with the supplied M, N values, and wait for the DPLL to + * lock.. Returns -EINVAL upon error, or 0 upon success. + */ +static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +{ + struct dpll_data *dd = clk->dpll_data; + u32 v; + + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ + _omap3_noncore_dpll_bypass(clk); + + /* Set jitter correction */ + v = __raw_readl(dd->control_reg); + v &= ~dd->freqsel_mask; + v |= freqsel << __ffs(dd->freqsel_mask); + __raw_writel(v, dd->control_reg); + + /* Set DPLL multiplier, divider */ + v = __raw_readl(dd->mult_div1_reg); + v &= ~(dd->mult_mask | dd->div1_mask); + v |= m << __ffs(dd->mult_mask); + v |= (n - 1) << __ffs(dd->div1_mask); + __raw_writel(v, dd->mult_div1_reg); + + /* We let the clock framework set the other output dividers later */ + + /* REVISIT: Set ramp-up delay? */ + + _omap3_noncore_dpll_lock(clk); + + return 0; +} -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) +/** + * omap3_noncore_dpll_set_rate - set non-core DPLL rate + * @clk: struct clk * of DPLL to set + * @rate: rounded target rate + * + * Set the DPLL CLKOUT to the target rate. If the DPLL can enter + * low-power bypass, and the target rate is the bypass source clock + * rate, then configure the DPLL for bypass. Otherwise, round the + * target rate if it hasn't been done already, then program and lock + * the DPLL. Returns -EINVAL upon error, or 0 upon success. + */ +static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *new_parent = NULL; + u16 freqsel; + struct dpll_data *dd; + int ret; + + if (!clk || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (rate == omap2_get_dpll_rate(clk)) + return 0; + + /* + * Ensure both the bypass and ref clocks are enabled prior to + * doing anything; we need the bypass clock running to reprogram + * the DPLL. + */ + omap2_clk_enable(dd->clk_bypass); + omap2_clk_enable(dd->clk_ref); + + if (dd->clk_bypass->rate == rate && + (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); + + ret = _omap3_noncore_dpll_bypass(clk); + if (!ret) + new_parent = dd->clk_bypass; + } else { + if (dd->last_rounded_rate != rate) + omap2_dpll_round_rate(clk, rate); + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + + pr_debug("clock: %s: set rate: locking rate to %lu.\n", + clk->name, rate); + + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + if (!ret) + new_parent = dd->clk_ref; + } + if (!ret) { + /* + * Switch the parent clock in the heirarchy, and make sure + * that the new parent's usecount is correct. Note: we + * enable the new parent before disabling the old to avoid + * any unnecessary hardware disable->enable transitions. + */ + if (clk->usecount) { + omap2_clk_enable(new_parent); + omap2_clk_disable(clk->parent); + } + clk_reparent(clk, new_parent); + clk->rate = rate; + } + omap2_clk_disable(dd->clk_ref); + omap2_clk_disable(dd->clk_bypass); + + return 0; +} + +static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) { /* * According to the 12-5 CDP code from TI, "Limitation 2.5" @@ -179,12 +831,12 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) +static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; u32 unlock_dll = 0; u32 c; - unsigned long validrate, sdrcrate, _mpurate; + unsigned long validrate, sdrcrate, mpurate; struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; @@ -192,11 +844,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (!clk || !rate) return -EINVAL; + if (clk != &dpll3_m2_ck) + return -EINVAL; + validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; - sdrcrate = sdrc_ick_p->rate; + sdrcrate = sdrc_ick.rate; if (rate > clk->rate) sdrcrate <<= ((rate / clk->rate) >> 1); else @@ -214,8 +869,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; - c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; + mpurate = arm_fck.rate / CYCLES_PER_MHZ; + c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS; c >>= SDRC_MPURATE_SCALE; @@ -251,6 +906,129 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return 0; } + +static const struct clkops clkops_noncore_dpll_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, +}; + +/* DPLL autoidle read/set code */ + + +/** + * omap3_dpll_autoidle_read - read a DPLL's autoidle bits + * @clk: struct clk * of the DPLL to read + * + * Return the DPLL's autoidle bits, shifted down to bit 0. Returns + * -EINVAL if passed a null pointer or if the struct clk does not + * appear to refer to a DPLL. + */ +static u32 omap3_dpll_autoidle_read(struct clk *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return -EINVAL; + + dd = clk->dpll_data; + + v = __raw_readl(dd->autoidle_reg); + v &= dd->autoidle_mask; + v >>= __ffs(dd->autoidle_mask); + + return v; +} + +/** + * omap3_dpll_allow_idle - enable DPLL autoidle bits + * @clk: struct clk * of the DPLL to operate on + * + * Enable DPLL automatic idle control. This automatic idle mode + * switching takes effect only when the DPLL is locked, at least on + * OMAP3430. The DPLL will enter low-power stop when its downstream + * clocks are gated. No return value. + */ +static void omap3_dpll_allow_idle(struct clk *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return; + + dd = clk->dpll_data; + + /* + * REVISIT: CORE DPLL can optionally enter low-power bypass + * by writing 0x5 instead of 0x1. Add some mechanism to + * optionally enter this mode. + */ + v = __raw_readl(dd->autoidle_reg); + v &= ~dd->autoidle_mask; + v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); + __raw_writel(v, dd->autoidle_reg); +} + +/** + * omap3_dpll_deny_idle - prevent DPLL from automatically idling + * @clk: struct clk * of the DPLL to operate on + * + * Disable DPLL automatic idle control. No return value. + */ +static void omap3_dpll_deny_idle(struct clk *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return; + + dd = clk->dpll_data; + + v = __raw_readl(dd->autoidle_reg); + v &= ~dd->autoidle_mask; + v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); + __raw_writel(v, dd->autoidle_reg); +} + +/* Clock control for DPLL outputs */ + +/** + * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate + * @clk: DPLL output struct clk + * + * Using parent clock DPLL data, look up DPLL state. If locked, set our + * rate to the dpll_clk * 2; otherwise, just use dpll_clk. + */ +static unsigned long omap3_clkoutx2_recalc(struct clk *clk) +{ + const struct dpll_data *dd; + unsigned long rate; + u32 v; + struct clk *pclk; + + /* Walk up the parents of clk, looking for a DPLL */ + pclk = clk->parent; + while (pclk && !pclk->dpll_data) + pclk = pclk->parent; + + /* clk does not have a DPLL as a parent? */ + WARN_ON(!pclk); + + dd = pclk->dpll_data; + + WARN_ON(!dd->enable_mask); + + v = __raw_readl(dd->control_reg) & dd->enable_mask; + v >>= __ffs(dd->enable_mask); + if (v != OMAP3XXX_EN_DPLL_LOCKED) + rate = clk->parent->rate; + else + rate = clk->parent->rate * 2; + return rate; +} + /* Common clock code */ /* @@ -259,7 +1037,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) */ #if defined(CONFIG_ARCH_OMAP3) -struct clk_functions omap2_clk_functions = { +static struct clk_functions omap2_clk_functions = { .clk_enable = omap2_clk_enable, .clk_disable = omap2_clk_disable, .clk_round_rate = omap2_clk_round_rate, @@ -285,7 +1063,7 @@ void omap2_clk_prepare_for_reboot(void) #endif } -void omap3_clk_lock_dpll5(void) +static void omap3_clk_lock_dpll5(void) { struct clk *dpll5_clk; struct clk *dpll5_m2_clk; @@ -315,32 +1093,19 @@ void omap3_clk_lock_dpll5(void) */ static int __init omap2_clk_arch_init(void) { - struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; - unsigned long osc_sys_rate; - if (!mpurate) return -EINVAL; - /* XXX test these for success */ - dpll1_ck = clk_get(NULL, "dpll1_ck"); - arm_fck = clk_get(NULL, "arm_fck"); - core_ck = clk_get(NULL, "core_ck"); - osc_sys_ck = clk_get(NULL, "osc_sys_ck"); - /* REVISIT: not yet ready for 343x */ - if (clk_set_rate(dpll1_ck, mpurate)) + if (clk_set_rate(&dpll1_ck, mpurate)) printk(KERN_ERR "*** Unable to set MPU rate\n"); recalculate_root_clocks(); - osc_sys_rate = clk_get_rate(osc_sys_ck); - - pr_info("Switched to new clocking rate (Crystal/Core/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (osc_sys_rate / 1000000), - ((osc_sys_rate / 100000) % 10), - (clk_get_rate(core_ck) / 1000000), - (clk_get_rate(arm_fck) / 1000000)); + printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " + "%ld.%01ld/%ld/%ld MHz\n", + (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; calibrate_delay(); @@ -348,7 +1113,83 @@ static int __init omap2_clk_arch_init(void) } arch_initcall(omap2_clk_arch_init); +int __init omap2_clk_init(void) +{ + /* struct prcm_config *prcm; */ + struct omap_clk *c; + /* u32 clkrate; */ + u32 cpu_clkflg; + + if (cpu_is_omap34xx()) { + cpu_mask = RATE_IN_343X; + cpu_clkflg = CK_343X; + + /* + * Update this if there are further clock changes between ES2 + * and production parts + */ + if (omap_rev() == OMAP3430_REV_ES1_0) { + /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ + cpu_clkflg |= CK_3430ES1; + } else { + cpu_mask |= RATE_IN_3430ES2; + cpu_clkflg |= CK_3430ES2; + } + } + + clk_init(&omap2_clk_functions); + + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + clk_preinit(c->lk.clk); + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + omap2_init_clk_clkdm(c->lk.clk); + } + + /* REVISIT: Not yet ready for OMAP3 */ +#if 0 + /* Check the MPU rate set by bootloader */ + clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck.rate) + continue; + if (prcm->dpll_speed <= clkrate) + break; + } + curr_prcm_set = prcm; #endif + recalculate_root_clocks(); + + printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " + "%ld.%01ld/%ld/%ld MHz\n", + (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable_init_clocks(); + + /* + * Lock DPLL5 and put it in autoidle. + */ + if (omap_rev() >= OMAP3430_REV_ES2_0) + omap3_clk_lock_dpll5(); + /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ + /* REVISIT: not yet ready for 343x */ +#if 0 + vclk = clk_get(NULL, "virt_prcm_set"); + sclk = clk_get(NULL, "sys_ck"); +#endif + return 0; +} + +#endif diff --git a/trunk/arch/arm/mach-omap2/clock34xx.h b/trunk/arch/arm/mach-omap2/clock34xx.h index 9a2c07eac9ad..8fe1bcb23dd9 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.h +++ b/trunk/arch/arm/mach-omap2/clock34xx.h @@ -1,24 +1,2993 @@ /* - * OMAP3 clock function prototypes and macros + * OMAP3 clock framework * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation + * + * Written by Paul Walmsley + * With many device clock fixes by Kevin Hilman and Jouni Högander + * DPLL bypass clock support added by Roman Tereshonkov + * + */ + +/* + * Virtual clocks are introduced as convenient tools. + * They are sources for other clocks and not supposed + * to be requested from drivers directly. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H +#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H + +#include + +#include "clock.h" +#include "cm.h" +#include "cm-regbits-34xx.h" +#include "prm.h" +#include "prm-regbits-34xx.h" + +#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR + +static unsigned long omap3_dpll_recalc(struct clk *clk); +static unsigned long omap3_clkoutx2_recalc(struct clk *clk); +static void omap3_dpll_allow_idle(struct clk *clk); +static void omap3_dpll_deny_idle(struct clk *clk); +static u32 omap3_dpll_autoidle_read(struct clk *clk); +static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); +static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); +static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); + +/* Maximum DPLL multiplier, divider values for OMAP3 */ +#define OMAP3_MAX_DPLL_MULT 2048 +#define OMAP3_MAX_DPLL_DIV 128 + +/* + * DPLL1 supplies clock to the MPU. + * DPLL2 supplies clock to the IVA2. + * DPLL3 supplies CORE domain clocks. + * DPLL4 supplies peripheral clocks. + * DPLL5 supplies other peripheral clocks (USBHOST, USIM). + */ + +/* Forward declarations for DPLL bypass clocks */ +static struct clk dpll1_fck; +static struct clk dpll2_fck; + +/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ +#define DPLL_LOW_POWER_STOP 0x1 +#define DPLL_LOW_POWER_BYPASS 0x5 +#define DPLL_LOCKED 0x7 + +/* PRM CLOCKS */ + +/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ +static struct clk omap_32k_fck = { + .name = "omap_32k_fck", + .ops = &clkops_null, + .rate = 32768, + .flags = RATE_FIXED, +}; + +static struct clk secure_32k_fck = { + .name = "secure_32k_fck", + .ops = &clkops_null, + .rate = 32768, + .flags = RATE_FIXED, +}; + +/* Virtual source clocks for osc_sys_ck */ +static struct clk virt_12m_ck = { + .name = "virt_12m_ck", + .ops = &clkops_null, + .rate = 12000000, + .flags = RATE_FIXED, +}; + +static struct clk virt_13m_ck = { + .name = "virt_13m_ck", + .ops = &clkops_null, + .rate = 13000000, + .flags = RATE_FIXED, +}; + +static struct clk virt_16_8m_ck = { + .name = "virt_16_8m_ck", + .ops = &clkops_null, + .rate = 16800000, + .flags = RATE_FIXED, +}; + +static struct clk virt_19_2m_ck = { + .name = "virt_19_2m_ck", + .ops = &clkops_null, + .rate = 19200000, + .flags = RATE_FIXED, +}; + +static struct clk virt_26m_ck = { + .name = "virt_26m_ck", + .ops = &clkops_null, + .rate = 26000000, + .flags = RATE_FIXED, +}; + +static struct clk virt_38_4m_ck = { + .name = "virt_38_4m_ck", + .ops = &clkops_null, + .rate = 38400000, + .flags = RATE_FIXED, +}; + +static const struct clksel_rate osc_sys_12m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_13m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_16_8m_rates[] = { + { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_19_2m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_26m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate osc_sys_38_4m_rates[] = { + { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel osc_sys_clksel[] = { + { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, + { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, + { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, + { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, + { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, + { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, + { .parent = NULL }, +}; + +/* Oscillator clock */ +/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ +static struct clk osc_sys_ck = { + .name = "osc_sys_ck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_PRM_CLKSEL, + .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, + .clksel = osc_sys_clksel, + /* REVISIT: deal with autoextclkmode? */ + .flags = RATE_FIXED, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate div2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel sys_clksel[] = { + { .parent = &osc_sys_ck, .rates = div2_rates }, + { .parent = NULL } +}; + +/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ +/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ +static struct clk sys_ck = { + .name = "sys_ck", + .ops = &clkops_null, + .parent = &osc_sys_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, + .clksel_mask = OMAP_SYSCLKDIV_MASK, + .clksel = sys_clksel, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk sys_altclk = { + .name = "sys_altclk", + .ops = &clkops_null, +}; + +/* Optional external clock input for some McBSPs */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .ops = &clkops_null, +}; + +/* PRM EXTERNAL CLOCK OUTPUT */ + +static struct clk sys_clkout1 = { + .name = "sys_clkout1", + .ops = &clkops_omap2_dflt, + .parent = &osc_sys_ck, + .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, + .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, + .recalc = &followparent_recalc, +}; + +/* DPLLS */ + +/* CM CLOCKS */ + +static const struct clksel_rate div16_dpll_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 5, .val = 5, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 7, .val = 7, .flags = RATE_IN_343X }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 9, .val = 9, .flags = RATE_IN_343X }, + { .div = 10, .val = 10, .flags = RATE_IN_343X }, + { .div = 11, .val = 11, .flags = RATE_IN_343X }, + { .div = 12, .val = 12, .flags = RATE_IN_343X }, + { .div = 13, .val = 13, .flags = RATE_IN_343X }, + { .div = 14, .val = 14, .flags = RATE_IN_343X }, + { .div = 15, .val = 15, .flags = RATE_IN_343X }, + { .div = 16, .val = 16, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +/* DPLL1 */ +/* MPU clock source */ +/* Type: DPLL */ +static struct dpll_data dpll1_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, + .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .clk_bypass = &dpll1_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE +}; + +static struct clk dpll1_ck = { + .name = "dpll1_ck", + .ops = &clkops_null, + .parent = &sys_ck, + .dpll_data = &dpll1_dd, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll1_clkdm", + .recalc = &omap3_dpll_recalc, +}; + +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed. + */ +static struct clk dpll1_x2_ck = { + .name = "dpll1_x2_ck", + .ops = &clkops_null, + .parent = &dpll1_ck, + .clkdm_name = "dpll1_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ +static const struct clksel div16_dpll1_x2m2_clksel[] = { + { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* + * Does not exist in the TRM - needed to separate the M2 divider from + * bypass selection in mpu_ck + */ +static struct clk dpll1_x2m2_ck = { + .name = "dpll1_x2m2_ck", + .ops = &clkops_null, + .parent = &dpll1_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), + .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, + .clksel = div16_dpll1_x2m2_clksel, + .clkdm_name = "dpll1_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* DPLL2 */ +/* IVA2 clock source */ +/* Type: DPLL */ + +static struct dpll_data dpll2_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, + .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .clk_bypass = &dpll2_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | + (1 << DPLL_LOW_POWER_BYPASS), + .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE +}; + +static struct clk dpll2_ck = { + .name = "dpll2_ck", + .ops = &clkops_noncore_dpll_ops, + .parent = &sys_ck, + .dpll_data = &dpll2_dd, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll2_clkdm", + .recalc = &omap3_dpll_recalc, +}; + +static const struct clksel div16_dpll2_m2x2_clksel[] = { + { .parent = &dpll2_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* + * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT + * or CLKOUTX2. CLKOUT seems most plausible. + */ +static struct clk dpll2_m2_ck = { + .name = "dpll2_m2_ck", + .ops = &clkops_null, + .parent = &dpll2_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKSEL2_PLL), + .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, + .clksel = div16_dpll2_m2x2_clksel, + .clkdm_name = "dpll2_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* + * DPLL3 + * Source clock for all interfaces and for some device fclks + * REVISIT: Also supports fast relock bypass - not included below + */ +static struct dpll_data dpll3_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, + .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE +}; + +static struct clk dpll3_ck = { + .name = "dpll3_ck", + .ops = &clkops_null, + .parent = &sys_ck, + .dpll_data = &dpll3_dd, + .round_rate = &omap2_dpll_round_rate, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap3_dpll_recalc, +}; + +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed + */ +static struct clk dpll3_x2_ck = { + .name = "dpll3_x2_ck", + .ops = &clkops_null, + .parent = &dpll3_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel_rate div31_dpll3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, + { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, + { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, + { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, + { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, + { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, + { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, + { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, + { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, + { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, + { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, + { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, + { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, + { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, + { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, + { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, + { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, + { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, + { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, + { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, + { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, + { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, + { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, + { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, + { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, + { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, + { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, + { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, + { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, + { .div = 0 }, +}; + +static const struct clksel div31_dpll3m2_clksel[] = { + { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, + { .parent = NULL } +}; + +/* DPLL3 output M2 - primary control point for CORE speed */ +static struct clk dpll3_m2_ck = { + .name = "dpll3_m2_ck", + .ops = &clkops_null, + .parent = &dpll3_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, + .clksel = div31_dpll3m2_clksel, + .clkdm_name = "dpll3_clkdm", + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap3_core_dpll_m2_set_rate, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk core_ck = { + .name = "core_ck", + .ops = &clkops_null, + .parent = &dpll3_m2_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dpll3_m2x2_ck = { + .name = "dpll3_m2x2_ck", + .ops = &clkops_null, + .parent = &dpll3_m2_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static const struct clksel div16_dpll3_clksel[] = { + { .parent = &dpll3_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* This virtual clock is the source for dpll3_m3x2_ck */ +static struct clk dpll3_m3_ck = { + .name = "dpll3_m3_ck", + .ops = &clkops_null, + .parent = &dpll3_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL3_MASK, + .clksel = div16_dpll3_clksel, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll3_m3x2_ck = { + .name = "dpll3_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll3_m3_ck, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll3_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +static struct clk emu_core_alwon_ck = { + .name = "emu_core_alwon_ck", + .ops = &clkops_null, + .parent = &dpll3_m3x2_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &followparent_recalc, +}; + +/* DPLL4 */ +/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ +/* Type: DPLL */ +static struct dpll_data dpll4_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, + .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE +}; + +static struct clk dpll4_ck = { + .name = "dpll4_ck", + .ops = &clkops_noncore_dpll_ops, + .parent = &sys_ck, + .dpll_data = &dpll4_dd, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_dpll4_set_rate, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_dpll_recalc, +}; + +/* + * This virtual clock provides the CLKOUTX2 output from the DPLL if the + * DPLL isn't bypassed -- + * XXX does this serve any downstream clocks? + */ +static struct clk dpll4_x2_ck = { + .name = "dpll4_x2_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel div16_dpll4_clksel[] = { + { .parent = &dpll4_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +/* This virtual clock is the source for dpll4_m2x2_ck */ +static struct clk dpll4_m2_ck = { + .name = "dpll4_m2_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), + .clksel_mask = OMAP3430_DIV_96M_MASK, + .clksel = div16_dpll4_clksel, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m2x2_ck = { + .name = "dpll4_m2x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll4_m2_ck, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_96M_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +/* + * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as + * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: + * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and + * CM_96K_(F)CLK. + */ +static struct clk omap_96m_alwon_fck = { + .name = "omap_96m_alwon_fck", + .ops = &clkops_null, + .parent = &dpll4_m2x2_ck, + .recalc = &followparent_recalc, +}; + +static struct clk cm_96m_fck = { + .name = "cm_96m_fck", + .ops = &clkops_null, + .parent = &omap_96m_alwon_fck, + .recalc = &followparent_recalc, +}; + +static const struct clksel_rate omap_96m_dpll_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_96m_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_96m_fck_clksel[] = { + { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, + { .parent = &sys_ck, .rates = omap_96m_sys_rates }, + { .parent = NULL } +}; + +static struct clk omap_96m_fck = { + .name = "omap_96m_fck", + .ops = &clkops_null, + .parent = &sys_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_96M_MASK, + .clksel = omap_96m_fck_clksel, + .recalc = &omap2_clksel_recalc, +}; + +/* This virtual clock is the source for dpll4_m3x2_ck */ +static struct clk dpll4_m3_ck = { + .name = "dpll4_m3_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_TV_MASK, + .clksel = div16_dpll4_clksel, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m3x2_ck = { + .name = "dpll4_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll4_m3_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_TV_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +static const struct clksel_rate omap_54m_d4m3x2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_54m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_54m_clksel[] = { + { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, + { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, + { .parent = NULL } +}; + +static struct clk omap_54m_fck = { + .name = "omap_54m_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_54M_MASK, + .clksel = omap_54m_clksel, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate omap_48m_cm96m_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_48m_clksel[] = { + { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, + { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, + { .parent = NULL } +}; + +static struct clk omap_48m_fck = { + .name = "omap_48m_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_48M_MASK, + .clksel = omap_48m_clksel, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk omap_12m_fck = { + .name = "omap_12m_fck", + .ops = &clkops_null, + .parent = &omap_48m_fck, + .fixed_div = 4, + .recalc = &omap2_fixed_divisor_recalc, +}; + +/* This virstual clock is the source for dpll4_m4x2_ck */ +static struct clk dpll4_m4_ck = { + .name = "dpll4_m4_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, + .clksel = div16_dpll4_clksel, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m4x2_ck = { + .name = "dpll4_m4x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll4_m4_ck, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +/* This virtual clock is the source for dpll4_m5x2_ck */ +static struct clk dpll4_m5_ck = { + .name = "dpll4_m5_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, + .clksel = div16_dpll4_clksel, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m5x2_ck = { + .name = "dpll4_m5x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll4_m5_ck, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +/* This virtual clock is the source for dpll4_m6x2_ck */ +static struct clk dpll4_m6_ck = { + .name = "dpll4_m6_ck", + .ops = &clkops_null, + .parent = &dpll4_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_DIV_DPLL4_MASK, + .clksel = div16_dpll4_clksel, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* The PWRDN bit is apparently only available on 3430ES2 and above */ +static struct clk dpll4_m6x2_ck = { + .name = "dpll4_m6x2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll4_m6_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", + .recalc = &omap3_clkoutx2_recalc, +}; + +static struct clk emu_per_alwon_ck = { + .name = "emu_per_alwon_ck", + .ops = &clkops_null, + .parent = &dpll4_m6x2_ck, + .clkdm_name = "dpll4_clkdm", + .recalc = &followparent_recalc, +}; + +/* DPLL5 */ +/* Supplies 120MHz clock, USIM source clock */ +/* Type: DPLL */ +/* 3430ES2 only */ +static struct dpll_data dpll5_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), + .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, + .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), + .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), + .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), + .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE +}; + +static struct clk dpll5_ck = { + .name = "dpll5_ck", + .ops = &clkops_noncore_dpll_ops, + .parent = &sys_ck, + .dpll_data = &dpll5_dd, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll5_clkdm", + .recalc = &omap3_dpll_recalc, +}; + +static const struct clksel div16_dpll5_clksel[] = { + { .parent = &dpll5_ck, .rates = div16_dpll_rates }, + { .parent = NULL } +}; + +static struct clk dpll5_m2_ck = { + .name = "dpll5_m2_ck", + .ops = &clkops_null, + .parent = &dpll5_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), + .clksel_mask = OMAP3430ES2_DIV_120M_MASK, + .clksel = div16_dpll5_clksel, + .clkdm_name = "dpll5_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* CM EXTERNAL CLOCK OUTPUTS */ + +static const struct clksel_rate clkout2_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel clkout2_src_clksel[] = { + { .parent = &core_ck, .rates = clkout2_src_core_rates }, + { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, + { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, + { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, + { .parent = NULL } +}; + +static struct clk clkout2_src_ck = { + .name = "clkout2_src_ck", + .ops = &clkops_omap2_dflt, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP3430_CM_CLKOUT_CTRL, + .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, + .clksel = clkout2_src_clksel, + .clkdm_name = "core_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate sys_clkout2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 1, .flags = RATE_IN_343X }, + { .div = 4, .val = 2, .flags = RATE_IN_343X }, + { .div = 8, .val = 3, .flags = RATE_IN_343X }, + { .div = 16, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel sys_clkout2_clksel[] = { + { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, + { .parent = NULL }, +}; + +static struct clk sys_clkout2 = { + .name = "sys_clkout2", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, + .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, + .clksel = sys_clkout2_clksel, + .recalc = &omap2_clksel_recalc, +}; + +/* CM OUTPUT CLOCKS */ + +static struct clk corex2_fck = { + .name = "corex2_fck", + .ops = &clkops_null, + .parent = &dpll3_m2x2_ck, + .recalc = &followparent_recalc, +}; + +/* DPLL power domain clock controls */ + +static const struct clksel_rate div4_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel div4_core_clksel[] = { + { .parent = &core_ck, .rates = div4_rates }, + { .parent = NULL } +}; + +/* + * REVISIT: Are these in DPLL power domain or CM power domain? docs + * may be inconsistent here? + */ +static struct clk dpll1_fck = { + .name = "dpll1_fck", + .ops = &clkops_null, + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, + .clksel = div4_core_clksel, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mpu_ck = { + .name = "mpu_ck", + .ops = &clkops_null, + .parent = &dpll1_x2m2_ck, + .clkdm_name = "mpu_clkdm", + .recalc = &followparent_recalc, +}; + +/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ +static const struct clksel_rate arm_fck_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 1, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel arm_fck_clksel[] = { + { .parent = &mpu_ck, .rates = arm_fck_rates }, + { .parent = NULL } +}; + +static struct clk arm_fck = { + .name = "arm_fck", + .ops = &clkops_null, + .parent = &mpu_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, + .clksel = arm_fck_clksel, + .clkdm_name = "mpu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* XXX What about neon_clkdm ? */ + +/* + * REVISIT: This clock is never specifically defined in the 3430 TRM, + * although it is referenced - so this is a guess + */ +static struct clk emu_mpu_alwon_ck = { + .name = "emu_mpu_alwon_ck", + .ops = &clkops_null, + .parent = &mpu_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dpll2_fck = { + .name = "dpll2_fck", + .ops = &clkops_null, + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, + .clksel = div4_core_clksel, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk iva2_ck = { + .name = "iva2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &dpll2_m2_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, + .clkdm_name = "iva2_clkdm", + .recalc = &followparent_recalc, +}; + +/* Common interface clocks */ + +static const struct clksel div2_core_clksel[] = { + { .parent = &core_ck, .rates = div2_rates }, + { .parent = NULL } +}; + +static struct clk l3_ick = { + .name = "l3_ick", + .ops = &clkops_null, + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_L3_MASK, + .clksel = div2_core_clksel, + .clkdm_name = "core_l3_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel div2_l3_clksel[] = { + { .parent = &l3_ick, .rates = div2_rates }, + { .parent = NULL } +}; + +static struct clk l4_ick = { + .name = "l4_ick", + .ops = &clkops_null, + .parent = &l3_ick, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_L4_MASK, + .clksel = div2_l3_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, + +}; + +static const struct clksel div2_l4_clksel[] = { + { .parent = &l4_ick, .rates = div2_rates }, + { .parent = NULL } +}; + +static struct clk rm_ick = { + .name = "rm_ick", + .ops = &clkops_null, + .parent = &l4_ick, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_RM_MASK, + .clksel = div2_l4_clksel, + .recalc = &omap2_clksel_recalc, +}; + +/* GFX power domain */ + +/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ + +static const struct clksel gfx_l3_clksel[] = { + { .parent = &l3_ick, .rates = gfx_l3_rates }, + { .parent = NULL } +}; + +/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ +static struct clk gfx_l3_ck = { + .name = "gfx_l3_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &l3_ick, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk gfx_l3_fck = { + .name = "gfx_l3_fck", + .ops = &clkops_null, + .parent = &gfx_l3_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + .clksel_mask = OMAP_CLKSEL_GFX_MASK, + .clksel = gfx_l3_clksel, + .clkdm_name = "gfx_3430es1_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gfx_l3_ick = { + .name = "gfx_l3_ick", + .ops = &clkops_null, + .parent = &gfx_l3_ck, + .clkdm_name = "gfx_3430es1_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gfx_cg1_ck = { + .name = "gfx_cg1_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &gfx_l3_fck, /* REVISIT: correct? */ + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_2D_SHIFT, + .clkdm_name = "gfx_3430es1_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gfx_cg2_ck = { + .name = "gfx_cg2_ck", + .ops = &clkops_omap2_dflt_wait, + .parent = &gfx_l3_fck, /* REVISIT: correct? */ + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_3D_SHIFT, + .clkdm_name = "gfx_3430es1_clkdm", + .recalc = &followparent_recalc, +}; + +/* SGX power domain - 3430ES2 only */ + +static const struct clksel_rate sgx_core_rates[] = { + { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 1, .flags = RATE_IN_343X }, + { .div = 6, .val = 2, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate sgx_96m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel sgx_clksel[] = { + { .parent = &core_ck, .rates = sgx_core_rates }, + { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, + { .parent = NULL }, +}; + +static struct clk sgx_fck = { + .name = "sgx_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, + .clksel = sgx_clksel, + .clkdm_name = "sgx_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk sgx_ick = { + .name = "sgx_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, + .clkdm_name = "sgx_clkdm", + .recalc = &followparent_recalc, +}; + +/* CORE power domain */ + +static struct clk d2d_26m_fck = { + .name = "d2d_26m_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, + .clkdm_name = "d2d_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk modem_fck = { + .name = "modem_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MODEM_SHIFT, + .clkdm_name = "d2d_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk sad2d_ick = { + .name = "sad2d_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SAD2D_SHIFT, + .clkdm_name = "d2d_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mad2d_ick = { + .name = "mad2d_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430_EN_MAD2D_SHIFT, + .clkdm_name = "d2d_clkdm", + .recalc = &followparent_recalc, +}; + +static const struct clksel omap343x_gpt_clksel[] = { + { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = NULL} +}; + +static struct clk gpt10_fck = { + .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_GPT10_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt11_fck = { + .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_GPT11_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk cpefuse_fck = { + .name = "cpefuse_fck", + .ops = &clkops_omap2_dflt, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk ts_fck = { + .name = "ts_fck", + .ops = &clkops_omap2_dflt, + .parent = &omap_32k_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_TS_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk usbtll_fck = { + .name = "usbtll_fck", + .ops = &clkops_omap2_dflt, + .parent = &dpll5_m2_ck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .recalc = &followparent_recalc, +}; + +/* CORE 96M FCLK-derived clocks */ + +static struct clk core_96m_fck = { + .name = "core_96m_fck", + .ops = &clkops_null, + .parent = &omap_96m_fck, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs3_fck = { + .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs2_fck = { + .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mspro_fck = { + .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs1_fck = { + .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_fck = { + .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c2_fck = { + .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c1_fck = { + .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +/* + * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; + * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. + */ +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel mcbsp_15_clksel[] = { + { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + +static struct clk mcbsp5_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 5, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, + .clksel = mcbsp_15_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp1_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_15_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* CORE_48M_FCK-derived clocks */ + +static struct clk core_48m_fck = { + .name = "core_48m_fck", + .ops = &clkops_null, + .parent = &omap_48m_fck, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcspi4_fck = { + .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 4, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi3_fck = { + .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi2_fck = { + .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk mcspi1_fck = { + .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk uart2_fck = { + .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk uart1_fck = { + .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk fshostusb_fck = { + .name = "fshostusb_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_48m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + .recalc = &followparent_recalc, +}; + +/* CORE_12M_FCK based clocks */ + +static struct clk core_12m_fck = { + .name = "core_12m_fck", + .ops = &clkops_null, + .parent = &omap_12m_fck, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk hdq_fck = { + .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_12m_fck, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .recalc = &followparent_recalc, +}; + +/* DPLL3-derived clock */ + +static const struct clksel_rate ssi_ssr_corex2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_clksel[] = { + { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, + { .parent = NULL } +}; + +static struct clk ssi_ssr_fck_3430es1 = { + .name = "ssi_ssr_fck", + .ops = &clkops_omap2_dflt, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, + .clksel = ssi_ssr_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk ssi_ssr_fck_3430es2 = { + .name = "ssi_ssr_fck", + .ops = &clkops_omap3430es2_ssi_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, + .clksel = ssi_ssr_clksel, + .clkdm_name = "core_l4_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk ssi_sst_fck_3430es1 = { + .name = "ssi_sst_fck", + .ops = &clkops_null, + .parent = &ssi_ssr_fck_3430es1, + .fixed_div = 2, + .recalc = &omap2_fixed_divisor_recalc, +}; + +static struct clk ssi_sst_fck_3430es2 = { + .name = "ssi_sst_fck", + .ops = &clkops_null, + .parent = &ssi_ssr_fck_3430es2, + .fixed_div = 2, + .recalc = &omap2_fixed_divisor_recalc, +}; + + + +/* CORE_L3_ICK based clocks */ + +/* + * XXX must add clk_enable/clk_disable for these if standard code won't + * handle it + */ +static struct clk core_l3_ick = { + .name = "core_l3_ick", + .ops = &clkops_null, + .parent = &l3_ick, + .clkdm_name = "core_l3_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk hsotgusb_ick_3430es1 = { + .name = "hsotgusb_ick", + .ops = &clkops_omap2_dflt, + .parent = &core_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .clkdm_name = "core_l3_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk hsotgusb_ick_3430es2 = { + .name = "hsotgusb_ick", + .ops = &clkops_omap3430es2_hsotgusb_wait, + .parent = &core_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .clkdm_name = "core_l3_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk sdrc_ick = { + .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpmc_fck = { + .name = "gpmc_fck", + .ops = &clkops_null, + .parent = &core_l3_ick, + .flags = ENABLE_ON_INIT, /* huh? */ + .clkdm_name = "core_l3_clkdm", + .recalc = &followparent_recalc, +}; + +/* SECURITY_L3_ICK based clocks */ + +static struct clk security_l3_ick = { + .name = "security_l3_ick", + .ops = &clkops_null, + .parent = &l3_ick, + .recalc = &followparent_recalc, +}; + +static struct clk pka_ick = { + .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &security_l3_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_PKA_SHIFT, + .recalc = &followparent_recalc, +}; + +/* CORE_L4_ICK based clocks */ + +static struct clk core_l4_ick = { + .name = "core_l4_ick", + .ops = &clkops_null, + .parent = &l4_ick, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk usbtll_ick = { + .name = "usbtll_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs3_ick = { + .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +/* Intersystem Communication Registers - chassis mode only */ +static struct clk icr_ick = { + .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_ICR_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk aes2_ick = { + .name = "aes2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_AES2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk sha12_ick = { + .name = "sha12_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SHA12_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk des2_ick = { + .name = "des2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_DES2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs2_ick = { + .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mmchs1_ick = { + .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mspro_ick = { + .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk hdq_ick = { + .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcspi4_ick = { + .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 4, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcspi3_ick = { + .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcspi2_ick = { + .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcspi1_ick = { + .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c3_ick = { + .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c2_ick = { + .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk i2c1_ick = { + .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk uart2_ick = { + .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk uart1_ick = { + .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt11_ick = { + .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt10_ick = { + .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp5_ick = { + .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 5, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp1_ick = { + .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 1, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk fac_ick = { + .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mailboxes_ick = { + .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk omapctrl_ick = { + .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .recalc = &followparent_recalc, +}; + +/* SSI_L4_ICK based clocks */ + +static struct clk ssi_l4_ick = { + .name = "ssi_l4_ick", + .ops = &clkops_null, + .parent = &l4_ick, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk ssi_ick_3430es1 = { + .name = "ssi_ick", + .ops = &clkops_omap2_dflt, + .parent = &ssi_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk ssi_ick_3430es2 = { + .name = "ssi_ick", + .ops = &clkops_omap3430es2_ssi_wait, + .parent = &ssi_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + +/* REVISIT: Technically the TRM claims that this is CORE_CLK based, + * but l4_ick makes more sense to me */ + +static const struct clksel usb_l4_clksel[] = { + { .parent = &l4_ick, .rates = div2_rates }, + { .parent = NULL }, +}; + +static struct clk usb_l4_ick = { + .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &l4_ick, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, + .clksel = usb_l4_clksel, + .recalc = &omap2_clksel_recalc, +}; + +/* SECURITY_L4_ICK2 based clocks */ + +static struct clk security_l4_ick2 = { + .name = "security_l4_ick2", + .ops = &clkops_null, + .parent = &l4_ick, + .recalc = &followparent_recalc, +}; + +static struct clk aes1_ick = { + .name = "aes1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_AES1_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk rng_ick = { + .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_RNG_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk sha11_ick = { + .name = "sha11_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_SHA11_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk des1_ick = { + .name = "des1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &security_l4_ick2, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_DES1_SHIFT, + .recalc = &followparent_recalc, +}; + +/* DSS */ +static struct clk dss1_alwon_fck_3430es1 = { + .name = "dss1_alwon_fck", + .ops = &clkops_omap2_dflt, + .parent = &dpll4_m4x2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss1_alwon_fck_3430es2 = { + .name = "dss1_alwon_fck", + .ops = &clkops_omap3430es2_dss_usbhost_wait, + .parent = &dpll4_m4x2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss_tv_fck = { + .name = "dss_tv_fck", + .ops = &clkops_omap2_dflt, + .parent = &omap_54m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss_96m_fck = { + .name = "dss_96m_fck", + .ops = &clkops_omap2_dflt, + .parent = &omap_96m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss2_alwon_fck = { + .name = "dss2_alwon_fck", + .ops = &clkops_omap2_dflt, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS2_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss_ick_3430es1 = { + /* Handles both L3 and L4 clocks */ + .name = "dss_ick", + .ops = &clkops_omap2_dflt, + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk dss_ick_3430es2 = { + /* Handles both L3 and L4 clocks */ + .name = "dss_ick", + .ops = &clkops_omap3430es2_dss_usbhost_wait, + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, + .clkdm_name = "dss_clkdm", + .recalc = &followparent_recalc, +}; + +/* CAM */ + +static struct clk cam_mclk = { + .name = "cam_mclk", + .ops = &clkops_omap2_dflt, + .parent = &dpll4_m5x2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .clkdm_name = "cam_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk cam_ick = { + /* Handles both L3 and L4 clocks */ + .name = "cam_ick", + .ops = &clkops_omap2_dflt, + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .clkdm_name = "cam_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk csi2_96m_fck = { + .name = "csi2_96m_fck", + .ops = &clkops_omap2_dflt, + .parent = &core_96m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CSI2_SHIFT, + .clkdm_name = "cam_clkdm", + .recalc = &followparent_recalc, +}; + +/* USBHOST - 3430ES2 only */ + +static struct clk usbhost_120m_fck = { + .name = "usbhost_120m_fck", + .ops = &clkops_omap2_dflt, + .parent = &dpll5_m2_ck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, + .clkdm_name = "usbhost_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_48m_fck = { + .name = "usbhost_48m_fck", + .ops = &clkops_omap3430es2_dss_usbhost_wait, + .parent = &omap_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .clkdm_name = "usbhost_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk usbhost_ick = { + /* Handles both L3 and L4 clocks */ + .name = "usbhost_ick", + .ops = &clkops_omap3430es2_dss_usbhost_wait, + .parent = &l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .clkdm_name = "usbhost_clkdm", + .recalc = &followparent_recalc, +}; + +/* WKUP */ + +static const struct clksel_rate usim_96m_rates[] = { + { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 8, .val = 5, .flags = RATE_IN_343X }, + { .div = 10, .val = 6, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel_rate usim_120m_rates[] = { + { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 8, .val = 8, .flags = RATE_IN_343X }, + { .div = 16, .val = 9, .flags = RATE_IN_343X }, + { .div = 20, .val = 10, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel usim_clksel[] = { + { .parent = &omap_96m_fck, .rates = usim_96m_rates }, + { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, + { .parent = &sys_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +/* 3430ES2 only */ +static struct clk usim_fck = { + .name = "usim_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, + .clksel = usim_clksel, + .recalc = &omap2_clksel_recalc, +}; + +/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ +static struct clk gpt1_fck = { + .name = "gpt1_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT1_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "wkup_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk wkup_32k_fck = { + .name = "wkup_32k_fck", + .ops = &clkops_null, + .parent = &omap_32k_fck, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_dbck = { + .name = "gpio1_dbck", + .ops = &clkops_omap2_dflt, + .parent = &wkup_32k_fck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wdt2_fck = { + .name = "wdt2_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_32k_fck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wkup_l4_ick = { + .name = "wkup_l4_ick", + .ops = &clkops_null, + .parent = &sys_ck, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +/* 3430ES2 only */ +/* Never specifically named in the TRM, so we have to infer a likely name */ +static struct clk usim_ick = { + .name = "usim_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wdt2_ick = { + .name = "wdt2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wdt1_ick = { + .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_ick = { + .name = "gpio1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk omap_32ksync_ick = { + .name = "omap_32ksync_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +/* XXX This clock no longer exists in 3430 TRM rev F */ +static struct clk gpt12_ick = { + .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT12_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt1_ick = { + .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &wkup_l4_ick, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + + + +/* PER clock domain */ + +static struct clk per_96m_fck = { + .name = "per_96m_fck", + .ops = &clkops_null, + .parent = &omap_96m_alwon_fck, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk per_48m_fck = { + .name = "per_48m_fck", + .ops = &clkops_null, + .parent = &omap_48m_fck, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk uart3_fck = { + .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt2_fck = { + .name = "gpt2_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt3_fck = { + .name = "gpt3_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt4_fck = { + .name = "gpt4_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt5_fck = { + .name = "gpt5_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt6_fck = { + .name = "gpt6_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt7_fck = { + .name = "gpt7_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT7_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt8_fck = { + .name = "gpt8_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT8_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpt9_fck = { + .name = "gpt9_fck", + .ops = &clkops_omap2_dflt_wait, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPT9_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, + .clksel = omap343x_gpt_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk per_32k_alwon_fck = { + .name = "per_32k_alwon_fck", + .ops = &clkops_null, + .parent = &omap_32k_fck, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio6_dbck = { + .name = "gpio6_dbck", + .ops = &clkops_omap2_dflt, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio5_dbck = { + .name = "gpio5_dbck", + .ops = &clkops_omap2_dflt, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio4_dbck = { + .name = "gpio4_dbck", + .ops = &clkops_omap2_dflt, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_dbck = { + .name = "gpio3_dbck", + .ops = &clkops_omap2_dflt, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_dbck = { + .name = "gpio2_dbck", + .ops = &clkops_omap2_dflt, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wdt3_fck = { + .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_32k_alwon_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk per_l4_ick = { + .name = "per_l4_ick", + .ops = &clkops_null, + .parent = &l4_ick, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio6_ick = { + .name = "gpio6_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio5_ick = { + .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio4_ick = { + .name = "gpio4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_ick = { + .name = "gpio3_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_ick = { + .name = "gpio2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk wdt3_ick = { + .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk uart3_ick = { + .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt9_ick = { + .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT9_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt8_ick = { + .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT8_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt7_ick = { + .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT7_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt6_ick = { + .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt5_ick = { + .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt4_ick = { + .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt3_ick = { + .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk gpt2_ick = { + .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp2_ick = { + .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp3_ick = { + .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk mcbsp4_ick = { + .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, + .id = 4, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + +static const struct clksel mcbsp_234_clksel[] = { + { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + +static struct clk mcbsp2_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 2, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp3_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 3, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk mcbsp4_fck = { + .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, + .id = 4, + .init = &omap2_init_clksel_parent, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, + .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .clksel = mcbsp_234_clksel, + .clkdm_name = "per_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* EMU clocks */ + +/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ + +static const struct clksel_rate emu_src_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_per_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_mpu_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 }, +}; + +static const struct clksel emu_src_clksel[] = { + { .parent = &sys_ck, .rates = emu_src_sys_rates }, + { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, + { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, + { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, + { .parent = NULL }, +}; + +/* + * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only + * to switch the source of some of the EMU clocks. + * XXX Are there CLKEN bits for these EMU clks? */ +static struct clk emu_src_ck = { + .name = "emu_src_ck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_MUX_CTRL_MASK, + .clksel = emu_src_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate pclk_emu_rates[] = { + { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 6, .val = 6, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel pclk_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = pclk_emu_rates }, + { .parent = NULL }, +}; + +static struct clk pclk_fck = { + .name = "pclk_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, + .clksel = pclk_emu_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate pclkx2_emu_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 3, .val = 3, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel pclkx2_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, + { .parent = NULL }, +}; + +static struct clk pclkx2_fck = { + .name = "pclkx2_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, + .clksel = pclkx2_emu_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel atclk_emu_clksel[] = { + { .parent = &emu_src_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +static struct clk atclk_fck = { + .name = "atclk_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, + .clksel = atclk_emu_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static struct clk traceclk_src_fck = { + .name = "traceclk_src_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, + .clksel = emu_src_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate traceclk_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 }, +}; + +static const struct clksel traceclk_clksel[] = { + { .parent = &traceclk_src_fck, .rates = traceclk_rates }, + { .parent = NULL }, +}; + +static struct clk traceclk_fck = { + .name = "traceclk_fck", + .ops = &clkops_null, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, + .clksel = traceclk_clksel, + .clkdm_name = "emu_clkdm", + .recalc = &omap2_clksel_recalc, +}; + +/* SR clocks */ + +/* SmartReflex fclk (VDD1) */ +static struct clk sr1_fck = { + .name = "sr1_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR1_SHIFT, + .recalc = &followparent_recalc, +}; + +/* SmartReflex fclk (VDD2) */ +static struct clk sr2_fck = { + .name = "sr2_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &sys_ck, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR2_SHIFT, + .recalc = &followparent_recalc, +}; -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H +static struct clk sr_l4_ick = { + .name = "sr_l4_ick", + .ops = &clkops_null, /* RMK: missing? */ + .parent = &l4_ick, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); -void omap3_clk_lock_dpll5(void); +/* SECURE_32K_FCK clocks */ -extern struct clk *sdrc_ick_p; -extern struct clk *arm_fck_p; +static struct clk gpt12_fck = { + .name = "gpt12_fck", + .ops = &clkops_null, + .parent = &secure_32k_fck, + .recalc = &followparent_recalc, +}; -/* OMAP34xx-specific clkops */ -extern const struct clkops clkops_omap3430es2_ssi_wait; -extern const struct clkops clkops_omap3430es2_hsotgusb_wait; -extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; -extern const struct clkops clkops_noncore_dpll_ops; +static struct clk wdt1_fck = { + .name = "wdt1_fck", + .ops = &clkops_null, + .parent = &secure_32k_fck, + .recalc = &followparent_recalc, +}; #endif diff --git a/trunk/arch/arm/mach-omap2/clock34xx_data.c b/trunk/arch/arm/mach-omap2/clock34xx_data.c deleted file mode 100644 index 8bdcc9cc7f9a..000000000000 --- a/trunk/arch/arm/mach-omap2/clock34xx_data.c +++ /dev/null @@ -1,3289 +0,0 @@ -/* - * OMAP3 clock data - * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation - * - * Written by Paul Walmsley - * With many device clock fixes by Kevin Hilman and Jouni Högander - * DPLL bypass clock support added by Roman Tereshonkov - * - */ - -/* - * Virtual clocks are introduced as convenient tools. - * They are sources for other clocks and not supposed - * to be requested from drivers directly. - */ - -#include -#include -#include - -#include -#include - -#include "clock.h" -#include "clock34xx.h" -#include "cm.h" -#include "cm-regbits-34xx.h" -#include "prm.h" -#include "prm-regbits-34xx.h" - -/* - * clocks - */ - -#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR - -/* Maximum DPLL multiplier, divider values for OMAP3 */ -#define OMAP3_MAX_DPLL_MULT 2048 -#define OMAP3_MAX_DPLL_DIV 128 - -/* - * DPLL1 supplies clock to the MPU. - * DPLL2 supplies clock to the IVA2. - * DPLL3 supplies CORE domain clocks. - * DPLL4 supplies peripheral clocks. - * DPLL5 supplies other peripheral clocks (USBHOST, USIM). - */ - -/* Forward declarations for DPLL bypass clocks */ -static struct clk dpll1_fck; -static struct clk dpll2_fck; - -/* PRM CLOCKS */ - -/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ -static struct clk omap_32k_fck = { - .name = "omap_32k_fck", - .ops = &clkops_null, - .rate = 32768, - .flags = RATE_FIXED, -}; - -static struct clk secure_32k_fck = { - .name = "secure_32k_fck", - .ops = &clkops_null, - .rate = 32768, - .flags = RATE_FIXED, -}; - -/* Virtual source clocks for osc_sys_ck */ -static struct clk virt_12m_ck = { - .name = "virt_12m_ck", - .ops = &clkops_null, - .rate = 12000000, - .flags = RATE_FIXED, -}; - -static struct clk virt_13m_ck = { - .name = "virt_13m_ck", - .ops = &clkops_null, - .rate = 13000000, - .flags = RATE_FIXED, -}; - -static struct clk virt_16_8m_ck = { - .name = "virt_16_8m_ck", - .ops = &clkops_null, - .rate = 16800000, - .flags = RATE_FIXED, -}; - -static struct clk virt_19_2m_ck = { - .name = "virt_19_2m_ck", - .ops = &clkops_null, - .rate = 19200000, - .flags = RATE_FIXED, -}; - -static struct clk virt_26m_ck = { - .name = "virt_26m_ck", - .ops = &clkops_null, - .rate = 26000000, - .flags = RATE_FIXED, -}; - -static struct clk virt_38_4m_ck = { - .name = "virt_38_4m_ck", - .ops = &clkops_null, - .rate = 38400000, - .flags = RATE_FIXED, -}; - -static const struct clksel_rate osc_sys_12m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_13m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_19_2m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_26m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_38_4m_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel osc_sys_clksel[] = { - { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, - { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, - { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, - { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, - { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, - { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, - { .parent = NULL }, -}; - -/* Oscillator clock */ -/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ -static struct clk osc_sys_ck = { - .name = "osc_sys_ck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_PRM_CLKSEL, - .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, - .clksel = osc_sys_clksel, - /* REVISIT: deal with autoextclkmode? */ - .flags = RATE_FIXED, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 0 } -}; - -static const struct clksel sys_clksel[] = { - { .parent = &osc_sys_ck, .rates = div2_rates }, - { .parent = NULL } -}; - -/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ -/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ -static struct clk sys_ck = { - .name = "sys_ck", - .ops = &clkops_null, - .parent = &osc_sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, - .clksel_mask = OMAP_SYSCLKDIV_MASK, - .clksel = sys_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk sys_altclk = { - .name = "sys_altclk", - .ops = &clkops_null, -}; - -/* Optional external clock input for some McBSPs */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - -/* PRM EXTERNAL CLOCK OUTPUT */ - -static struct clk sys_clkout1 = { - .name = "sys_clkout1", - .ops = &clkops_omap2_dflt, - .parent = &osc_sys_ck, - .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, - .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DPLLS */ - -/* CM CLOCKS */ - -static const struct clksel_rate div16_dpll_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 5, .val = 5, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 7, .val = 7, .flags = RATE_IN_343X }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 9, .val = 9, .flags = RATE_IN_343X }, - { .div = 10, .val = 10, .flags = RATE_IN_343X }, - { .div = 11, .val = 11, .flags = RATE_IN_343X }, - { .div = 12, .val = 12, .flags = RATE_IN_343X }, - { .div = 13, .val = 13, .flags = RATE_IN_343X }, - { .div = 14, .val = 14, .flags = RATE_IN_343X }, - { .div = 15, .val = 15, .flags = RATE_IN_343X }, - { .div = 16, .val = 16, .flags = RATE_IN_343X }, - { .div = 0 } -}; - -/* DPLL1 */ -/* MPU clock source */ -/* Type: DPLL */ -static struct dpll_data dpll1_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), - .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, - .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, - .clk_bypass = &dpll1_fck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), - .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), - .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE -}; - -static struct clk dpll1_ck = { - .name = "dpll1_ck", - .ops = &clkops_null, - .parent = &sys_ck, - .dpll_data = &dpll1_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed. - */ -static struct clk dpll1_x2_ck = { - .name = "dpll1_x2_ck", - .ops = &clkops_null, - .parent = &dpll1_ck, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ -static const struct clksel div16_dpll1_x2m2_clksel[] = { - { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* - * Does not exist in the TRM - needed to separate the M2 divider from - * bypass selection in mpu_ck - */ -static struct clk dpll1_x2m2_ck = { - .name = "dpll1_x2m2_ck", - .ops = &clkops_null, - .parent = &dpll1_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), - .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, - .clksel = div16_dpll1_x2m2_clksel, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL2 */ -/* IVA2 clock source */ -/* Type: DPLL */ - -static struct dpll_data dpll2_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), - .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, - .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, - .clk_bypass = &dpll2_fck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), - .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | - (1 << DPLL_LOW_POWER_BYPASS), - .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), - .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE -}; - -static struct clk dpll2_ck = { - .name = "dpll2_ck", - .ops = &clkops_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll2_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll2_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll2_m2x2_clksel[] = { - { .parent = &dpll2_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* - * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT - * or CLKOUTX2. CLKOUT seems most plausible. - */ -static struct clk dpll2_m2_ck = { - .name = "dpll2_m2_ck", - .ops = &clkops_null, - .parent = &dpll2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKSEL2_PLL), - .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, - .clksel = div16_dpll2_m2x2_clksel, - .clkdm_name = "dpll2_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* - * DPLL3 - * Source clock for all interfaces and for some device fclks - * REVISIT: Also supports fast relock bypass - not included below - */ -static struct dpll_data dpll3_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, - .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, - .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), - .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE -}; - -static struct clk dpll3_ck = { - .name = "dpll3_ck", - .ops = &clkops_null, - .parent = &sys_ck, - .dpll_data = &dpll3_dd, - .round_rate = &omap2_dpll_round_rate, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed - */ -static struct clk dpll3_x2_ck = { - .name = "dpll3_x2_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate div31_dpll3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, - { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, - { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, - { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, - { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, - { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, - { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, - { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, - { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, - { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, - { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, - { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, - { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, - { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, - { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, - { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, - { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, - { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, - { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, - { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, - { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, - { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, - { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, - { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, - { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, - { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, - { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, - { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, - { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, - { .div = 0 }, -}; - -static const struct clksel div31_dpll3m2_clksel[] = { - { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, - { .parent = NULL } -}; - -/* DPLL3 output M2 - primary control point for CORE speed */ -static struct clk dpll3_m2_ck = { - .name = "dpll3_m2_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, - .clksel = div31_dpll3m2_clksel, - .clkdm_name = "dpll3_clkdm", - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap3_core_dpll_m2_set_rate, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name = "core_ck", - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll3_m2x2_ck = { - .name = "dpll3_m2x2_ck", - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static const struct clksel div16_dpll3_clksel[] = { - { .parent = &dpll3_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* This virtual clock is the source for dpll3_m3x2_ck */ -static struct clk dpll3_m3_ck = { - .name = "dpll3_m3_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_DIV_DPLL3_MASK, - .clksel = div16_dpll3_clksel, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll3_m3x2_ck = { - .name = "dpll3_m3x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll3_m3_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_core_alwon_ck = { - .name = "emu_core_alwon_ck", - .ops = &clkops_null, - .parent = &dpll3_m3x2_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &followparent_recalc, -}; - -/* DPLL4 */ -/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ -/* Type: DPLL */ -static struct dpll_data dpll4_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), - .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, - .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), - .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE -}; - -static struct clk dpll4_ck = { - .name = "dpll4_ck", - .ops = &clkops_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll4_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_dpll4_set_rate, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed -- - * XXX does this serve any downstream clocks? - */ -static struct clk dpll4_x2_ck = { - .name = "dpll4_x2_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel div16_dpll4_clksel[] = { - { .parent = &dpll4_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* This virtual clock is the source for dpll4_m2x2_ck */ -static struct clk dpll4_m2_ck = { - .name = "dpll4_m2_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), - .clksel_mask = OMAP3430_DIV_96M_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m2x2_ck = { - .name = "dpll4_m2x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m2_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* - * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as - * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: - * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and - * CM_96K_(F)CLK. - */ -static struct clk omap_96m_alwon_fck = { - .name = "omap_96m_alwon_fck", - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk cm_96m_fck = { - .name = "cm_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate omap_96m_dpll_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate omap_96m_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel omap_96m_fck_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, - { .parent = &sys_ck, .rates = omap_96m_sys_rates }, - { .parent = NULL } -}; - -static struct clk omap_96m_fck = { - .name = "omap_96m_fck", - .ops = &clkops_null, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_96M_MASK, - .clksel = omap_96m_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This virtual clock is the source for dpll4_m3x2_ck */ -static struct clk dpll4_m3_ck = { - .name = "dpll4_m3_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_TV_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m3x2_ck = { - .name = "dpll4_m3x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m3_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate omap_54m_d4m3x2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate omap_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel omap_54m_clksel[] = { - { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, - { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, - { .parent = NULL } -}; - -static struct clk omap_54m_fck = { - .name = "omap_54m_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_54M_MASK, - .clksel = omap_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate omap_48m_cm96m_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate omap_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel omap_48m_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, - { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, - { .parent = NULL } -}; - -static struct clk omap_48m_fck = { - .name = "omap_48m_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_48M_MASK, - .clksel = omap_48m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk omap_12m_fck = { - .name = "omap_12m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .fixed_div = 4, - .recalc = &omap2_fixed_divisor_recalc, -}; - -/* This virstual clock is the source for dpll4_m4x2_ck */ -static struct clk dpll4_m4_ck = { - .name = "dpll4_m4_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m4x2_ck = { - .name = "dpll4_m4x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m4_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m5x2_ck */ -static struct clk dpll4_m5_ck = { - .name = "dpll4_m5_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m5x2_ck = { - .name = "dpll4_m5x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m5_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m6x2_ck */ -static struct clk dpll4_m6_ck = { - .name = "dpll4_m6_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_DIV_DPLL4_MASK, - .clksel = div16_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m6x2_ck = { - .name = "dpll4_m6x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m6_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_per_alwon_ck = { - .name = "emu_per_alwon_ck", - .ops = &clkops_null, - .parent = &dpll4_m6x2_ck, - .clkdm_name = "dpll4_clkdm", - .recalc = &followparent_recalc, -}; - -/* DPLL5 */ -/* Supplies 120MHz clock, USIM source clock */ -/* Type: DPLL */ -/* 3430ES2 only */ -static struct dpll_data dpll5_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), - .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, - .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), - .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), - .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), - .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE -}; - -static struct clk dpll5_ck = { - .name = "dpll5_ck", - .ops = &clkops_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll5_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll5_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll5_clksel[] = { - { .parent = &dpll5_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -static struct clk dpll5_m2_ck = { - .name = "dpll5_m2_ck", - .ops = &clkops_null, - .parent = &dpll5_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), - .clksel_mask = OMAP3430ES2_DIV_120M_MASK, - .clksel = div16_dpll5_clksel, - .clkdm_name = "dpll5_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* CM EXTERNAL CLOCK OUTPUTS */ - -static const struct clksel_rate clkout2_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel clkout2_src_clksel[] = { - { .parent = &core_ck, .rates = clkout2_src_core_rates }, - { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, - { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, - { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, - { .parent = NULL } -}; - -static struct clk clkout2_src_ck = { - .name = "clkout2_src_ck", - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP3430_CM_CLKOUT_CTRL, - .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, - .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, - .clksel = clkout2_src_clksel, - .clkdm_name = "core_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate sys_clkout2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 1, .flags = RATE_IN_343X }, - { .div = 4, .val = 2, .flags = RATE_IN_343X }, - { .div = 8, .val = 3, .flags = RATE_IN_343X }, - { .div = 16, .val = 4, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel sys_clkout2_clksel[] = { - { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, - { .parent = NULL }, -}; - -static struct clk sys_clkout2 = { - .name = "sys_clkout2", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, - .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, - .clksel = sys_clkout2_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* CM OUTPUT CLOCKS */ - -static struct clk corex2_fck = { - .name = "corex2_fck", - .ops = &clkops_null, - .parent = &dpll3_m2x2_ck, - .recalc = &followparent_recalc, -}; - -/* DPLL power domain clock controls */ - -static const struct clksel_rate div4_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 0 } -}; - -static const struct clksel div4_core_clksel[] = { - { .parent = &core_ck, .rates = div4_rates }, - { .parent = NULL } -}; - -/* - * REVISIT: Are these in DPLL power domain or CM power domain? docs - * may be inconsistent here? - */ -static struct clk dpll1_fck = { - .name = "dpll1_fck", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mpu_ck = { - .name = "mpu_ck", - .ops = &clkops_null, - .parent = &dpll1_x2m2_ck, - .clkdm_name = "mpu_clkdm", - .recalc = &followparent_recalc, -}; - -/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ -static const struct clksel_rate arm_fck_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 1, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel arm_fck_clksel[] = { - { .parent = &mpu_ck, .rates = arm_fck_rates }, - { .parent = NULL } -}; - -static struct clk arm_fck = { - .name = "arm_fck", - .ops = &clkops_null, - .parent = &mpu_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, - .clksel = arm_fck_clksel, - .clkdm_name = "mpu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* XXX What about neon_clkdm ? */ - -/* - * REVISIT: This clock is never specifically defined in the 3430 TRM, - * although it is referenced - so this is a guess - */ -static struct clk emu_mpu_alwon_ck = { - .name = "emu_mpu_alwon_ck", - .ops = &clkops_null, - .parent = &mpu_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll2_fck = { - .name = "dpll2_fck", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk iva2_ck = { - .name = "iva2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll2_m2_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .clkdm_name = "iva2_clkdm", - .recalc = &followparent_recalc, -}; - -/* Common interface clocks */ - -static const struct clksel div2_core_clksel[] = { - { .parent = &core_ck, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk l3_ick = { - .name = "l3_ick", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_L3_MASK, - .clksel = div2_core_clksel, - .clkdm_name = "core_l3_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel div2_l3_clksel[] = { - { .parent = &l3_ick, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk l4_ick = { - .name = "l4_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_L4_MASK, - .clksel = div2_l3_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, - -}; - -static const struct clksel div2_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk rm_ick = { - .name = "rm_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_RM_MASK, - .clksel = div2_l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* GFX power domain */ - -/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ - -static const struct clksel gfx_l3_clksel[] = { - { .parent = &l3_ick, .rates = gfx_l3_rates }, - { .parent = NULL } -}; - -/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ -static struct clk gfx_l3_ck = { - .name = "gfx_l3_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gfx_l3_fck = { - .name = "gfx_l3_fck", - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_l3_clksel, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gfx_l3_ick = { - .name = "gfx_l3_ick", - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg1_ck = { - .name = "gfx_cg1_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES1_EN_2D_SHIFT, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg2_ck = { - .name = "gfx_cg2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES1_EN_3D_SHIFT, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -/* SGX power domain - 3430ES2 only */ - -static const struct clksel_rate sgx_core_rates[] = { - { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 4, .val = 1, .flags = RATE_IN_343X }, - { .div = 6, .val = 2, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel_rate sgx_96m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 }, -}; - -static const struct clksel sgx_clksel[] = { - { .parent = &core_ck, .rates = sgx_core_rates }, - { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, - { .parent = NULL }, -}; - -static struct clk sgx_fck = { - .name = "sgx_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, - .clksel = sgx_clksel, - .clkdm_name = "sgx_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk sgx_ick = { - .name = "sgx_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, - .clkdm_name = "sgx_clkdm", - .recalc = &followparent_recalc, -}; - -/* CORE power domain */ - -static struct clk d2d_26m_fck = { - .name = "d2d_26m_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk modem_fck = { - .name = "modem_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MODEM_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sad2d_ick = { - .name = "sad2d_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mad2d_ick = { - .name = "mad2d_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP3430_EN_MAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static const struct clksel omap343x_gpt_clksel[] = { - { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = NULL} -}; - -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk cpefuse_fck = { - .name = "cpefuse_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk ts_fck = { - .name = "ts_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_32k_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_TS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_fck = { - .name = "usbtll_fck", - .ops = &clkops_omap2_dflt, - .parent = &dpll5_m2_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE 96M FCLK-derived clocks */ - -static struct clk core_96m_fck = { - .name = "core_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_fck = { - .name = "mmchs_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_fck = { - .name = "mmchs_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name = "mspro_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_fck = { - .name = "mmchs_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_fck = { - .name = "i2c_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name = "i2c_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_fck = { - .name = "i2c_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; - * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. - */ -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel mcbsp_15_clksel[] = { - { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp5_fck = { - .name = "mcbsp_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 5, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, - .clksel = mcbsp_15_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_fck = { - .name = "mcbsp_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_15_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* CORE_48M_FCK-derived clocks */ - -static struct clk core_48m_fck = { - .name = "core_48m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_fck = { - .name = "mcspi_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 4, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_fck = { - .name = "mcspi_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name = "mcspi_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name = "mcspi_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_UART2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_UART1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk fshostusb_fck = { - .name = "fshostusb_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE_12M_FCK based clocks */ - -static struct clk core_12m_fck = { - .name = "core_12m_fck", - .ops = &clkops_null, - .parent = &omap_12m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name = "hdq_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_12m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DPLL3-derived clock */ - -static const struct clksel_rate ssi_ssr_corex2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_clksel[] = { - { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, - { .parent = NULL } -}; - -static struct clk ssi_ssr_fck_3430es1 = { - .name = "ssi_ssr_fck", - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_ssr_fck_3430es2 = { - .name = "ssi_ssr_fck", - .ops = &clkops_omap3430es2_ssi_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_sst_fck_3430es1 = { - .name = "ssi_sst_fck", - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es1, - .fixed_div = 2, - .recalc = &omap2_fixed_divisor_recalc, -}; - -static struct clk ssi_sst_fck_3430es2 = { - .name = "ssi_sst_fck", - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es2, - .fixed_div = 2, - .recalc = &omap2_fixed_divisor_recalc, -}; - - - -/* CORE_L3_ICK based clocks */ - -/* - * XXX must add clk_enable/clk_disable for these if standard code won't - * handle it - */ -static struct clk core_l3_ick = { - .name = "core_l3_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es1 = { - .name = "hsotgusb_ick", - .ops = &clkops_omap2_dflt, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es2 = { - .name = "hsotgusb_ick", - .ops = &clkops_omap3430es2_hsotgusb_wait, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sdrc_ick = { - .name = "sdrc_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_fck = { - .name = "gpmc_fck", - .ops = &clkops_null, - .parent = &core_l3_ick, - .flags = ENABLE_ON_INIT, /* huh? */ - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -/* SECURITY_L3_ICK based clocks */ - -static struct clk security_l3_ick = { - .name = "security_l3_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name = "pka_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &security_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_PKA_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE_L4_ICK based clocks */ - -static struct clk core_l4_ick = { - .name = "core_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_ick = { - .name = "usbtll_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_ick = { - .name = "mmchs_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* Intersystem Communication Registers - chassis mode only */ -static struct clk icr_ick = { - .name = "icr_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_ICR_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk aes2_ick = { - .name = "aes2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_AES2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sha12_ick = { - .name = "sha12_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SHA12_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk des2_ick = { - .name = "des2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_DES2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_ick = { - .name = "mmchs_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_ick = { - .name = "mmchs_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name = "mspro_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name = "hdq_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_ick = { - .name = "mcspi_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 4, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_ick = { - .name = "mcspi_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name = "mcspi_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_ick = { - .name = "mcspi_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_ick = { - .name = "i2c_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ick = { - .name = "i2c_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_ick = { - .name = "i2c_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name = "uart2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name = "uart1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_ick = { - .name = "gpt11_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_ick = { - .name = "gpt10_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp5_ick = { - .name = "mcbsp_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 5, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp1_ick = { - .name = "mcbsp_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 1, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name = "fac_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name = "mailboxes_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name = "omapctrl_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .recalc = &followparent_recalc, -}; - -/* SSI_L4_ICK based clocks */ - -static struct clk ssi_l4_ick = { - .name = "ssi_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es1 = { - .name = "ssi_ick", - .ops = &clkops_omap2_dflt, - .parent = &ssi_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es2 = { - .name = "ssi_ick", - .ops = &clkops_omap3430es2_ssi_wait, - .parent = &ssi_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* REVISIT: Technically the TRM claims that this is CORE_CLK based, - * but l4_ick makes more sense to me */ - -static const struct clksel usb_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent = NULL }, -}; - -static struct clk usb_l4_ick = { - .name = "usb_l4_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, - .clksel = usb_l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* SECURITY_L4_ICK2 based clocks */ - -static struct clk security_l4_ick2 = { - .name = "security_l4_ick2", - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk aes1_ick = { - .name = "aes1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_AES1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_RNG_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sha11_ick = { - .name = "sha11_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_SHA11_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk des1_ick = { - .name = "des1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_DES1_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DSS */ -static struct clk dss1_alwon_fck_3430es1 = { - .name = "dss1_alwon_fck", - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m4x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss1_alwon_fck_3430es2 = { - .name = "dss1_alwon_fck", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &dpll4_m4x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_fck = { - .name = "dss_tv_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_54m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_96m_fck = { - .name = "dss_96m_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_96m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss2_alwon_fck = { - .name = "dss2_alwon_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS2_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es1 = { - /* Handles both L3 and L4 clocks */ - .name = "dss_ick", - .ops = &clkops_omap2_dflt, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es2 = { - /* Handles both L3 and L4 clocks */ - .name = "dss_ick", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -/* CAM */ - -static struct clk cam_mclk = { - .name = "cam_mclk", - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m5x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_CAM_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { - /* Handles both L3 and L4 clocks */ - .name = "cam_ick", - .ops = &clkops_omap2_dflt, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_CAM_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk csi2_96m_fck = { - .name = "csi2_96m_fck", - .ops = &clkops_omap2_dflt, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_CSI2_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -/* USBHOST - 3430ES2 only */ - -static struct clk usbhost_120m_fck = { - .name = "usbhost_120m_fck", - .ops = &clkops_omap2_dflt, - .parent = &dpll5_m2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_48m_fck = { - .name = "usbhost_48m_fck", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &omap_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_ick = { - /* Handles both L3 and L4 clocks */ - .name = "usbhost_ick", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -/* WKUP */ - -static const struct clksel_rate usim_96m_rates[] = { - { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 8, .val = 5, .flags = RATE_IN_343X }, - { .div = 10, .val = 6, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel_rate usim_120m_rates[] = { - { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 8, .val = 8, .flags = RATE_IN_343X }, - { .div = 16, .val = 9, .flags = RATE_IN_343X }, - { .div = 20, .val = 10, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel usim_clksel[] = { - { .parent = &omap_96m_fck, .rates = usim_96m_rates }, - { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, - { .parent = &sys_ck, .rates = div2_rates }, - { .parent = NULL }, -}; - -/* 3430ES2 only */ -static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, - .clksel = usim_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk wkup_32k_fck = { - .name = "wkup_32k_fck", - .ops = &clkops_null, - .parent = &omap_32k_fck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbck = { - .name = "gpio1_dbck", - .ops = &clkops_omap2_dflt, - .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_fck = { - .name = "wdt2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wkup_l4_ick = { - .name = "wkup_l4_ick", - .ops = &clkops_null, - .parent = &sys_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* 3430ES2 only */ -/* Never specifically named in the TRM, so we have to infer a likely name */ -static struct clk usim_ick = { - .name = "usim_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_ick = { - .name = "wdt2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name = "wdt1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_ick = { - .name = "gpio1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk omap_32ksync_ick = { - .name = "omap_32ksync_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* XXX This clock no longer exists in 3430 TRM rev F */ -static struct clk gpt12_ick = { - .name = "gpt12_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT12_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_ick = { - .name = "gpt1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - - - -/* PER clock domain */ - -static struct clk per_96m_fck = { - .name = "per_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk per_48m_fck = { - .name = "per_48m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_UART3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk per_32k_alwon_fck = { - .name = "per_32k_alwon_fck", - .ops = &clkops_null, - .parent = &omap_32k_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_dbck = { - .name = "gpio6_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_dbck = { - .name = "gpio5_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_dbck = { - .name = "gpio4_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbck = { - .name = "gpio3_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbck = { - .name = "gpio2_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_fck = { - .name = "wdt3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk per_l4_ick = { - .name = "per_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ick = { - .name = "gpio6_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name = "gpio5_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ick = { - .name = "gpio4_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ick = { - .name = "gpio3_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ick = { - .name = "gpio2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ick = { - .name = "wdt3_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name = "uart3_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_UART3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_ick = { - .name = "gpt9_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_ick = { - .name = "gpt8_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_ick = { - .name = "gpt7_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_ick = { - .name = "gpt6_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_ick = { - .name = "gpt5_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_ick = { - .name = "gpt4_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_ick = { - .name = "gpt3_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_ick = { - .name = "gpt2_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_ick = { - .name = "mcbsp_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp3_ick = { - .name = "mcbsp_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp4_ick = { - .name = "mcbsp_ick", - .ops = &clkops_omap2_dflt_wait, - .id = 4, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static const struct clksel mcbsp_234_clksel[] = { - { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp2_fck = { - .name = "mcbsp_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 2, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp3_fck = { - .name = "mcbsp_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 3, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp4_fck = { - .name = "mcbsp_fck", - .ops = &clkops_omap2_dflt_wait, - .id = 4, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* EMU clocks */ - -/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ - -static const struct clksel_rate emu_src_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_per_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_mpu_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 }, -}; - -static const struct clksel emu_src_clksel[] = { - { .parent = &sys_ck, .rates = emu_src_sys_rates }, - { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, - { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, - { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, - { .parent = NULL }, -}; - -/* - * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only - * to switch the source of some of the EMU clocks. - * XXX Are there CLKEN bits for these EMU clks? - */ -static struct clk emu_src_ck = { - .name = "emu_src_ck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_MUX_CTRL_MASK, - .clksel = emu_src_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclk_emu_rates[] = { - { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 6, .val = 6, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel pclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclk_emu_rates }, - { .parent = NULL }, -}; - -static struct clk pclk_fck = { - .name = "pclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, - .clksel = pclk_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclkx2_emu_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 3, .val = 3, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel pclkx2_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, - { .parent = NULL }, -}; - -static struct clk pclkx2_fck = { - .name = "pclkx2_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, - .clksel = pclkx2_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel atclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = div2_rates }, - { .parent = NULL }, -}; - -static struct clk atclk_fck = { - .name = "atclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, - .clksel = atclk_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk traceclk_src_fck = { - .name = "traceclk_src_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, - .clksel = emu_src_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate traceclk_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 2, .val = 2, .flags = RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_343X }, - { .div = 0 }, -}; - -static const struct clksel traceclk_clksel[] = { - { .parent = &traceclk_src_fck, .rates = traceclk_rates }, - { .parent = NULL }, -}; - -static struct clk traceclk_fck = { - .name = "traceclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, - .clksel = traceclk_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* SR clocks */ - -/* SmartReflex fclk (VDD1) */ -static struct clk sr1_fck = { - .name = "sr1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_SR1_SHIFT, - .recalc = &followparent_recalc, -}; - -/* SmartReflex fclk (VDD2) */ -static struct clk sr2_fck = { - .name = "sr2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_SR2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sr_l4_ick = { - .name = "sr_l4_ick", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* SECURE_32K_FCK clocks */ - -static struct clk gpt12_fck = { - .name = "gpt12_fck", - .ops = &clkops_null, - .parent = &secure_32k_fck, - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_fck = { - .name = "wdt1_fck", - .ops = &clkops_null, - .parent = &secure_32k_fck, - .recalc = &followparent_recalc, -}; - - -/* - * clkdev - */ - -static struct omap_clk omap34xx_clks[] = { - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), - CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), - CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), - CLK(NULL, "sys_ck", &sys_ck, CK_343X), - CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), - CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), - CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), - CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), - CLK(NULL, "core_ck", &core_ck, CK_343X), - CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), - CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), - CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), - CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), - CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), - CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), - CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), - CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), - CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), - CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), - CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), - CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), - CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), - CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), - CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), - CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), - CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), - CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), - CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), - CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), - CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), - CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), - CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), - CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), - CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), - CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), - CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), - CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), - CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), - CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), - CLK(NULL, "arm_fck", &arm_fck, CK_343X), - CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), - CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), - CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), - CLK(NULL, "l3_ick", &l3_ick, CK_343X), - CLK(NULL, "l4_ick", &l4_ick, CK_343X), - CLK(NULL, "rm_ick", &rm_ick, CK_343X), - CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), - CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), - CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), - CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), - CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), - CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_343X), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), - CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), - CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), - CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), - CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), - CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), - CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), - CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), - CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), - CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), - CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), - CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), - CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), - CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), - CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), - CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), - CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), - CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), - CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), - CLK(NULL, "pka_ick", &pka_ick, CK_343X), - CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), - CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), - CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), - CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), - CLK(NULL, "des2_ick", &des2_ick, CK_343X), - CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), - CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), - CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), - CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), - CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), - CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), - CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), - CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), - CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), - CLK("omap_rng", "ick", &rng_ick, CK_343X), - CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), - CLK(NULL, "des1_ick", &des1_ick, CK_343X), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), - CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), - CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), - CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), - CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), - CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), - CLK(NULL, "cam_ick", &cam_ick, CK_343X), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), - CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), - CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), - CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), - CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), - CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), - CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), - CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), - CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), - CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), - CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), - CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), - CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), - CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), - CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), - CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), - CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), - CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), - CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), - CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), - CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), - CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), - CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), - CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), - CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), - CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), - CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), - CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), - CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), -}; - - -int __init omap2_clk_init(void) -{ - /* struct prcm_config *prcm; */ - struct omap_clk *c; - /* u32 clkrate; */ - u32 cpu_clkflg; - - if (cpu_is_omap34xx()) { - cpu_mask = RATE_IN_343X; - cpu_clkflg = CK_343X; - - /* - * Update this if there are further clock changes between ES2 - * and production parts - */ - if (omap_rev() == OMAP3430_REV_ES1_0) { - /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ - cpu_clkflg |= CK_3430ES1; - } else { - cpu_mask |= RATE_IN_3430ES2; - cpu_clkflg |= CK_3430ES2; - } - } - - clk_init(&omap2_clk_functions); - - for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) - clk_preinit(c->lk.clk); - - for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* REVISIT: Not yet ready for OMAP3 */ -#if 0 - /* Check the MPU rate set by bootloader */ - clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - if (prcm->dpll_speed <= clkrate) - break; - } - curr_prcm_set = prcm; -#endif - - recalculate_root_clocks(); - - printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - /* - * Lock DPLL5 and put it in autoidle. - */ - if (omap_rev() >= OMAP3430_REV_ES2_0) - omap3_clk_lock_dpll5(); - - /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); - - return 0; -} diff --git a/trunk/arch/arm/mach-omap2/clock44xx.c b/trunk/arch/arm/mach-omap2/clock44xx.c deleted file mode 100644 index e370868a79a8..000000000000 --- a/trunk/arch/arm/mach-omap2/clock44xx.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * OMAP4-specific clock framework functions - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Rajendra Nayak (rnayak@ti.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include "clock.h" - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -}; - -const struct clkops clkops_noncore_dpll_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, -}; - -void omap2_clk_prepare_for_reboot(void) -{ - return; -} diff --git a/trunk/arch/arm/mach-omap2/clock44xx.h b/trunk/arch/arm/mach-omap2/clock44xx.h deleted file mode 100644 index 59b9ced4daa1..000000000000 --- a/trunk/arch/arm/mach-omap2/clock44xx.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * OMAP4 clock function prototypes and macros - * - * Copyright (C) 2009 Texas Instruments, Inc. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H - -#define OMAP4430_MAX_DPLL_MULT 2048 -#define OMAP4430_MAX_DPLL_DIV 128 - -extern const struct clkops clkops_noncore_dpll_ops; - -#endif diff --git a/trunk/arch/arm/mach-omap2/clock44xx_data.c b/trunk/arch/arm/mach-omap2/clock44xx_data.c deleted file mode 100644 index 2210e227d78a..000000000000 --- a/trunk/arch/arm/mach-omap2/clock44xx_data.c +++ /dev/null @@ -1,2766 +0,0 @@ -/* - * OMAP4 Clock data - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include - -#include "clock.h" -#include "clock44xx.h" -#include "cm.h" -#include "cm-regbits-44xx.h" -#include "prm.h" -#include "prm-regbits-44xx.h" - -/* Root clocks */ - -static struct clk extalt_clkin_ck = { - .name = "extalt_clkin_ck", - .rate = 59000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk pad_clks_ck = { - .name = "pad_clks_ck", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk pad_slimbus_core_clks_ck = { - .name = "pad_slimbus_core_clks_ck", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk secure_32k_clk_src_ck = { - .name = "secure_32k_clk_src_ck", - .rate = 32768, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk slimbus_clk = { - .name = "slimbus_clk", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk sys_32k_ck = { - .name = "sys_32k_ck", - .rate = 32768, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk virt_12000000_ck = { - .name = "virt_12000000_ck", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk virt_13000000_ck = { - .name = "virt_13000000_ck", - .ops = &clkops_null, - .rate = 13000000, -}; - -static struct clk virt_16800000_ck = { - .name = "virt_16800000_ck", - .ops = &clkops_null, - .rate = 16800000, -}; - -static struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, -}; - -static struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, -}; - -static struct clk virt_27000000_ck = { - .name = "virt_27000000_ck", - .ops = &clkops_null, - .rate = 27000000, -}; - -static struct clk virt_38400000_ck = { - .name = "virt_38400000_ck", - .ops = &clkops_null, - .rate = 38400000, -}; - -static const struct clksel_rate div_1_0_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_2_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_3_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_4_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_5_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_6_rates[] = { - { .div = 1, .val = 6, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_7_rates[] = { - { .div = 1, .val = 7, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, - { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, - { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, - { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, - { .parent = NULL }, -}; - -static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .rate = 38400000, - .clksel = sys_clkin_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_SYS_CLKSEL, - .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk utmi_phy_clkout_ck = { - .name = "utmi_phy_clkout_ck", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk xclk60mhsp1_ck = { - .name = "xclk60mhsp1_ck", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk xclk60mhsp2_ck = { - .name = "xclk60mhsp2_ck", - .rate = 12000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -static struct clk xclk60motg_ck = { - .name = "xclk60motg_ck", - .rate = 60000000, - .ops = &clkops_null, - .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, -}; - -/* Module clocks and DPLL outputs */ - -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel dpll_sys_ref_clk_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_sys_ref_clk = { - .name = "dpll_sys_ref_clk", - .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, - .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel abe_dpll_refclk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk abe_dpll_refclk_mux_ck = { - .name = "abe_dpll_refclk_mux_ck", - .parent = &dpll_sys_ref_clk, - .clksel = abe_dpll_refclk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_ABE */ -static struct dpll_data dpll_abe_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_abe_ck = { - .name = "dpll_abe_ck", - .parent = &abe_dpll_refclk_mux_ck, - .dpll_data = &dpll_abe_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_abe_m2x2_ck = { - .name = "dpll_abe_m2x2_ck", - .parent = &dpll_abe_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk abe_24m_fclk = { - .name = "abe_24m_fclk", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel abe_clk_div[] = { - { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk abe_clk = { - .name = "abe_clk", - .parent = &dpll_abe_m2x2_ck, - .clksel = abe_clk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_ABE, - .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel aess_fclk_div[] = { - { .parent = &abe_clk, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk aess_fclk = { - .name = "aess_fclk", - .parent = &abe_clk, - .clksel = aess_fclk_div, - .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 3, .val = 2, .flags = RATE_IN_4430 }, - { .div = 4, .val = 3, .flags = RATE_IN_4430 }, - { .div = 5, .val = 4, .flags = RATE_IN_4430 }, - { .div = 6, .val = 5, .flags = RATE_IN_4430 }, - { .div = 7, .val = 6, .flags = RATE_IN_4430 }, - { .div = 8, .val = 7, .flags = RATE_IN_4430 }, - { .div = 9, .val = 8, .flags = RATE_IN_4430 }, - { .div = 10, .val = 9, .flags = RATE_IN_4430 }, - { .div = 11, .val = 10, .flags = RATE_IN_4430 }, - { .div = 12, .val = 11, .flags = RATE_IN_4430 }, - { .div = 13, .val = 12, .flags = RATE_IN_4430 }, - { .div = 14, .val = 13, .flags = RATE_IN_4430 }, - { .div = 15, .val = 14, .flags = RATE_IN_4430 }, - { .div = 16, .val = 15, .flags = RATE_IN_4430 }, - { .div = 17, .val = 16, .flags = RATE_IN_4430 }, - { .div = 18, .val = 17, .flags = RATE_IN_4430 }, - { .div = 19, .val = 18, .flags = RATE_IN_4430 }, - { .div = 20, .val = 19, .flags = RATE_IN_4430 }, - { .div = 21, .val = 20, .flags = RATE_IN_4430 }, - { .div = 22, .val = 21, .flags = RATE_IN_4430 }, - { .div = 23, .val = 22, .flags = RATE_IN_4430 }, - { .div = 24, .val = 23, .flags = RATE_IN_4430 }, - { .div = 25, .val = 24, .flags = RATE_IN_4430 }, - { .div = 26, .val = 25, .flags = RATE_IN_4430 }, - { .div = 27, .val = 26, .flags = RATE_IN_4430 }, - { .div = 28, .val = 27, .flags = RATE_IN_4430 }, - { .div = 29, .val = 28, .flags = RATE_IN_4430 }, - { .div = 30, .val = 29, .flags = RATE_IN_4430 }, - { .div = 31, .val = 30, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel dpll_abe_m3_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_abe_m3_ck = { - .name = "dpll_abe_m3_ck", - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m3_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk core_hsd_byp_clk_mux_ck = { - .name = "core_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, - .clksel = core_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_core_m6_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m6_ck = { - .name = "dpll_core_m6_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dbgclk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk dbgclk_mux_ck = { - .name = "dbgclk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_core_m2_ck = { - .name = "dpll_core_m2_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk ddrphy_ck = { - .name = "ddrphy_ck", - .parent = &dpll_core_m2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_core_m5_ck = { - .name = "dpll_core_m5_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk div_core_ck = { - .name = "div_core_ck", - .parent = &dpll_core_m5_ck, - .clksel = div_core_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div4_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 8, .val = 3, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, - { .parent = NULL }, -}; - -static struct clk div_iva_hs_clk = { - .name = "div_iva_hs_clk", - .parent = &dpll_core_m5_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk div_mpu_hs_clk = { - .name = "div_mpu_hs_clk", - .parent = &dpll_core_m5_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_core_m4_ck = { - .name = "dpll_core_m4_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dll_clk_div_ck = { - .name = "dll_clk_div_ck", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_abe_m2_ck = { - .name = "dpll_abe_m2_ck", - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m3_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_core_m3_ck = { - .name = "dpll_core_m3_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_core_m7_ck = { - .name = "dpll_core_m7_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m6_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk iva_hsd_byp_clk_mux_ck = { - .name = "iva_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_IVA */ -static struct dpll_data dpll_iva_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_iva_ck = { - .name = "dpll_iva_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_iva_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_iva_m4_div[] = { - { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_iva_m4_ck = { - .name = "dpll_iva_m4_ck", - .parent = &dpll_iva_ck, - .clksel = dpll_iva_m4_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_iva_m5_ck = { - .name = "dpll_iva_m5_ck", - .parent = &dpll_iva_ck, - .clksel = dpll_iva_m4_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .parent = &dpll_mpu_ck, - .clksel = dpll_mpu_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk per_hs_clk_div_ck = { - .name = "per_hs_clk_div_ck", - .parent = &dpll_abe_m3_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk per_hsd_byp_clk_mux_ck = { - .name = "per_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, - .clksel = per_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m2x2_ck = { - .name = "dpll_per_m2x2_ck", - .parent = &dpll_per_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m3_ck = { - .name = "dpll_per_m3_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m4_ck = { - .name = "dpll_per_m4_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m5_ck = { - .name = "dpll_per_m5_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m6_ck = { - .name = "dpll_per_m6_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_per_m7_ck = { - .name = "dpll_per_m7_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_UNIPRO */ -static struct dpll_data dpll_unipro_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &dpll_sys_ref_clk, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_unipro_ck = { - .name = "dpll_unipro_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_unipro_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_unipro_m2x2_div[] = { - { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_unipro_m2x2_ck = { - .name = "dpll_unipro_m2x2_ck", - .parent = &dpll_unipro_ck, - .clksel = dpll_unipro_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk usb_hs_clk_div_ck = { - .name = "usb_hs_clk_div_ck", - .parent = &dpll_abe_m3_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* DPLL_USB */ -static struct dpll_data dpll_usb_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, - .clk_bypass = &usb_hs_clk_div_ck, - .clk_ref = &dpll_sys_ref_clk, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, - .min_divider = 1, -}; - - -static struct clk dpll_usb_ck = { - .name = "dpll_usb_ck", - .parent = &dpll_sys_ref_clk, - .dpll_data = &dpll_usb_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk dpll_usb_clkdcoldo_ck = { - .name = "dpll_usb_clkdcoldo_ck", - .parent = &dpll_usb_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel dpll_usb_m2_div[] = { - { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_usb_m2_ck = { - .name = "dpll_usb_m2_ck", - .parent = &dpll_usb_ck, - .clksel = dpll_usb_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel ducati_clk_mux_sel[] = { - { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk ducati_clk_mux_ck = { - .name = "ducati_clk_mux_ck", - .parent = &div_core_ck, - .clksel = ducati_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk func_12m_fclk = { - .name = "func_12m_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk func_24m_clk = { - .name = "func_24m_clk", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk func_24mc_fclk = { - .name = "func_24mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div2_4to8_rates[] = { - { .div = 4, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel func_48m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, - { .parent = NULL }, -}; - -static struct clk func_48m_fclk = { - .name = "func_48m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_48m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk func_48mc_fclk = { - .name = "func_48mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div2_2to4_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 4, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; - -static struct clk func_64m_fclk = { - .name = "func_64m_fclk", - .parent = &dpll_per_m4_ck, - .clksel = func_64m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_96m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; - -static struct clk func_96m_fclk = { - .name = "func_96m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_96m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel hsmmc6_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk hsmmc6_fclk = { - .name = "hsmmc6_fclk", - .parent = &func_64m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div2_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel init_60m_fclk_div[] = { - { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, - { .parent = NULL }, -}; - -static struct clk init_60m_fclk = { - .name = "init_60m_fclk", - .parent = &dpll_usb_m2_ck, - .clksel = init_60m_fclk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel l3_div_div[] = { - { .parent = &div_core_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk l3_div_ck = { - .name = "l3_div_ck", - .parent = &div_core_ck, - .clksel = l3_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L3_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel l4_div_div[] = { - { .parent = &l3_div_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk l4_div_ck = { - .name = "l4_div_ck", - .parent = &l3_div_ck, - .clksel = l4_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L4_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk lp_clk_div_ck = { - .name = "lp_clk_div_ck", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel l4_wkup_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk l4_wkup_clk_mux_ck = { - .name = "l4_wkup_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = l4_wkup_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel per_abe_nc_fclk_div[] = { - { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk per_abe_nc_fclk = { - .name = "per_abe_nc_fclk", - .parent = &dpll_abe_m2_ck, - .clksel = per_abe_nc_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel mcasp2_fclk_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk mcasp2_fclk = { - .name = "mcasp2_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk mcasp3_fclk = { - .name = "mcasp3_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk ocp_abe_iclk = { - .name = "ocp_abe_iclk", - .parent = &aess_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk per_abe_24m_fclk = { - .name = "per_abe_24m_fclk", - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel pmd_stm_clock_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk pmd_stm_clock_mux_ck = { - .name = "pmd_stm_clock_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk pmd_trace_clk_mux_ck = { - .name = "pmd_trace_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static struct clk syc_clk_div_ck = { - .name = "syc_clk_div_ck", - .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, - .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -/* Leaf clocks controlled by modules */ - -static struct clk aes1_ck = { - .name = "aes1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aes2_ck = { - .name = "aes2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aess_ck = { - .name = "aess_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &aess_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk cust_efuse_ck = { - .name = "cust_efuse_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk des3des_ck = { - .name = "des3des_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel dmic_sync_mux_sel[] = { - { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, - { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, - { .parent = &func_24m_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk dmic_sync_mux_ck = { - .name = "dmic_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_dmic_abe_gfclk into dmic_ck */ -static struct clk dmic_ck = { - .name = "dmic_ck", - .parent = &dmic_sync_mux_ck, - .clksel = func_dmic_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk dss_ck = { - .name = "dss_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_dss_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk ducati_ck = { - .name = "ducati_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif1_ck = { - .name = "emif1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif2_ck = { - .name = "emif2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -/* Merged fdif_fclk into fdif_ck */ -static struct clk fdif_ck = { - .name = "fdif_ck", - .parent = &dpll_per_m4_ck, - .clksel = fdif_fclk_div, - .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "iss_clkdm", -}; - -static const struct clksel per_sgx_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk per_sgx_fclk = { - .name = "per_sgx_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged sgx_clk_mux into gfx_ck */ -static struct clk gfx_ck = { - .name = "gfx_ck", - .parent = &dpll_core_m7_ck, - .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", -}; - -static struct clk gpio1_ck = { - .name = "gpio1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ck = { - .name = "gpio2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ck = { - .name = "gpio3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ck = { - .name = "gpio4_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ck = { - .name = "gpio5_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ck = { - .name = "gpio6_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_ck = { - .name = "gpmc_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_2_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel dmt1_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged dmt1_clk_mux into gptimer1_ck */ -static struct clk gptimer1_ck = { - .name = "gptimer1_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* Merged cm2_dm10_mux into gptimer10_ck */ -static struct clk gptimer10_ck = { - .name = "gptimer10_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm11_mux into gptimer11_ck */ -static struct clk gptimer11_ck = { - .name = "gptimer11_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm2_mux into gptimer2_ck */ -static struct clk gptimer2_ck = { - .name = "gptimer2_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm3_mux into gptimer3_ck */ -static struct clk gptimer3_ck = { - .name = "gptimer3_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm4_mux into gptimer4_ck */ -static struct clk gptimer4_ck = { - .name = "gptimer4_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged timer5_sync_mux into gptimer5_ck */ -static struct clk gptimer5_ck = { - .name = "gptimer5_ck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer6_sync_mux into gptimer6_ck */ -static struct clk gptimer6_ck = { - .name = "gptimer6_ck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer7_sync_mux into gptimer7_ck */ -static struct clk gptimer7_ck = { - .name = "gptimer7_ck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer8_sync_mux into gptimer8_ck */ -static struct clk gptimer8_ck = { - .name = "gptimer8_ck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged cm2_dm9_mux into gptimer9_ck */ -static struct clk gptimer9_ck = { - .name = "gptimer9_ck", - .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk hdq1w_ck = { - .name = "hdq1w_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, -}; - -/* Merged hsi_fclk into hsi_ck */ -static struct clk hsi_ck = { - .name = "hsi_ck", - .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, - .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk i2c1_ck = { - .name = "i2c1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ck = { - .name = "i2c2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_ck = { - .name = "i2c3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c4_ck = { - .name = "i2c4_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk iss_ck = { - .name = "iss_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "iss_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk ivahd_ck = { - .name = "ivahd_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5_ck, - .recalc = &followparent_recalc, -}; - -static struct clk keyboard_ck = { - .name = "keyboard_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_instr_interconnect_ck = { - .name = "l3_instr_interconnect_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_interconnect_3_ck = { - .name = "l3_interconnect_3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp_sync_mux_ck = { - .name = "mcasp_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcasp_abe_gfclk into mcasp_ck */ -static struct clk mcasp_ck = { - .name = "mcasp_ck", - .parent = &mcasp_sync_mux_ck, - .clksel = func_mcasp_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp1_sync_mux_ck = { - .name = "mcbsp1_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp1_gfclk into mcbsp1_ck */ -static struct clk mcbsp1_ck = { - .name = "mcbsp1_ck", - .parent = &mcbsp1_sync_mux_ck, - .clksel = func_mcbsp1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp2_sync_mux_ck = { - .name = "mcbsp2_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp2_gfclk into mcbsp2_ck */ -static struct clk mcbsp2_ck = { - .name = "mcbsp2_ck", - .parent = &mcbsp2_sync_mux_ck, - .clksel = func_mcbsp2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp3_sync_mux_ck = { - .name = "mcbsp3_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp3_gfclk into mcbsp3_ck */ -static struct clk mcbsp3_ck = { - .name = "mcbsp3_ck", - .parent = &mcbsp3_sync_mux_ck, - .clksel = func_mcbsp3_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp4_sync_mux_ck = { - .name = "mcbsp4_sync_mux_ck", - .parent = &func_96m_fclk, - .clksel = mcasp2_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged per_mcbsp4_gfclk into mcbsp4_ck */ -static struct clk mcbsp4_ck = { - .name = "mcbsp4_ck", - .parent = &mcbsp4_sync_mux_ck, - .clksel = per_mcbsp4_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk mcspi1_ck = { - .name = "mcspi1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ck = { - .name = "mcspi2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_ck = { - .name = "mcspi3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_ck = { - .name = "mcspi4_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -/* Merged hsmmc1_fclk into mmc1_ck */ -static struct clk mmc1_ck = { - .name = "mmc1_ck", - .parent = &func_64m_fclk, - .clksel = hsmmc6_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -/* Merged hsmmc2_fclk into mmc2_ck */ -static struct clk mmc2_ck = { - .name = "mmc2_ck", - .parent = &func_64m_fclk, - .clksel = hsmmc6_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, - .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk mmc3_ck = { - .name = "mmc3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc4_ck = { - .name = "mmc4_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc5_ck = { - .name = "mmc5_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ocp_wp1_ck = { - .name = "ocp_wp1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk pdm_ck = { - .name = "pdm_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk pkaeip29_ck = { - .name = "pkaeip29_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ck = { - .name = "rng_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sha2md51_ck = { - .name = "sha2md51_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sl2_ck = { - .name = "sl2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_ck = { - .name = "slimbus1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &ocp_abe_iclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_ck = { - .name = "slimbus2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sr_core_ck = { - .name = "sr_core_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sr_iva_ck = { - .name = "sr_iva_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sr_mpu_ck = { - .name = "sr_mpu_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk tesla_ck = { - .name = "tesla_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ck = { - .name = "uart1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ck = { - .name = "uart2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ck = { - .name = "uart3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart4_ck = { - .name = "uart4_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk unipro1_ck = { - .name = "unipro1_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_ck = { - .name = "usb_host_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_fs_ck = { - .name = "usb_host_fs_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_ck = { - .name = "usb_otg_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_ck = { - .name = "usb_tll_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usbphyocp2scp_ck = { - .name = "usbphyocp2scp_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_ck = { - .name = "usim_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_ck = { - .name = "wdt2_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ck = { - .name = "wdt3_ck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -/* Remaining optional clocks */ -static const struct clksel otg_60m_gfclk_sel[] = { - { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, - { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk otg_60m_gfclk_ck = { - .name = "otg_60m_gfclk_ck", - .parent = &utmi_phy_clkout_ck, - .clksel = otg_60m_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_60M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel_rate div2_14to18_rates[] = { - { .div = 14, .val = 0, .flags = RATE_IN_4430 }, - { .div = 18, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, - { .parent = NULL }, -}; - -static struct clk usim_fclk = { - .name = "usim_fclk", - .parent = &dpll_per_m4_ck, - .clksel = usim_fclk_div, - .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p1_gfclk_ck = { - .name = "utmi_p1_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p2_gfclk_ck = { - .name = "utmi_p2_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .flags = CLOCK_IN_OMAP4430, -}; - -/* - * clkdev - */ - -static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), - CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), - CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), - CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), - CLK(NULL, "abe_clk", &abe_clk, CK_443X), - CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), - CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), - CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), - CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), - CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), - CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), - CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), - CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), - CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), - CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), - CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), - CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), - CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), - CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), - CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), - CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), - CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), - CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), - CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), - CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "aes1_ck", &aes1_ck, CK_443X), - CLK(NULL, "aes2_ck", &aes2_ck, CK_443X), - CLK(NULL, "aess_ck", &aess_ck, CK_443X), - CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X), - CLK(NULL, "des3des_ck", &des3des_ck, CK_443X), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_ck", &dmic_ck, CK_443X), - CLK(NULL, "dss_ck", &dss_ck, CK_443X), - CLK(NULL, "ducati_ck", &ducati_ck, CK_443X), - CLK(NULL, "emif1_ck", &emif1_ck, CK_443X), - CLK(NULL, "emif2_ck", &emif2_ck, CK_443X), - CLK(NULL, "fdif_ck", &fdif_ck, CK_443X), - CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), - CLK(NULL, "gfx_ck", &gfx_ck, CK_443X), - CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X), - CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X), - CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X), - CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X), - CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X), - CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X), - CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X), - CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X), - CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X), - CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X), - CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X), - CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X), - CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X), - CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X), - CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X), - CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X), - CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X), - CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X), - CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X), - CLK(NULL, "hsi_ck", &hsi_ck, CK_443X), - CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X), - CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X), - CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X), - CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X), - CLK(NULL, "iss_ck", &iss_ck, CK_443X), - CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X), - CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X), - CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X), - CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X), - CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X), - CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X), - CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X), - CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X), - CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X), - CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X), - CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X), - CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X), - CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X), - CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X), - CLK(NULL, "pdm_ck", &pdm_ck, CK_443X), - CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X), - CLK("omap_rng", "ick", &rng_ck, CK_443X), - CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X), - CLK(NULL, "sl2_ck", &sl2_ck, CK_443X), - CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X), - CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X), - CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X), - CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X), - CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X), - CLK(NULL, "tesla_ck", &tesla_ck, CK_443X), - CLK(NULL, "uart1_ck", &uart1_ck, CK_443X), - CLK(NULL, "uart2_ck", &uart2_ck, CK_443X), - CLK(NULL, "uart3_ck", &uart3_ck, CK_443X), - CLK(NULL, "uart4_ck", &uart4_ck, CK_443X), - CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X), - CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X), - CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X), - CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X), - CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK("omap_wdt", "fck", &wdt2_ck, CK_443X), - CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X), - CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), - CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), -}; - -int __init omap2_clk_init(void) -{ - /* struct prcm_config *prcm; */ - struct omap_clk *c; - /* u32 clkrate; */ - u32 cpu_clkflg; - - if (cpu_is_omap44xx()) { - cpu_mask = RATE_IN_4430; - cpu_clkflg = CK_443X; - } - - clk_init(&omap2_clk_functions); - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - clk_preinit(c->lk.clk); - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - /* TODO - omap2_init_clk_clkdm(c->lk.clk); - */ - } - - recalculate_root_clocks(); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - return 0; -} diff --git a/trunk/arch/arm/mach-omap2/clock_common_data.c b/trunk/arch/arm/mach-omap2/clock_common_data.c deleted file mode 100644 index f69096b88cdb..000000000000 --- a/trunk/arch/arm/mach-omap2/clock_common_data.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/clock_common_data.c - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains clock data that is common to both the OMAP2xxx and - * OMAP3xxx clock definition files. - */ - -#include "clock.h" - -/* clksel_rate data common to 24xx/343x */ -const struct clksel_rate gpt_32k_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -const struct clksel_rate gpt_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -const struct clksel_rate gfx_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, - { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, - { .div = 0 } -}; - diff --git a/trunk/arch/arm/mach-omap2/clockdomain.c b/trunk/arch/arm/mach-omap2/clockdomain.c index 1a45ed1e8ba1..fcd82320a6a3 100644 --- a/trunk/arch/arm/mach-omap2/clockdomain.c +++ b/trunk/arch/arm/mach-omap2/clockdomain.c @@ -2,7 +2,7 @@ * OMAP2/3 clockdomain framework functions * * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2008 Nokia Corporation * * Written by Paul Walmsley and Jouni Högander * @@ -10,7 +10,9 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#undef DEBUG +#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN +# define DEBUG +#endif #include #include diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h deleted file mode 100644 index 0e67f75aa35c..000000000000 --- a/trunk/arch/arm/mach-omap2/cm-regbits-44xx.h +++ /dev/null @@ -1,1474 +0,0 @@ -/* - * OMAP44xx Clock Management register bits - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H -#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H - -#include "cm.h" - - -/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_ABE_DYNDEP_SHIFT (1 << 3) -#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP - */ -#define OMAP4430_ABE_STATDEP_SHIFT (1 << 3) -#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ALWONCORE_DYNDEP_SHIFT (1 << 16) -#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_ALWONCORE_STATDEP_SHIFT (1 << 16) -#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) - -/* - * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU - */ -#define OMAP4430_AUTO_DPLL_MODE_SHIFT (1 << 0) -#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_CEFUSE_DYNDEP_SHIFT (1 << 17) -#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_CEFUSE_STATDEP_SHIFT (1 << 17) -#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT (1 << 13) -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT (1 << 12) -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT (1 << 12) -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT (1 << 13) -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT (1 << 12) -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT (1 << 13) -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT (1 << 14) -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) - -/* Used by CM_DUCATI_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT (1 << 15) -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT (1 << 20) -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT (1 << 26) -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT (1 << 21) -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT (1 << 27) -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT (1 << 31) -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT (1 << 13) -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT (1 << 12) -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT (1 << 28) -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT (1 << 29) -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT (1 << 16) -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT (1 << 17) -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT (1 << 18) -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT (1 << 19) -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) - -/* Used by CM_IVAHD_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT (1 << 14) -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) - -/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_SDMA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT (1 << 12) -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) - -/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT (1 << 16) -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT (1 << 17) -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT (1 << 18) -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT (1 << 19) -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT (1 << 25) -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT (1 << 20) -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT (1 << 21) -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT (1 << 22) -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) - -/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT (1 << 24) -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) - -/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT (1 << 9) -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_TESLA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT (1 << 8) -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT (1 << 22) -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT (1 << 23) -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT (1 << 24) -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT (1 << 15) -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT (1 << 10) -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT (1 << 30) -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT (1 << 25) -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT (1 << 11) -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) - -/* - * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL - */ -#define OMAP4430_CLKSEL_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) - -/* - * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, - * CM_CLKSEL_USB_60MHZ - */ -#define OMAP4430_CLKSEL_0_0_SHIFT (1 << 0) -#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) - -/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ -#define OMAP4430_CLKSEL_0_1_SHIFT (1 << 0) -#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) - -/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ -#define OMAP4430_CLKSEL_24_25_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ -#define OMAP4430_CLKSEL_60M_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) - -/* Used by CM1_ABE_AESS_CLKCTRL */ -#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) - -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_CORE_SHIFT (1 << 0) -#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) - -/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_CORE_1_1_SHIFT (1 << 1) -#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) - -/* Used by CM_WKUP_USIM_CLKCTRL */ -#define OMAP4430_CLKSEL_DIV_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) - -/* Used by CM_CAM_FDIF_CLKCTRL */ -#define OMAP4430_CLKSEL_FCLK_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) - -/* Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT (1 << 25) -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) - -/* - * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT (1 << 26) -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) - -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_L3_SHIFT (1 << 4) -#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) - -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT (1 << 2) -#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) - -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ -#define OMAP4430_CLKSEL_L4_SHIFT (1 << 8) -#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) - -/* Used by CM_CLKSEL_ABE */ -#define OMAP4430_CLKSEL_OPP_SHIFT (1 << 0) -#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_PER_192M_SHIFT (1 << 25) -#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT (1 << 27) -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) - -/* - * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, - * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_SOURCE_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) - -/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_CLKSEL_UTMI_P1_SHIFT (1 << 24) -#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_CLKSEL_UTMI_P2_SHIFT (1 << 25) -#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) - -/* - * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, - * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, - * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, - * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, - * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE - */ -#define OMAP4430_CLKTRCTRL_SHIFT (1 << 0) -#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT (1 << 0) -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT (1 << 8) -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_D2D_DYNDEP_SHIFT (1 << 18) -#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP4430_D2D_STATDEP_SHIFT (1 << 18) -#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, - * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, - * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, - * CM_SSC_DELTAMSTEP_DPLL_MPU - */ -#define OMAP4430_DELTAMSTEP_SHIFT (1 << 0) -#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_OVERRIDE_SHIFT (1 << 2) -#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) - -/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ -#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT (1 << 0) -#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_RESET_SHIFT (1 << 3) -#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) - -/* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU - */ -#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT (1 << 23) -#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) - -/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT (1 << 20) -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) - -/* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE - */ -#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT (1 << 0) -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) - -/* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE - */ -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) - -/* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE - */ -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) - -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT (1 << 10) -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) - -/* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU - */ -#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT (1 << 0) -#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT (1 << 0) -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) - -/* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU - */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT (1 << 7) -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) - -/* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU - */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT (1 << 8) -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT (1 << 11) -#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT (1 << 3) -#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT (1 << 1) -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) - -/* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU - */ -#define OMAP4430_DPLL_DIV_SHIFT (1 << 0) -#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_DIV_0_7_SHIFT (1 << 0) -#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT (1 << 8) -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) - -/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT (1 << 3) -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_EN_SHIFT (1 << 0) -#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_LPMODE_EN_SHIFT (1 << 10) -#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) - -/* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU - */ -#define OMAP4430_DPLL_MULT_SHIFT (1 << 8) -#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_MULT_USB_SHIFT (1 << 8) -#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_REGM4XEN_SHIFT (1 << 11) -#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) - -/* Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_SD_DIV_SHIFT (1 << 24) -#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_SSC_ACK_SHIFT (1 << 13) -#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT (1 << 14) -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) - -/* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU - */ -#define OMAP4430_DPLL_SSC_EN_SHIFT (1 << 12) -#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_DSS_DYNDEP_SHIFT (1 << 8) -#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) - -/* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP - */ -#define OMAP4430_DSS_STATDEP_SHIFT (1 << 8) -#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_DUCATI_DYNDEP_SHIFT (1 << 0) -#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) - -/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ -#define OMAP4430_DUCATI_STATDEP_SHIFT (1 << 0) -#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_FREQ_UPDATE_SHIFT (1 << 0) -#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_GFX_DYNDEP_SHIFT (1 << 10) -#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_GFX_STATDEP_SHIFT (1 << 10) -#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT (1 << 0) -#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) - -/* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT (1 << 0) -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) - -/* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) - -/* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) - -/* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT (1 << 12) -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT (1 << 0) -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) - -/* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) - -/* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) - -/* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT (1 << 12) -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY - */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT (1 << 0) -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) - -/* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY - */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) - -/* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY - */ -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) - -/* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY - */ -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT (1 << 12) -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE - */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT (1 << 0) -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) - -/* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE - */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT (1 << 5) -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) - -/* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE - */ -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT (1 << 8) -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) - -/* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE - */ -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT (1 << 12) -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL - */ -#define OMAP4430_IDLEST_SHIFT (1 << 16) -#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) - -/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ISS_DYNDEP_SHIFT (1 << 9) -#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) - -/* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_ISS_STATDEP_SHIFT (1 << 9) -#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) - -/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_IVAHD_DYNDEP_SHIFT (1 << 2) -#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP - */ -#define OMAP4430_IVAHD_STATDEP_SHIFT (1 << 2) -#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L3INIT_DYNDEP_SHIFT (1 << 7) -#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_L3INIT_STATDEP_SHIFT (1 << 7) -#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) - -/* - * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_L3_1_DYNDEP_SHIFT (1 << 5) -#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_L3_1_STATDEP_SHIFT (1 << 5) -#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) - -/* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, - * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP - */ -#define OMAP4430_L3_2_DYNDEP_SHIFT (1 << 6) -#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_L3_2_STATDEP_SHIFT (1 << 6) -#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) - -/* Used by CM_L3_1_DYNAMICDEP */ -#define OMAP4430_L4CFG_DYNDEP_SHIFT (1 << 12) -#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP - */ -#define OMAP4430_L4CFG_STATDEP_SHIFT (1 << 12) -#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_L4PER_DYNDEP_SHIFT (1 << 13) -#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_L4PER_STATDEP_SHIFT (1 << 13) -#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L4SEC_DYNDEP_SHIFT (1 << 14) -#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) - -/* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP - */ -#define OMAP4430_L4SEC_STATDEP_SHIFT (1 << 14) -#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_L4WKUP_DYNDEP_SHIFT (1 << 15) -#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) - -/* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_L4WKUP_STATDEP_SHIFT (1 << 15) -#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) - -/* - * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MPU_DYNAMICDEP - */ -#define OMAP4430_MEMIF_DYNDEP_SHIFT (1 << 4) -#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP - */ -#define OMAP4430_MEMIF_STATDEP_SHIFT (1 << 4) -#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU - */ -#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT (1 << 8) -#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU - */ -#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT (1 << 0) -#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL - */ -#define OMAP4430_MODULEMODE_SHIFT (1 << 0) -#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) - -/* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_WKUP_BANDGAP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) - -/* Used by CM_CAM_ISS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) - -/* - * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE - */ -#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) - -/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT (1 << 10) -#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT (1 << 15) -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT (1 << 13) -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT (1 << 14) -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT (1 << 11) -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT (1 << 12) -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) - -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT (1 << 10) -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) - -/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT (1 << 11) -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) - -/* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT (1 << 10) -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_DSS_DSS_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT (1 << 11) -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) - -/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT (1 << 10) -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT (1 << 9) -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT (1 << 10) -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_XCLK_SHIFT (1 << 8) -#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_OVERRIDE_ENABLE_SHIFT (1 << 19) -#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) - -/* Used by CM_CLKSEL_ABE */ -#define OMAP4430_PAD_CLKS_GATE_SHIFT (1 << 8) -#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) - -/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ -#define OMAP4430_PERF_CURRENT_SHIFT (1 << 0) -#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) - -/* - * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, - * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, - * CM_IVA_DVFS_PERF_TESLA - */ -#define OMAP4430_PERF_REQ_SHIFT (1 << 0) -#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT (1 << 0) -#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT (1 << 8) -#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE1_COMPLETED_SHIFT (1 << 0) -#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2A_COMPLETED_SHIFT (1 << 1) -#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2B_COMPLETED_SHIFT (1 << 2) -#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT (1 << 20) -#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT (1 << 22) -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) - -/* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP4430_PRESCAL_SHIFT (1 << 0) -#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) - -/* Used by REVISION_CM2, REVISION_CM1 */ -#define OMAP4430_REV_SHIFT (1 << 0) -#define OMAP4430_REV_MASK BITFIELD(0, 7) - -/* - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE - */ -#define OMAP4430_SAR_MODE_SHIFT (1 << 4) -#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) - -/* Used by CM_SCALE_FCLK */ -#define OMAP4430_SCALE_FCLK_SHIFT (1 << 0) -#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_SDMA_DYNDEP_SHIFT (1 << 11) -#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_SDMA_STATDEP_SHIFT (1 << 11) -#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) - -/* Used by CM_CLKSEL_ABE */ -#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT (1 << 10) -#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) - -/* - * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL - */ -#define OMAP4430_STBYST_SHIFT (1 << 18) -#define OMAP4430_STBYST_MASK BITFIELD(18, 18) - -/* - * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, - * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU - */ -#define OMAP4430_ST_DPLL_CLK_SHIFT (1 << 0) -#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT (1 << 9) -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) - -/* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU - */ -#define OMAP4430_ST_DPLL_CLKOUT_SHIFT (1 << 9) -#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) - -/* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE - */ -#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT (1 << 9) -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) - -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ -#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT (1 << 11) -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) - -/* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT (1 << 9) -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) - -/* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT (1 << 9) -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) - -/* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT (1 << 9) -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) - -/* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT (1 << 9) -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) - -/* Used by CM_SYS_CLKSEL */ -#define OMAP4430_SYS_CLKSEL_SHIFT (1 << 0) -#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_TESLA_DYNDEP_SHIFT (1 << 1) -#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_TESLA_STATDEP_SHIFT (1 << 1) -#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) - -/* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_WINDOWSIZE_SHIFT (1 << 24) -#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) -#endif diff --git a/trunk/arch/arm/mach-omap2/cm.c b/trunk/arch/arm/mach-omap2/cm.c index 58e4a1c557d8..8eb2dab8c7db 100644 --- a/trunk/arch/arm/mach-omap2/cm.c +++ b/trunk/arch/arm/mach-omap2/cm.c @@ -21,8 +21,6 @@ #include -#include - #include "cm.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" @@ -63,8 +61,9 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) mask = 1 << idlest_shift; /* XXX should be OMAP2 CM */ - omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), - MAX_MODULE_READY_TIME, i); + while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) && + (i++ < MAX_MODULE_READY_TIME)) + udelay(1); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } diff --git a/trunk/arch/arm/mach-omap2/cm.h b/trunk/arch/arm/mach-omap2/cm.h index 90a4086fbdf4..a2fcfcc253cc 100644 --- a/trunk/arch/arm/mach-omap2/cm.h +++ b/trunk/arch/arm/mach-omap2/cm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Clock Management (CM) register definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley * @@ -22,12 +22,6 @@ OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) -#define OMAP44XX_CM1_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) -#define OMAP44XX_CM2_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) - -#include "cm44xx.h" /* * Architecture-specific global CM registers @@ -95,11 +89,6 @@ #define OMAP3430_CM_CLKSEL2_EMU 0x0050 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 -/* CM2.CEFUSE_CM2 register offsets */ - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 /* Clock management domain register get/set */ diff --git a/trunk/arch/arm/mach-omap2/cm44xx.h b/trunk/arch/arm/mach-omap2/cm44xx.h deleted file mode 100644 index c575b9b0c041..000000000000 --- a/trunk/arch/arm/mach-omap2/cm44xx.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * OMAP44xx CM1 & CM2 instance offset macros - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H -#define __ARCH_ARM_MACH_OMAP2_CM44XX_H - - -/* CM1 */ - - -/* CM1.OCP_SOCKET_CM1 register offsets */ -#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) - -/* CM1.CKGEN_CM1 register offsets */ -#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) -#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) -#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) -#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) -#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) -#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) -#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) -#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) -#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) -#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) -#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) -#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) -#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) -#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) -#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) -#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) -#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) -#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) -#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) -#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) -#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) -#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) -#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) -#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) -#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) -#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) -#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) -#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) -#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) -#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) -#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) -#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) -#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) -#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) -#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) -#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) -#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) -#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) -#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) -#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) -#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) - -/* CM1.MPU_CM1 register offsets */ -#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) -#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) -#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) -#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) - -/* CM1.TESLA_CM1 register offsets */ -#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) -#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) -#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) -#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) - -/* CM1.ABE_CM1 register offsets */ -#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) -#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) -#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) -#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) -#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) -#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) -#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) -#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) -#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) -#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) -#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) -#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) -#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) -#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) -#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) - -/* CM1.RESTORE_CM1 register offsets */ -#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) -#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) -#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) -#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) -#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) -#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) -#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) -#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) -#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) -#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) - -/* CM2 */ - - -/* CM2.OCP_SOCKET_CM2 register offsets */ -#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) - -/* CM2.CKGEN_CM2 register offsets */ -#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) -#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) -#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) -#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) -#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) -#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) -#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) -#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) -#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) -#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) -#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) -#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) -#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) -#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) -#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) -#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) -#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) -#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) -#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) -#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) -#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) -#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) -#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) -#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) -#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) -#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) -#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) -#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) -#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) -#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) -#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) -#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) -#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) - -/* CM2.ALWAYS_ON_CM2 register offsets */ -#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) -#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) -#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) -#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) -#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) - -/* CM2.CORE_CM2 register offsets */ -#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) -#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) -#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) -#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) -#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) -#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) -#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) -#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) -#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) -#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) -#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) -#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) -#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) -#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) -#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) -#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) -#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) -#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) -#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) -#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) -#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) -#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) -#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) -#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) -#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) -#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) -#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) -#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) -#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) -#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) -#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) -#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) -#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) -#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) -#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) -#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) -#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) -#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) - -/* CM2.IVAHD_CM2 register offsets */ -#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) -#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) -#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) -#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) -#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) - -/* CM2.CAM_CM2 register offsets */ -#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) -#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) -#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) -#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) -#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) - -/* CM2.DSS_CM2 register offsets */ -#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) -#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) -#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) -#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) -#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) - -/* CM2.GFX_CM2 register offsets */ -#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) -#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) -#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) -#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) - -/* CM2.L3INIT_CM2 register offsets */ -#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) -#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) -#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) -#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) -#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) -#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) -#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) -#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) -#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) -#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) -#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) -#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) -#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) -#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) -#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) -#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) -#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) -#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) - -/* CM2.L4PER_CM2 register offsets */ -#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) -#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) -#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) -#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) -#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) -#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) -#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) -#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) -#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) -#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) -#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) -#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) -#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) -#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) -#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) -#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) -#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) -#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) -#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) -#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) -#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) -#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) -#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) -#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) -#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) -#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) -#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) -#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) -#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) -#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) -#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) -#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) -#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) -#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) -#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) -#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) -#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) -#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) -#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) -#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) -#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) -#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) -#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) -#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) -#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) -#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) - -/* CM2.CEFUSE_CM2 register offsets */ -#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) -#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) - -/* CM2.RESTORE_CM2 register offsets */ -#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) -#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) -#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) -#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) -#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) -#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) -#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) -#endif diff --git a/trunk/arch/arm/mach-omap2/devices.c b/trunk/arch/arm/mach-omap2/devices.c index 18ad93160abb..733d3dcff98b 100644 --- a/trunk/arch/arm/mach-omap2/devices.c +++ b/trunk/arch/arm/mach-omap2/devices.c @@ -27,8 +27,6 @@ #include #include -#include "mux.h" - #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) static struct resource cam_resources[] = { @@ -597,40 +595,27 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, if (cpu_is_omap34xx()) { if (controller_nr == 0) { - omap_mux_init_signal("sdmmc1_clk", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_cmd", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat0", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(N28_3430_MMC1_CLK); + omap_cfg_reg(M27_3430_MMC1_CMD); + omap_cfg_reg(N27_3430_MMC1_DAT0); if (mmc_controller->slots[0].wires == 4 || mmc_controller->slots[0].wires == 8) { - omap_mux_init_signal("sdmmc1_dat1", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat2", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat3", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(N26_3430_MMC1_DAT1); + omap_cfg_reg(N25_3430_MMC1_DAT2); + omap_cfg_reg(P28_3430_MMC1_DAT3); } if (mmc_controller->slots[0].wires == 8) { - omap_mux_init_signal("sdmmc1_dat4", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat5", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat6", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat7", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(P27_3430_MMC1_DAT4); + omap_cfg_reg(P26_3430_MMC1_DAT5); + omap_cfg_reg(R27_3430_MMC1_DAT6); + omap_cfg_reg(R25_3430_MMC1_DAT7); } } if (controller_nr == 1) { /* MMC2 */ - omap_mux_init_signal("sdmmc2_clk", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_cmd", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat0", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AE2_3430_MMC2_CLK); + omap_cfg_reg(AG5_3430_MMC2_CMD); + omap_cfg_reg(AH5_3430_MMC2_DAT0); /* * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed @@ -638,22 +623,15 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, */ if (mmc_controller->slots[0].wires == 4 || mmc_controller->slots[0].wires == 8) { - omap_mux_init_signal("sdmmc2_dat1", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat2", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat3", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AH4_3430_MMC2_DAT1); + omap_cfg_reg(AG4_3430_MMC2_DAT2); + omap_cfg_reg(AF4_3430_MMC2_DAT3); } if (mmc_controller->slots[0].wires == 8) { - omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", - OMAP_PIN_INPUT_PULLUP); + omap_cfg_reg(AE4_3430_MMC2_DAT4); + omap_cfg_reg(AH3_3430_MMC2_DAT5); + omap_cfg_reg(AF3_3430_MMC2_DAT6); + omap_cfg_reg(AE3_3430_MMC2_DAT7); } } diff --git a/trunk/arch/arm/mach-omap2/dpll.c b/trunk/arch/arm/mach-omap2/dpll.c deleted file mode 100644 index f6055b493294..000000000000 --- a/trunk/arch/arm/mach-omap2/dpll.c +++ /dev/null @@ -1,538 +0,0 @@ -/* - * OMAP3/4 - specific DPLL control functions - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Written by Paul Walmsley - * Testing and integration fixes by Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "clock.h" -#include "prm.h" -#include "prm-regbits-34xx.h" -#include "cm.h" -#include "cm-regbits-34xx.h" - -/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ -#define DPLL_AUTOIDLE_DISABLE 0x0 -#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 - -#define MAX_DPLL_WAIT_TRIES 1000000 - - -/** - * omap3_dpll_recalc - recalculate DPLL rate - * @clk: DPLL struct clk - * - * Recalculate and propagate the DPLL rate. - */ -unsigned long omap3_dpll_recalc(struct clk *clk) -{ - return omap2_get_dpll_rate(clk); -} - -/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) -{ - const struct dpll_data *dd; - u32 v; - - dd = clk->dpll_data; - - v = __raw_readl(dd->control_reg); - v &= ~dd->enable_mask; - v |= clken_bits << __ffs(dd->enable_mask); - __raw_writel(v, dd->control_reg); -} - -/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -static int _omap3_wait_dpll_status(struct clk *clk, u8 state) -{ - const struct dpll_data *dd; - int i = 0; - int ret = -EINVAL; - - dd = clk->dpll_data; - - state <<= __ffs(dd->idlest_mask); - - while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && - i < MAX_DPLL_WAIT_TRIES) { - i++; - udelay(1); - } - - if (i == MAX_DPLL_WAIT_TRIES) { - printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk->name, (state) ? "locked" : "bypassed"); - } else { - pr_debug("clock: %s transition to '%s' in %d loops\n", - clk->name, (state) ? "locked" : "bypassed", i); - - ret = 0; - } - - return ret; -} - -/* From 3430 TRM ES2 4.7.6.2 */ -static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) -{ - unsigned long fint; - u16 f = 0; - - fint = clk->dpll_data->clk_ref->rate / n; - - pr_debug("clock: fint is %lu\n", fint); - - if (fint >= 750000 && fint <= 1000000) - f = 0x3; - else if (fint > 1000000 && fint <= 1250000) - f = 0x4; - else if (fint > 1250000 && fint <= 1500000) - f = 0x5; - else if (fint > 1500000 && fint <= 1750000) - f = 0x6; - else if (fint > 1750000 && fint <= 2100000) - f = 0x7; - else if (fint > 7500000 && fint <= 10000000) - f = 0xB; - else if (fint > 10000000 && fint <= 12500000) - f = 0xC; - else if (fint > 12500000 && fint <= 15000000) - f = 0xD; - else if (fint > 15000000 && fint <= 17500000) - f = 0xE; - else if (fint > 17500000 && fint <= 21000000) - f = 0xF; - else - pr_debug("clock: unknown freqsel setting for %d\n", n); - - return f; -} - -/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ - -/* - * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report - * readiness before returning. Will save and restore the DPLL's - * autoidle state across the enable, per the CDP code. If the DPLL - * locked successfully, return 0; if the DPLL did not lock in the time - * allotted, or DPLL3 was passed in, return -EINVAL. - */ -static int _omap3_noncore_dpll_lock(struct clk *clk) -{ - u8 ai; - int r; - - pr_debug("clock: locking DPLL %s\n", clk->name); - - ai = omap3_dpll_autoidle_read(clk); - - omap3_dpll_deny_idle(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOCKED); - - r = _omap3_wait_dpll_status(clk, 1); - - if (ai) - omap3_dpll_allow_idle(clk); - - return r; -} - -/* - * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power bypass mode. In - * bypass mode, the DPLL's rate is set equal to its parent clock's - * rate. Waits for the DPLL to report readiness before returning. - * Will save and restore the DPLL's autoidle state across the enable, - * per the CDP code. If the DPLL entered bypass mode successfully, - * return 0; if the DPLL did not enter bypass in the time allotted, or - * DPLL3 was passed in, or the DPLL does not support low-power bypass, - * return -EINVAL. - */ -static int _omap3_noncore_dpll_bypass(struct clk *clk) -{ - int r; - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) - return -EINVAL; - - pr_debug("clock: configuring DPLL %s for low-power bypass\n", - clk->name); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); - - r = _omap3_wait_dpll_status(clk, 0); - - if (ai) - omap3_dpll_allow_idle(clk); - else - omap3_dpll_deny_idle(clk); - - return r; -} - -/* - * _omap3_noncore_dpll_stop - instruct a DPLL to stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. Will save and - * restore the DPLL's autoidle state across the stop, per the CDP - * code. If DPLL3 was passed in, or the DPLL does not support - * low-power stop, return -EINVAL; otherwise, return 0. - */ -static int _omap3_noncore_dpll_stop(struct clk *clk) -{ - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) - return -EINVAL; - - pr_debug("clock: stopping DPLL %s\n", clk->name); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); - - if (ai) - omap3_dpll_allow_idle(clk); - else - omap3_dpll_deny_idle(clk); - - return 0; -} - -/** - * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. - * The choice of modes depends on the DPLL's programmed rate: if it is - * the same as the DPLL's parent clock, it will enter bypass; - * otherwise, it will enter lock. This code will wait for the DPLL to - * indicate readiness before returning, unless the DPLL takes too long - * to enter the target state. Intended to be used as the struct clk's - * enable function. If DPLL3 was passed in, or the DPLL does not - * support low-power stop, or if the DPLL took too long to enter - * bypass or lock, return -EINVAL; otherwise, return 0. - */ -int omap3_noncore_dpll_enable(struct clk *clk) -{ - int r; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (clk->rate == dd->clk_bypass->rate) { - WARN_ON(clk->parent != dd->clk_bypass); - r = _omap3_noncore_dpll_bypass(clk); - } else { - WARN_ON(clk->parent != dd->clk_ref); - r = _omap3_noncore_dpll_lock(clk); - } - /* - *FIXME: this is dubious - if clk->rate has changed, what about - * propagating? - */ - if (!r) - clk->rate = omap2_get_dpll_rate(clk); - - return r; -} - -/** - * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. This function is - * intended for use in struct clkops. No return value. - */ -void omap3_noncore_dpll_disable(struct clk *clk) -{ - _omap3_noncore_dpll_stop(clk); -} - - -/* Non-CORE DPLL rate set code */ - -/* - * omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * @freqsel: FREQSEL value to set - * - * Program the DPLL with the supplied M, N values, and wait for the DPLL to - * lock.. Returns -EINVAL upon error, or 0 upon success. - */ -int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) -{ - struct dpll_data *dd = clk->dpll_data; - u32 v; - - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); - - /* Set jitter correction */ - if (!cpu_is_omap44xx()) { - v = __raw_readl(dd->control_reg); - v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); - __raw_writel(v, dd->control_reg); - } - - /* Set DPLL multiplier, divider */ - v = __raw_readl(dd->mult_div1_reg); - v &= ~(dd->mult_mask | dd->div1_mask); - v |= m << __ffs(dd->mult_mask); - v |= (n - 1) << __ffs(dd->div1_mask); - __raw_writel(v, dd->mult_div1_reg); - - /* We let the clock framework set the other output dividers later */ - - /* REVISIT: Set ramp-up delay? */ - - _omap3_noncore_dpll_lock(clk); - - return 0; -} - -/** - * omap3_noncore_dpll_set_rate - set non-core DPLL rate - * @clk: struct clk * of DPLL to set - * @rate: rounded target rate - * - * Set the DPLL CLKOUT to the target rate. If the DPLL can enter - * low-power bypass, and the target rate is the bypass source clock - * rate, then configure the DPLL for bypass. Otherwise, round the - * target rate if it hasn't been done already, then program and lock - * the DPLL. Returns -EINVAL upon error, or 0 upon success. - */ -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *new_parent = NULL; - u16 freqsel = 0; - struct dpll_data *dd; - int ret; - - if (!clk || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (rate == omap2_get_dpll_rate(clk)) - return 0; - - /* - * Ensure both the bypass and ref clocks are enabled prior to - * doing anything; we need the bypass clock running to reprogram - * the DPLL. - */ - omap2_clk_enable(dd->clk_bypass); - omap2_clk_enable(dd->clk_ref); - - if (dd->clk_bypass->rate == rate && - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); - - ret = _omap3_noncore_dpll_bypass(clk); - if (!ret) - new_parent = dd->clk_bypass; - } else { - if (dd->last_rounded_rate != rate) - omap2_dpll_round_rate(clk, rate); - - if (dd->last_rounded_rate == 0) - return -EINVAL; - - /* No freqsel on OMAP4 */ - if (!cpu_is_omap44xx()) { - freqsel = _omap3_dpll_compute_freqsel(clk, - dd->last_rounded_n); - if (!freqsel) - WARN_ON(1); - } - - pr_debug("clock: %s: set rate: locking rate to %lu.\n", - clk->name, rate); - - ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, - dd->last_rounded_n, freqsel); - if (!ret) - new_parent = dd->clk_ref; - } - if (!ret) { - /* - * Switch the parent clock in the heirarchy, and make sure - * that the new parent's usecount is correct. Note: we - * enable the new parent before disabling the old to avoid - * any unnecessary hardware disable->enable transitions. - */ - if (clk->usecount) { - omap2_clk_enable(new_parent); - omap2_clk_disable(clk->parent); - } - clk_reparent(clk, new_parent); - clk->rate = rate; - } - omap2_clk_disable(dd->clk_ref); - omap2_clk_disable(dd->clk_bypass); - - return 0; -} - -/* DPLL autoidle read/set code */ - -/** - * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read - * - * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not - * appear to refer to a DPLL. - */ -u32 omap3_dpll_autoidle_read(struct clk *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd = clk->dpll_data; - - v = __raw_readl(dd->autoidle_reg); - v &= dd->autoidle_mask; - v >>= __ffs(dd->autoidle_mask); - - return v; -} - -/** - * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on - * - * Enable DPLL automatic idle control. This automatic idle mode - * switching takes effect only when the DPLL is locked, at least on - * OMAP3430. The DPLL will enter low-power stop when its downstream - * clocks are gated. No return value. - */ -void omap3_dpll_allow_idle(struct clk *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - /* - * REVISIT: CORE DPLL can optionally enter low-power bypass - * by writing 0x5 instead of 0x1. Add some mechanism to - * optionally enter this mode. - */ - v = __raw_readl(dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); -} - -/** - * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on - * - * Disable DPLL automatic idle control. No return value. - */ -void omap3_dpll_deny_idle(struct clk *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - v = __raw_readl(dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); - -} - -/* Clock control for DPLL outputs */ - -/** - * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate - * @clk: DPLL output struct clk - * - * Using parent clock DPLL data, look up DPLL state. If locked, set our - * rate to the dpll_clk * 2; otherwise, just use dpll_clk. - */ -unsigned long omap3_clkoutx2_recalc(struct clk *clk) -{ - const struct dpll_data *dd; - unsigned long rate; - u32 v; - struct clk *pclk; - - /* Walk up the parents of clk, looking for a DPLL */ - pclk = clk->parent; - while (pclk && !pclk->dpll_data) - pclk = pclk->parent; - - /* clk does not have a DPLL as a parent? */ - WARN_ON(!pclk); - - dd = pclk->dpll_data; - - WARN_ON(!dd->enable_mask); - - v = __raw_readl(dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); - if (v != OMAP3XXX_EN_DPLL_LOCKED) - rate = clk->parent->rate; - else - rate = clk->parent->rate * 2; - return rate; -} diff --git a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c b/trunk/arch/arm/mach-omap2/gpmc-smc91x.c index 877c6f5807b7..6083e21b3be6 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/trunk/arch/arm/mach-omap2/gpmc-smc91x.c @@ -33,19 +33,17 @@ static struct resource gpmc_smc91x_resources[] = { }; static struct smc91x_platdata gpmc_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0, }; static struct platform_device gpmc_smc91x_device = { .name = "smc91x", .id = -1, + .num_resources = ARRAY_SIZE(gpmc_smc91x_resources), + .resource = gpmc_smc91x_resources, .dev = { .platform_data = &gpmc_smc91x_info, }, - .num_resources = ARRAY_SIZE(gpmc_smc91x_resources), - .resource = gpmc_smc91x_resources, }; /* diff --git a/trunk/arch/arm/mach-omap2/gpmc.c b/trunk/arch/arm/mach-omap2/gpmc.c index bd8cb5974726..e86f5ca180ea 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.c +++ b/trunk/arch/arm/mach-omap2/gpmc.c @@ -517,7 +517,7 @@ void __init gpmc_init(void) ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; } else if (cpu_is_omap44xx()) { - ck = "gpmc_ck"; + ck = "gpmc_fck"; l = OMAP44XX_GPMC_BASE; } diff --git a/trunk/arch/arm/mach-omap2/i2c.c b/trunk/arch/arm/mach-omap2/i2c.c deleted file mode 100644 index 789ca8c02f0c..000000000000 --- a/trunk/arch/arm/mach-omap2/i2c.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Helper module for board specific I2C bus registration - * - * Copyright (C) 2009 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include -#include -#include - -#include "mux.h" - -int __init omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len) -{ - if (cpu_is_omap24xx()) { - const int omap24xx_pins[][2] = { - { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, - { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, - }; - int scl, sda; - - scl = omap24xx_pins[bus_id - 1][0]; - sda = omap24xx_pins[bus_id - 1][1]; - omap_cfg_reg(sda); - omap_cfg_reg(scl); - } - - /* First I2C bus is not muxable */ - if (cpu_is_omap34xx() && bus_id > 1) { - char mux_name[sizeof("i2c2_scl.i2c2_scl")]; - - sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - } - - return omap_plat_register_i2c_bus(bus_id, clkrate, info, len); -} diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index a091b53657b9..f48a4b2654dd 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -246,31 +246,6 @@ void __init omap3_check_revision(void) } } -void __init omap4_check_revision(void) -{ - u32 idcode; - u16 hawkeye; - u8 rev; - char *rev_name = "ES1.0"; - - /* - * The IC rev detection is done with hawkeye and rev. - * Note that rev does not map directly to defined processor - * revision numbers as ES1.0 uses value 0. - */ - idcode = read_tap_reg(OMAP_TAP_IDCODE); - hawkeye = (idcode >> 12) & 0xffff; - rev = (idcode >> 28) & 0xff; - - if ((hawkeye == 0xb852) && (rev == 0x0)) { - omap_revision = OMAP4430_REV_ES1_0; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); - return; - } - - pr_err("Unknown OMAP4 CPU id\n"); -} - #define OMAP3_SHOW_FEATURE(feat) \ if (omap3_has_ ##feat()) \ printk(#feat" "); @@ -302,10 +277,10 @@ void __init omap3_cpuinfo(void) } else if (omap3_has_iva() && omap3_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ strcpy(cpu_name, "OMAP3430/3530"); - } else if (omap3_has_iva()) { + } else if (omap3_has_sgx()) { omap_revision = OMAP3525_REV(rev); strcpy(cpu_name, "OMAP3525"); - } else if (omap3_has_sgx()) { + } else if (omap3_has_iva()) { omap_revision = OMAP3515_REV(rev); strcpy(cpu_name, "OMAP3515"); } else { @@ -361,7 +336,7 @@ void __init omap2_check_revision(void) omap3_check_features(); omap3_cpuinfo(); } else if (cpu_is_omap44xx()) { - omap4_check_revision(); + printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n"); return; } else { pr_err("OMAP revision unknown, please fix!\n"); diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index a8749e8017b9..6a4d8e468703 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -33,9 +33,9 @@ #include #include #include -#include #include +#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ #include "clock.h" #include @@ -44,6 +44,7 @@ #include #include "clockdomains.h" +#endif #include #include "omap_hwmod_2420.h" #include "omap_hwmod_2430.h" @@ -320,8 +321,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); -#endif omap2_clk_init(); +#endif omap_serial_early_init(); #ifndef CONFIG_ARCH_OMAP4 omap_hwmod_late_init(); diff --git a/trunk/arch/arm/mach-omap2/mux.c b/trunk/arch/arm/mach-omap2/mux.c index e071b3fd1878..c18a94eca641 100644 --- a/trunk/arch/arm/mach-omap2/mux.c +++ b/trunk/arch/arm/mach-omap2/mux.c @@ -27,52 +27,19 @@ #include #include #include -#include -#include -#include -#include -#include #include #include #include -#include "mux.h" - -#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ -#define OMAP_MUX_BASE_SZ 0x5ca - -struct omap_mux_entry { - struct omap_mux mux; - struct list_head node; -}; - -static unsigned long mux_phys; -static void __iomem *mux_base; - -static inline u16 omap_mux_read(u16 reg) -{ - if (cpu_is_omap24xx()) - return __raw_readb(mux_base + reg); - else - return __raw_readw(mux_base + reg); -} - -static inline void omap_mux_write(u16 val, u16 reg) -{ - if (cpu_is_omap24xx()) - __raw_writeb(val, mux_base + reg); - else - __raw_writew(val, mux_base + reg); -} - -#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) +#ifdef CONFIG_OMAP_MUX static struct omap_mux_cfg arch_mux_cfg; /* NOTE: See mux.h for the enumeration */ +#ifdef CONFIG_ARCH_OMAP24XX static struct pin_config __initdata_or_module omap24xx_pins[] = { /* * description mux mux pull pull debug @@ -282,14 +249,342 @@ MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) +#else +#define omap24xx_pins NULL +#define OMAP24XX_PINS_SZ 0 +#endif /* CONFIG_ARCH_OMAP24XX */ + +#ifdef CONFIG_ARCH_OMAP34XX +static struct pin_config __initdata_or_module omap34xx_pins[] = { +/* + * Name, reg-offset, + * mux-mode | [active-mode | off-mode] + */ + +/* 34xx I2C */ +MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) + +/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/ +MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) + +/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/ +MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN) + +/* TLL - HSUSB: 12-pin TLL Port 1*/ +MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) + +/* TLL - HSUSB: 12-pin TLL Port 2*/ +MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN) + +/* TLL - HSUSB: 12-pin TLL Port 3*/ +MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) + +/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */ +MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) + +/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */ +MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de, + OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) + +/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */ +MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, + OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) + + +/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. + * (Always specify PIN_INPUT, except for names suffixed by "_OUT".) + * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. + */ +MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN) +MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) + +/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) + +/* MMC1 */ +MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) + +/* MMC2 */ +MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP) + +/* MMC3 */ +MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0, + OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2, + OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP) + +/* SYS_NIRQ T2 INT1 */ +MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0, + OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP | + OMAP34XX_MUX_MODE0) +/* EHCI GPIO's on OMAP3EVM (Rev >= E) */ +MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) +MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) +}; + +#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) + +#else +#define omap34xx_pins NULL +#define OMAP34XX_PINS_SZ 0 +#endif /* CONFIG_ARCH_OMAP34XX */ +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) { u16 orig; u8 warn = 0, debug = 0; - orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET); + if (cpu_is_omap24xx()) + orig = omap_ctrl_readb(cfg->mux_reg); + else + orig = omap_ctrl_readw(cfg->mux_reg); #ifdef CONFIG_OMAP_MUX_DEBUG debug = cfg->debug; @@ -305,6 +600,7 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r #define omap2_cfg_debug(x, y) do {} while (0) #endif +#ifdef CONFIG_ARCH_OMAP24XX static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) { static DEFINE_SPINLOCK(mux_spin_lock); @@ -318,692 +614,47 @@ static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) if (cfg->pu_pd_val) reg |= OMAP2_PULL_UP; omap2_cfg_debug(cfg, reg); - omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET); + omap_ctrl_writeb(reg, cfg->mux_reg); spin_unlock_irqrestore(&mux_spin_lock, flags); return 0; } - -int __init omap2_mux_init(void) -{ - u32 mux_pbase; - - if (cpu_is_omap2420()) - mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else if (cpu_is_omap2430()) - mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else - return -ENODEV; - - mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ); - if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); - return -ENODEV; - } - - if (cpu_is_omap24xx()) { - arch_mux_cfg.pins = omap24xx_pins; - arch_mux_cfg.size = OMAP24XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; - - return omap_mux_register(&arch_mux_cfg); - } - - return 0; -} - #else -int __init omap2_mux_init(void) -{ - return 0; -} -#endif /* CONFIG_OMAP_MUX */ - -/*----------------------------------------------------------------------------*/ +#define omap24xx_cfg_reg NULL +#endif #ifdef CONFIG_ARCH_OMAP34XX -static LIST_HEAD(muxmodes); -static DEFINE_MUTEX(muxmode_mutex); - -#ifdef CONFIG_OMAP_MUX - -static char *omap_mux_options; - -int __init omap_mux_init_gpio(int gpio, int val) +static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg) { - struct omap_mux_entry *e; - int found = 0; - - if (!gpio) - return -EINVAL; - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - if (gpio == m->gpio) { - u16 old_mode; - u16 mux_mode; - - old_mode = omap_mux_read(m->reg_offset); - mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - mux_mode |= OMAP_MUX_MODE4; - printk(KERN_DEBUG "mux: Setting signal " - "%s.gpio%i 0x%04x -> 0x%04x\n", - m->muxnames[0], gpio, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); - found++; - } - } - - if (found == 1) - return 0; - - if (found > 1) { - printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); - return -EINVAL; - } - - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); - - return -ENODEV; -} - -int __init omap_mux_init_signal(char *muxname, int val) -{ - struct omap_mux_entry *e; - char *m0_name = NULL, *mode_name = NULL; - int found = 0; - - mode_name = strchr(muxname, '.'); - if (mode_name) { - *mode_name = '\0'; - mode_name++; - m0_name = muxname; - } else { - mode_name = muxname; - } - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - char *m0_entry = m->muxnames[0]; - int i; - - if (m0_name && strcmp(m0_name, m0_entry)) - continue; - - for (i = 0; i < OMAP_MUX_NR_MODES; i++) { - char *mode_cur = m->muxnames[i]; - - if (!mode_cur) - continue; - - if (!strcmp(mode_name, mode_cur)) { - u16 old_mode; - u16 mux_mode; - - old_mode = omap_mux_read(m->reg_offset); - mux_mode = val | i; - printk(KERN_DEBUG "mux: Setting signal " - "%s.%s 0x%04x -> 0x%04x\n", - m0_entry, muxname, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); - found++; - } - } - } - - if (found == 1) - return 0; - - if (found > 1) { - printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", - found, muxname); - return -EINVAL; - } - - printk(KERN_ERR "mux: Could not set signal %s\n", muxname); - - return -ENODEV; -} - -#ifdef CONFIG_DEBUG_FS - -#define OMAP_MUX_MAX_NR_FLAGS 10 -#define OMAP_MUX_TEST_FLAG(val, mask) \ - if (((val) & (mask)) == (mask)) { \ - i++; \ - flags[i] = #mask; \ - } - -/* REVISIT: Add checking for non-optimal mux settings */ -static inline void omap_mux_decode(struct seq_file *s, u16 val) -{ - char *flags[OMAP_MUX_MAX_NR_FLAGS]; - char mode[14]; - int i = -1; - - sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7); - i++; - flags[i] = mode; - - OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE); - if (val & OMAP_OFF_EN) { - if (!(val & OMAP_OFFOUT_EN)) { - if (!(val & OMAP_OFF_PULL_UP)) { - OMAP_MUX_TEST_FLAG(val, - OMAP_PIN_OFF_INPUT_PULLDOWN); - } else { - OMAP_MUX_TEST_FLAG(val, - OMAP_PIN_OFF_INPUT_PULLUP); - } - } else { - if (!(val & OMAP_OFFOUT_VAL)) { - OMAP_MUX_TEST_FLAG(val, - OMAP_PIN_OFF_OUTPUT_LOW); - } else { - OMAP_MUX_TEST_FLAG(val, - OMAP_PIN_OFF_OUTPUT_HIGH); - } - } - } - - if (val & OMAP_INPUT_EN) { - if (val & OMAP_PULL_ENA) { - if (!(val & OMAP_PULL_UP)) { - OMAP_MUX_TEST_FLAG(val, - OMAP_PIN_INPUT_PULLDOWN); - } else { - OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP); - } - } else { - OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT); - } - } else { - i++; - flags[i] = "OMAP_PIN_OUTPUT"; - } - - do { - seq_printf(s, "%s", flags[i]); - if (i > 0) - seq_printf(s, " | "); - } while (i-- > 0); -} - -#define OMAP_MUX_DEFNAME_LEN 16 - -static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) -{ - struct omap_mux_entry *e; - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - char m0_def[OMAP_MUX_DEFNAME_LEN]; - char *m0_name = m->muxnames[0]; - u16 val; - int i, mode; - - if (!m0_name) - continue; - - for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) { - if (m0_name[i] == '\0') { - m0_def[i] = m0_name[i]; - break; - } - m0_def[i] = toupper(m0_name[i]); - } - val = omap_mux_read(m->reg_offset); - mode = val & OMAP_MUX_MODE7; - - seq_printf(s, "OMAP%i_MUX(%s, ", - cpu_is_omap34xx() ? 3 : 0, m0_def); - omap_mux_decode(s, val); - seq_printf(s, "),\n"); - } - - return 0; -} - -static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) -{ - return single_open(file, omap_mux_dbg_board_show, &inode->i_private); -} - -static const struct file_operations omap_mux_dbg_board_fops = { - .open = omap_mux_dbg_board_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; + static DEFINE_SPINLOCK(mux_spin_lock); + unsigned long flags; + u16 reg = 0; -static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) -{ - struct omap_mux *m = s->private; - const char *none = "NA"; - u16 val; - int mode; - - val = omap_mux_read(m->reg_offset); - mode = val & OMAP_MUX_MODE7; - - seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", - m->muxnames[0], m->muxnames[mode], - mux_phys + m->reg_offset, m->reg_offset, val, - m->balls[0] ? m->balls[0] : none, - m->balls[1] ? m->balls[1] : none); - seq_printf(s, "mode: "); - omap_mux_decode(s, val); - seq_printf(s, "\n"); - seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n", - m->muxnames[0] ? m->muxnames[0] : none, - m->muxnames[1] ? m->muxnames[1] : none, - m->muxnames[2] ? m->muxnames[2] : none, - m->muxnames[3] ? m->muxnames[3] : none, - m->muxnames[4] ? m->muxnames[4] : none, - m->muxnames[5] ? m->muxnames[5] : none, - m->muxnames[6] ? m->muxnames[6] : none, - m->muxnames[7] ? m->muxnames[7] : none); + spin_lock_irqsave(&mux_spin_lock, flags); + reg |= cfg->mux_val; + omap2_cfg_debug(cfg, reg); + omap_ctrl_writew(reg, cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); return 0; } - -#define OMAP_MUX_MAX_ARG_CHAR 7 - -static ssize_t omap_mux_dbg_signal_write(struct file *file, - const char __user *user_buf, - size_t count, loff_t *ppos) -{ - char buf[OMAP_MUX_MAX_ARG_CHAR]; - struct seq_file *seqf; - struct omap_mux *m; - unsigned long val; - int buf_size, ret; - - if (count > OMAP_MUX_MAX_ARG_CHAR) - return -EINVAL; - - memset(buf, 0, sizeof(buf)); - buf_size = min(count, sizeof(buf) - 1); - - if (copy_from_user(buf, user_buf, buf_size)) - return -EFAULT; - - ret = strict_strtoul(buf, 0x10, &val); - if (ret < 0) - return ret; - - if (val > 0xffff) - return -EINVAL; - - seqf = file->private_data; - m = seqf->private; - - omap_mux_write((u16)val, m->reg_offset); - *ppos += count; - - return count; -} - -static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file) -{ - return single_open(file, omap_mux_dbg_signal_show, inode->i_private); -} - -static const struct file_operations omap_mux_dbg_signal_fops = { - .open = omap_mux_dbg_signal_open, - .read = seq_read, - .write = omap_mux_dbg_signal_write, - .llseek = seq_lseek, - .release = single_release, -}; - -static struct dentry *mux_dbg_dir; - -static void __init omap_mux_dbg_init(void) -{ - struct omap_mux_entry *e; - - mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); - if (!mux_dbg_dir) - return; - - (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, - NULL, &omap_mux_dbg_board_fops); - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - - (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, - m, &omap_mux_dbg_signal_fops); - } -} - #else -static inline void omap_mux_dbg_init(void) -{ -} -#endif /* CONFIG_DEBUG_FS */ - -static void __init omap_mux_free_names(struct omap_mux *m) -{ - int i; - - for (i = 0; i < OMAP_MUX_NR_MODES; i++) - kfree(m->muxnames[i]); - -#ifdef CONFIG_DEBUG_FS - for (i = 0; i < OMAP_MUX_NR_SIDES; i++) - kfree(m->balls[i]); -#endif - -} - -/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ -static int __init omap_mux_late_init(void) -{ - struct omap_mux_entry *e, *tmp; - - list_for_each_entry_safe(e, tmp, &muxmodes, node) { - struct omap_mux *m = &e->mux; - u16 mode = omap_mux_read(m->reg_offset); - - if (OMAP_MODE_GPIO(mode)) - continue; - -#ifndef CONFIG_DEBUG_FS - mutex_lock(&muxmode_mutex); - list_del(&e->node); - mutex_unlock(&muxmode_mutex); - omap_mux_free_names(m); - kfree(m); -#endif - - } - - omap_mux_dbg_init(); - - return 0; -} -late_initcall(omap_mux_late_init); - -static void __init omap_mux_package_fixup(struct omap_mux *p, - struct omap_mux *superset) -{ - while (p->reg_offset != OMAP_MUX_TERMINATOR) { - struct omap_mux *s = superset; - int found = 0; - - while (s->reg_offset != OMAP_MUX_TERMINATOR) { - if (s->reg_offset == p->reg_offset) { - *s = *p; - found++; - break; - } - s++; - } - if (!found) - printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", - p->reg_offset); - p++; - } -} - -#ifdef CONFIG_DEBUG_FS - -static void __init omap_mux_package_init_balls(struct omap_ball *b, - struct omap_mux *superset) -{ - while (b->reg_offset != OMAP_MUX_TERMINATOR) { - struct omap_mux *s = superset; - int found = 0; - - while (s->reg_offset != OMAP_MUX_TERMINATOR) { - if (s->reg_offset == b->reg_offset) { - s->balls[0] = b->balls[0]; - s->balls[1] = b->balls[1]; - found++; - break; - } - s++; - } - if (!found) - printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", - b->reg_offset); - b++; - } -} - -#else /* CONFIG_DEBUG_FS */ - -static inline void omap_mux_package_init_balls(struct omap_ball *b, - struct omap_mux *superset) -{ -} - -#endif /* CONFIG_DEBUG_FS */ - -static int __init omap_mux_setup(char *options) -{ - if (!options) - return 0; - - omap_mux_options = options; - - return 1; -} -__setup("omap_mux=", omap_mux_setup); - -/* - * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234 - * cmdline options only override the bootloader values. - * During development, please enable CONFIG_DEBUG_FS, and use the - * signal specific entries under debugfs. - */ -static void __init omap_mux_set_cmdline_signals(void) -{ - char *options, *next_opt, *token; - - if (!omap_mux_options) - return; - - options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL); - if (!options) - return; - - strcpy(options, omap_mux_options); - next_opt = options; - - while ((token = strsep(&next_opt, ",")) != NULL) { - char *keyval, *name; - unsigned long val; - - keyval = token; - name = strsep(&keyval, "="); - if (name) { - int res; - - res = strict_strtoul(keyval, 0x10, &val); - if (res < 0) - continue; - - omap_mux_init_signal(name, (u16)val); - } - } - - kfree(options); -} - -static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux) -{ - while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { - omap_mux_write(board_mux->value, board_mux->reg_offset); - board_mux++; - } -} - -static int __init omap_mux_copy_names(struct omap_mux *src, - struct omap_mux *dst) -{ - int i; - - for (i = 0; i < OMAP_MUX_NR_MODES; i++) { - if (src->muxnames[i]) { - dst->muxnames[i] = - kmalloc(strlen(src->muxnames[i]) + 1, - GFP_KERNEL); - if (!dst->muxnames[i]) - goto free; - strcpy(dst->muxnames[i], src->muxnames[i]); - } - } - -#ifdef CONFIG_DEBUG_FS - for (i = 0; i < OMAP_MUX_NR_SIDES; i++) { - if (src->balls[i]) { - dst->balls[i] = - kmalloc(strlen(src->balls[i]) + 1, - GFP_KERNEL); - if (!dst->balls[i]) - goto free; - strcpy(dst->balls[i], src->balls[i]); - } - } +#define omap34xx_cfg_reg NULL #endif - return 0; - -free: - omap_mux_free_names(dst); - return -ENOMEM; - -} - -#endif /* CONFIG_OMAP_MUX */ - -static u16 omap_mux_get_by_gpio(int gpio) -{ - struct omap_mux_entry *e; - u16 offset = OMAP_MUX_TERMINATOR; - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; - if (m->gpio == gpio) { - offset = m->reg_offset; - break; - } - } - - return offset; -} - -/* Needed for dynamic muxing of GPIO pins for off-idle */ -u16 omap_mux_get_gpio(int gpio) -{ - u16 offset; - - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); - return offset; - } - - return omap_mux_read(offset); -} - -/* Needed for dynamic muxing of GPIO pins for off-idle */ -void omap_mux_set_gpio(u16 val, int gpio) -{ - u16 offset; - - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); - return; - } - - omap_mux_write(val, offset); -} - -static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) +int __init omap2_mux_init(void) { - struct omap_mux_entry *entry; - struct omap_mux *m; - - entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL); - if (!entry) - return NULL; - - m = &entry->mux; - memcpy(m, src, sizeof(struct omap_mux_entry)); - -#ifdef CONFIG_OMAP_MUX - if (omap_mux_copy_names(src, m)) { - kfree(entry); - return NULL; + if (cpu_is_omap24xx()) { + arch_mux_cfg.pins = omap24xx_pins; + arch_mux_cfg.size = OMAP24XX_PINS_SZ; + arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; + } else if (cpu_is_omap34xx()) { + arch_mux_cfg.pins = omap34xx_pins; + arch_mux_cfg.size = OMAP34XX_PINS_SZ; + arch_mux_cfg.cfg_reg = omap34xx_cfg_reg; } -#endif - - mutex_lock(&muxmode_mutex); - list_add_tail(&entry->node, &muxmodes); - mutex_unlock(&muxmode_mutex); - return m; + return omap_mux_register(&arch_mux_cfg); } -/* - * Note if CONFIG_OMAP_MUX is not selected, we will only initialize - * the GPIO to mux offset mapping that is needed for dynamic muxing - * of GPIO pins for off-idle. - */ -static void __init omap_mux_init_list(struct omap_mux *superset) -{ - while (superset->reg_offset != OMAP_MUX_TERMINATOR) { - struct omap_mux *entry; - -#ifndef CONFIG_OMAP_MUX - /* Skip pins that are not muxed as GPIO by bootloader */ - if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { - superset++; - continue; - } #endif - - entry = omap_mux_list_add(superset); - if (!entry) { - printk(KERN_ERR "mux: Could not add entry\n"); - return; - } - superset++; - } -} - -int __init omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls) -{ - if (mux_base) - return -EBUSY; - - mux_phys = mux_pbase; - mux_base = ioremap(mux_pbase, mux_size); - if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); - return -ENODEV; - } - -#ifdef CONFIG_OMAP_MUX - omap_mux_package_fixup(package_subset, superset); - omap_mux_package_init_balls(package_balls, superset); - omap_mux_set_cmdline_signals(); - omap_mux_set_board_signals(board_mux); -#endif - - omap_mux_init_list(superset); - - return 0; -} - -#endif /* CONFIG_ARCH_OMAP34XX */ - diff --git a/trunk/arch/arm/mach-omap2/mux.h b/trunk/arch/arm/mach-omap2/mux.h deleted file mode 100644 index d8b4d5ad2278..000000000000 --- a/trunk/arch/arm/mach-omap2/mux.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "mux34xx.h" - -#define OMAP_MUX_TERMINATOR 0xffff - -/* 34xx mux mode options for each pin. See TRM for options */ -#define OMAP_MUX_MODE0 0 -#define OMAP_MUX_MODE1 1 -#define OMAP_MUX_MODE2 2 -#define OMAP_MUX_MODE3 3 -#define OMAP_MUX_MODE4 4 -#define OMAP_MUX_MODE5 5 -#define OMAP_MUX_MODE6 6 -#define OMAP_MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define OMAP_PULL_ENA (1 << 3) -#define OMAP_PULL_UP (1 << 4) -#define OMAP_ALTELECTRICALSEL (1 << 5) - -/* 34xx specific mux bit defines */ -#define OMAP_INPUT_EN (1 << 8) -#define OMAP_OFF_EN (1 << 9) -#define OMAP_OFFOUT_EN (1 << 10) -#define OMAP_OFFOUT_VAL (1 << 11) -#define OMAP_OFF_PULL_EN (1 << 12) -#define OMAP_OFF_PULL_UP (1 << 13) -#define OMAP_WAKEUP_EN (1 << 14) - -/* Active pin states */ -#define OMAP_PIN_OUTPUT 0 -#define OMAP_PIN_INPUT OMAP_INPUT_EN -#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \ - | OMAP_PULL_UP) -#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN) - -/* Off mode states */ -#define OMAP_PIN_OFF_NONE 0 -#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \ - | OMAP_OFFOUT_VAL) -#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN) -#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \ - | OMAP_OFF_PULL_UP) -#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN) -#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN - -#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) - -/* Flags for omap_mux_init */ -#define OMAP_PACKAGE_MASK 0xffff -#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */ -#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */ - - -#define OMAP_MUX_NR_MODES 8 /* Available modes */ -#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ - -/** - * struct omap_mux - data for omap mux register offset and it's value - * @reg_offset: mux register offset from the mux base - * @gpio: GPIO number - * @muxnames: available signal modes for a ball - */ -struct omap_mux { - u16 reg_offset; - u16 gpio; -#ifdef CONFIG_OMAP_MUX - char *muxnames[OMAP_MUX_NR_MODES]; -#ifdef CONFIG_DEBUG_FS - char *balls[OMAP_MUX_NR_SIDES]; -#endif -#endif -}; - -/** - * struct omap_ball - data for balls on omap package - * @reg_offset: mux register offset from the mux base - * @balls: available balls on the package - */ -struct omap_ball { - u16 reg_offset; - char *balls[OMAP_MUX_NR_SIDES]; -}; - -/** - * struct omap_board_mux - data for initializing mux registers - * @reg_offset: mux register offset from the mux base - * @mux_value: desired mux value to set - */ -struct omap_board_mux { - u16 reg_offset; - u16 value; -}; - -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX) - -/** - * omap_mux_init_gpio - initialize a signal based on the GPIO number - * @gpio: GPIO number - * @val: Options for the mux register value - */ -int omap_mux_init_gpio(int gpio, int val); - -/** - * omap_mux_init_signal - initialize a signal based on the signal name - * @muxname: Mux name in mode0_name.signal_name format - * @val: Options for the mux register value - */ -int omap_mux_init_signal(char *muxname, int val); - -#else - -static inline int omap_mux_init_gpio(int gpio, int val) -{ - return 0; -} -static inline int omap_mux_init_signal(char *muxname, int val) -{ - return 0; -} - -#endif - -/** - * omap_mux_get_gpio() - get mux register value based on GPIO number - * @gpio: GPIO number - * - */ -u16 omap_mux_get_gpio(int gpio); - -/** - * omap_mux_set_gpio() - set mux register value based on GPIO number - * @val: New mux register value - * @gpio: GPIO number - * - */ -void omap_mux_set_gpio(u16 val, int gpio); - -/** - * omap3_mux_init() - initialize mux system with board specific set - * @board_mux: Board specific mux table - * @flags: OMAP package type used for the board - */ -int omap3_mux_init(struct omap_board_mux *board_mux, int flags); - -/** - * omap_mux_init - private mux init function, do not call - */ -int omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls); diff --git a/trunk/arch/arm/mach-omap2/mux34xx.c b/trunk/arch/arm/mach-omap2/mux34xx.c deleted file mode 100644 index 68e0a595f9a1..000000000000 --- a/trunk/arch/arm/mach-omap2/mux34xx.c +++ /dev/null @@ -1,2099 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP3_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap3 - */ -static struct omap_mux __initdata omap3_muxmodes[] = { - _OMAP3_MUXENTRY(CAM_D0, 99, - "cam_d0", NULL, NULL, NULL, - "gpio_99", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D1, 100, - "cam_d1", NULL, NULL, NULL, - "gpio_100", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D10, 109, - "cam_d10", NULL, NULL, NULL, - "gpio_109", "hw_dbg8", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D11, 110, - "cam_d11", NULL, NULL, NULL, - "gpio_110", "hw_dbg9", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D2, 101, - "cam_d2", NULL, NULL, NULL, - "gpio_101", "hw_dbg4", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D3, 102, - "cam_d3", NULL, NULL, NULL, - "gpio_102", "hw_dbg5", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D4, 103, - "cam_d4", NULL, NULL, NULL, - "gpio_103", "hw_dbg6", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D5, 104, - "cam_d5", NULL, NULL, NULL, - "gpio_104", "hw_dbg7", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D6, 105, - "cam_d6", NULL, NULL, NULL, - "gpio_105", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D7, 106, - "cam_d7", NULL, NULL, NULL, - "gpio_106", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D8, 107, - "cam_d8", NULL, NULL, NULL, - "gpio_107", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D9, 108, - "cam_d9", NULL, NULL, NULL, - "gpio_108", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_FLD, 98, - "cam_fld", NULL, "cam_global_reset", NULL, - "gpio_98", "hw_dbg3", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_HS, 94, - "cam_hs", NULL, NULL, NULL, - "gpio_94", "hw_dbg0", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_PCLK, 97, - "cam_pclk", NULL, NULL, NULL, - "gpio_97", "hw_dbg2", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_STROBE, 126, - "cam_strobe", NULL, NULL, NULL, - "gpio_126", "hw_dbg11", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_VS, 95, - "cam_vs", NULL, NULL, NULL, - "gpio_95", "hw_dbg1", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_WEN, 167, - "cam_wen", NULL, "cam_shutter", NULL, - "gpio_167", "hw_dbg10", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_XCLKA, 96, - "cam_xclka", NULL, NULL, NULL, - "gpio_96", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_XCLKB, 111, - "cam_xclkb", NULL, NULL, NULL, - "gpio_111", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CSI2_DX0, 112, - "csi2_dx0", NULL, NULL, NULL, - "gpio_112", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CSI2_DX1, 114, - "csi2_dx1", NULL, NULL, NULL, - "gpio_114", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CSI2_DY0, 113, - "csi2_dy0", NULL, NULL, NULL, - "gpio_113", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CSI2_DY1, 115, - "csi2_dy1", NULL, NULL, NULL, - "gpio_115", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_ACBIAS, 69, - "dss_acbias", NULL, NULL, NULL, - "gpio_69", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA0, 70, - "dss_data0", NULL, "uart1_cts", NULL, - "gpio_70", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA1, 71, - "dss_data1", NULL, "uart1_rts", NULL, - "gpio_71", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA10, 80, - "dss_data10", NULL, NULL, NULL, - "gpio_80", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA11, 81, - "dss_data11", NULL, NULL, NULL, - "gpio_81", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA12, 82, - "dss_data12", NULL, NULL, NULL, - "gpio_82", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA13, 83, - "dss_data13", NULL, NULL, NULL, - "gpio_83", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA14, 84, - "dss_data14", NULL, NULL, NULL, - "gpio_84", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA15, 85, - "dss_data15", NULL, NULL, NULL, - "gpio_85", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA16, 86, - "dss_data16", NULL, NULL, NULL, - "gpio_86", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA17, 87, - "dss_data17", NULL, NULL, NULL, - "gpio_87", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA18, 88, - "dss_data18", NULL, "mcspi3_clk", "dss_data0", - "gpio_88", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA19, 89, - "dss_data19", NULL, "mcspi3_simo", "dss_data1", - "gpio_89", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA20, 90, - "dss_data20", NULL, "mcspi3_somi", "dss_data2", - "gpio_90", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA21, 91, - "dss_data21", NULL, "mcspi3_cs0", "dss_data3", - "gpio_91", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA22, 92, - "dss_data22", NULL, "mcspi3_cs1", "dss_data4", - "gpio_92", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA23, 93, - "dss_data23", NULL, NULL, "dss_data5", - "gpio_93", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA2, 72, - "dss_data2", NULL, NULL, NULL, - "gpio_72", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA3, 73, - "dss_data3", NULL, NULL, NULL, - "gpio_73", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA4, 74, - "dss_data4", NULL, "uart3_rx_irrx", NULL, - "gpio_74", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA5, 75, - "dss_data5", NULL, "uart3_tx_irtx", NULL, - "gpio_75", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA6, 76, - "dss_data6", NULL, "uart1_tx", NULL, - "gpio_76", "hw_dbg14", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA7, 77, - "dss_data7", NULL, "uart1_rx", NULL, - "gpio_77", "hw_dbg15", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA8, 78, - "dss_data8", NULL, NULL, NULL, - "gpio_78", "hw_dbg16", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA9, 79, - "dss_data9", NULL, NULL, NULL, - "gpio_79", "hw_dbg17", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_HSYNC, 67, - "dss_hsync", NULL, NULL, NULL, - "gpio_67", "hw_dbg13", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_PCLK, 66, - "dss_pclk", NULL, NULL, NULL, - "gpio_66", "hw_dbg12", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_VSYNC, 68, - "dss_vsync", NULL, NULL, NULL, - "gpio_68", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(ETK_CLK, 12, - "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", - "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"), - _OMAP3_MUXENTRY(ETK_CTL, 13, - "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", - "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"), - _OMAP3_MUXENTRY(ETK_D0, 14, - "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", - "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"), - _OMAP3_MUXENTRY(ETK_D1, 15, - "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", - "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"), - _OMAP3_MUXENTRY(ETK_D10, 24, - "etk_d10", NULL, "uart1_rx", "hsusb2_clk", - "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"), - _OMAP3_MUXENTRY(ETK_D11, 25, - "etk_d11", NULL, NULL, "hsusb2_stp", - "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"), - _OMAP3_MUXENTRY(ETK_D12, 26, - "etk_d12", NULL, NULL, "hsusb2_dir", - "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"), - _OMAP3_MUXENTRY(ETK_D13, 27, - "etk_d13", NULL, NULL, "hsusb2_nxt", - "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"), - _OMAP3_MUXENTRY(ETK_D14, 28, - "etk_d14", NULL, NULL, "hsusb2_data0", - "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"), - _OMAP3_MUXENTRY(ETK_D15, 29, - "etk_d15", NULL, NULL, "hsusb2_data1", - "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"), - _OMAP3_MUXENTRY(ETK_D2, 16, - "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", - "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"), - _OMAP3_MUXENTRY(ETK_D3, 17, - "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", - "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"), - _OMAP3_MUXENTRY(ETK_D4, 18, - "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", - "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"), - _OMAP3_MUXENTRY(ETK_D5, 19, - "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", - "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"), - _OMAP3_MUXENTRY(ETK_D6, 20, - "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", - "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"), - _OMAP3_MUXENTRY(ETK_D7, 21, - "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", - "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"), - _OMAP3_MUXENTRY(ETK_D8, 22, - "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", - "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"), - _OMAP3_MUXENTRY(ETK_D9, 23, - "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", - "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"), - _OMAP3_MUXENTRY(GPMC_A1, 34, - "gpmc_a1", NULL, NULL, NULL, - "gpio_34", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A10, 43, - "gpmc_a10", "sys_ndmareq3", NULL, NULL, - "gpio_43", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A2, 35, - "gpmc_a2", NULL, NULL, NULL, - "gpio_35", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A3, 36, - "gpmc_a3", NULL, NULL, NULL, - "gpio_36", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A4, 37, - "gpmc_a4", NULL, NULL, NULL, - "gpio_37", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A5, 38, - "gpmc_a5", NULL, NULL, NULL, - "gpio_38", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A6, 39, - "gpmc_a6", NULL, NULL, NULL, - "gpio_39", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A7, 40, - "gpmc_a7", NULL, NULL, NULL, - "gpio_40", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A8, 41, - "gpmc_a8", NULL, NULL, NULL, - "gpio_41", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_A9, 42, - "gpmc_a9", "sys_ndmareq2", NULL, NULL, - "gpio_42", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_CLK, 59, - "gpmc_clk", NULL, NULL, NULL, - "gpio_59", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D10, 46, - "gpmc_d10", NULL, NULL, NULL, - "gpio_46", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D11, 47, - "gpmc_d11", NULL, NULL, NULL, - "gpio_47", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D12, 48, - "gpmc_d12", NULL, NULL, NULL, - "gpio_48", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D13, 49, - "gpmc_d13", NULL, NULL, NULL, - "gpio_49", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D14, 50, - "gpmc_d14", NULL, NULL, NULL, - "gpio_50", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D15, 51, - "gpmc_d15", NULL, NULL, NULL, - "gpio_51", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D8, 44, - "gpmc_d8", NULL, NULL, NULL, - "gpio_44", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_D9, 45, - "gpmc_d9", NULL, NULL, NULL, - "gpio_45", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60, - "gpmc_nbe0_cle", NULL, NULL, NULL, - "gpio_60", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NBE1, 61, - "gpmc_nbe1", NULL, NULL, NULL, - "gpio_61", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS1, 52, - "gpmc_ncs1", NULL, NULL, NULL, - "gpio_52", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS2, 53, - "gpmc_ncs2", NULL, NULL, NULL, - "gpio_53", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS3, 54, - "gpmc_ncs3", "sys_ndmareq0", NULL, NULL, - "gpio_54", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS4, 55, - "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt", - "gpio_55", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS5, 56, - "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt", - "gpio_56", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS6, 57, - "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt", - "gpio_57", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NCS7, 58, - "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt", - "gpio_58", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_NWP, 62, - "gpmc_nwp", NULL, NULL, NULL, - "gpio_62", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_WAIT1, 63, - "gpmc_wait1", NULL, NULL, NULL, - "gpio_63", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_WAIT2, 64, - "gpmc_wait2", NULL, NULL, NULL, - "gpio_64", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_WAIT3, 65, - "gpmc_wait3", "sys_ndmareq1", NULL, NULL, - "gpio_65", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HDQ_SIO, 170, - "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe", - "gpio_170", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_CLK, 120, - "hsusb0_clk", NULL, NULL, NULL, - "gpio_120", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA0, 125, - "hsusb0_data0", NULL, "uart3_tx_irtx", NULL, - "gpio_125", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA1, 130, - "hsusb0_data1", NULL, "uart3_rx_irrx", NULL, - "gpio_130", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA2, 131, - "hsusb0_data2", NULL, "uart3_rts_sd", NULL, - "gpio_131", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA3, 169, - "hsusb0_data3", NULL, "uart3_cts_rctx", NULL, - "gpio_169", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA4, 188, - "hsusb0_data4", NULL, NULL, NULL, - "gpio_188", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA5, 189, - "hsusb0_data5", NULL, NULL, NULL, - "gpio_189", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA6, 190, - "hsusb0_data6", NULL, NULL, NULL, - "gpio_190", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA7, 191, - "hsusb0_data7", NULL, NULL, NULL, - "gpio_191", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DIR, 122, - "hsusb0_dir", NULL, NULL, NULL, - "gpio_122", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_NXT, 124, - "hsusb0_nxt", NULL, NULL, NULL, - "gpio_124", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_STP, 121, - "hsusb0_stp", NULL, NULL, NULL, - "gpio_121", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C2_SCL, 168, - "i2c2_scl", NULL, NULL, NULL, - "gpio_168", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C2_SDA, 183, - "i2c2_sda", NULL, NULL, NULL, - "gpio_183", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C3_SCL, 184, - "i2c3_scl", NULL, NULL, NULL, - "gpio_184", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C3_SDA, 185, - "i2c3_sda", NULL, NULL, NULL, - "gpio_185", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C4_SCL, 0, - "i2c4_scl", "sys_nvmode1", NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(I2C4_SDA, 0, - "i2c4_sda", "sys_nvmode2", NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(JTAG_EMU0, 11, - "jtag_emu0", NULL, NULL, NULL, - "gpio_11", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(JTAG_EMU1, 31, - "jtag_emu1", NULL, NULL, NULL, - "gpio_31", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_CLKR, 156, - "mcbsp1_clkr", "mcspi4_clk", NULL, NULL, - "gpio_156", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_CLKX, 162, - "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL, - "gpio_162", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_DR, 159, - "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL, - "gpio_159", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_DX, 158, - "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL, - "gpio_158", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_FSR, 157, - "mcbsp1_fsr", NULL, "cam_global_reset", NULL, - "gpio_157", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_FSX, 161, - "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL, - "gpio_161", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP2_CLKX, 117, - "mcbsp2_clkx", NULL, NULL, NULL, - "gpio_117", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP2_DR, 118, - "mcbsp2_dr", NULL, NULL, NULL, - "gpio_118", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP2_DX, 119, - "mcbsp2_dx", NULL, NULL, NULL, - "gpio_119", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP2_FSX, 116, - "mcbsp2_fsx", NULL, NULL, NULL, - "gpio_116", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_CLKX, 142, - "mcbsp3_clkx", "uart2_tx", NULL, NULL, - "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_DR, 141, - "mcbsp3_dr", "uart2_rts", NULL, NULL, - "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_DX, 140, - "mcbsp3_dx", "uart2_cts", NULL, NULL, - "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_FSX, 143, - "mcbsp3_fsx", "uart2_rx", NULL, NULL, - "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_CLKX, 152, - "mcbsp4_clkx", NULL, NULL, NULL, - "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_DR, 153, - "mcbsp4_dr", NULL, NULL, NULL, - "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_DX, 154, - "mcbsp4_dx", NULL, NULL, NULL, - "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_FSX, 155, - "mcbsp4_fsx", NULL, NULL, NULL, - "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP_CLKS, 160, - "mcbsp_clks", NULL, "cam_shutter", NULL, - "gpio_160", "uart1_cts", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CLK, 171, - "mcspi1_clk", "sdmmc2_dat4", NULL, NULL, - "gpio_171", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CS0, 174, - "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL, - "gpio_174", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CS1, 175, - "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd", - "gpio_175", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CS2, 176, - "mcspi1_cs2", NULL, NULL, "sdmmc3_clk", - "gpio_176", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CS3, 177, - "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2", - "gpio_177", "mm2_txdat", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_SIMO, 172, - "mcspi1_simo", "sdmmc2_dat5", NULL, NULL, - "gpio_172", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_SOMI, 173, - "mcspi1_somi", "sdmmc2_dat6", NULL, NULL, - "gpio_173", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI2_CLK, 178, - "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7", - "gpio_178", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI2_CS0, 181, - "mcspi2_cs0", "gpt11_pwm_evt", - "hsusb2_tll_data6", "hsusb2_data6", - "gpio_181", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI2_CS1, 182, - "mcspi2_cs1", "gpt8_pwm_evt", - "hsusb2_tll_data3", "hsusb2_data3", - "gpio_182", "mm2_txen_n", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI2_SIMO, 179, - "mcspi2_simo", "gpt9_pwm_evt", - "hsusb2_tll_data4", "hsusb2_data4", - "gpio_179", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCSPI2_SOMI, 180, - "mcspi2_somi", "gpt10_pwm_evt", - "hsusb2_tll_data5", "hsusb2_data5", - "gpio_180", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_CLK, 120, - "sdmmc1_clk", NULL, NULL, NULL, - "gpio_120", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_CMD, 121, - "sdmmc1_cmd", NULL, NULL, NULL, - "gpio_121", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT0, 122, - "sdmmc1_dat0", NULL, NULL, NULL, - "gpio_122", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT1, 123, - "sdmmc1_dat1", NULL, NULL, NULL, - "gpio_123", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT2, 124, - "sdmmc1_dat2", NULL, NULL, NULL, - "gpio_124", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT3, 125, - "sdmmc1_dat3", NULL, NULL, NULL, - "gpio_125", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT4, 126, - "sdmmc1_dat4", NULL, "sim_io", NULL, - "gpio_126", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT5, 127, - "sdmmc1_dat5", NULL, "sim_clk", NULL, - "gpio_127", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT6, 128, - "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL, - "gpio_128", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT7, 129, - "sdmmc1_dat7", NULL, "sim_rst", NULL, - "gpio_129", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_CLK, 130, - "sdmmc2_clk", "mcspi3_clk", NULL, NULL, - "gpio_130", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_CMD, 131, - "sdmmc2_cmd", "mcspi3_simo", NULL, NULL, - "gpio_131", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT0, 132, - "sdmmc2_dat0", "mcspi3_somi", NULL, NULL, - "gpio_132", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT1, 133, - "sdmmc2_dat1", NULL, NULL, NULL, - "gpio_133", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT2, 134, - "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL, - "gpio_134", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT3, 135, - "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL, - "gpio_135", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT4, 136, - "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0", - "gpio_136", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT5, 137, - "sdmmc2_dat5", "sdmmc2_dir_dat1", - "cam_global_reset", "sdmmc3_dat1", - "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT6, 138, - "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2", - "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT7, 139, - "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3", - "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"), - _OMAP3_MUXENTRY(SDRC_CKE0, 0, - "sdrc_cke0", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDRC_CKE1, 0, - "sdrc_cke1", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT0, 2, - "sys_boot0", NULL, NULL, NULL, - "gpio_2", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT1, 3, - "sys_boot1", NULL, NULL, NULL, - "gpio_3", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT2, 4, - "sys_boot2", NULL, NULL, NULL, - "gpio_4", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT3, 5, - "sys_boot3", NULL, NULL, NULL, - "gpio_5", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT4, 6, - "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL, - "gpio_6", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT5, 7, - "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL, - "gpio_7", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT6, 8, - "sys_boot6", NULL, NULL, NULL, - "gpio_8", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_CLKOUT1, 10, - "sys_clkout1", NULL, NULL, NULL, - "gpio_10", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_CLKOUT2, 186, - "sys_clkout2", NULL, NULL, NULL, - "gpio_186", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_CLKREQ, 1, - "sys_clkreq", NULL, NULL, NULL, - "gpio_1", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_NIRQ, 0, - "sys_nirq", NULL, NULL, NULL, - "gpio_0", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_NRESWARM, 30, - "sys_nreswarm", NULL, NULL, NULL, - "gpio_30", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_OFF_MODE, 9, - "sys_off_mode", NULL, NULL, NULL, - "gpio_9", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_CTS, 150, - "uart1_cts", NULL, NULL, NULL, - "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_RTS, 149, - "uart1_rts", NULL, NULL, NULL, - "gpio_149", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_RX, 151, - "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk", - "gpio_151", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_TX, 148, - "uart1_tx", NULL, NULL, NULL, - "gpio_148", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART2_CTS, 144, - "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL, - "gpio_144", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART2_RTS, 145, - "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL, - "gpio_145", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART2_RX, 147, - "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL, - "gpio_147", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART2_TX, 146, - "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL, - "gpio_146", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163, - "uart3_cts_rctx", NULL, NULL, NULL, - "gpio_163", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART3_RTS_SD, 164, - "uart3_rts_sd", NULL, NULL, NULL, - "gpio_164", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART3_RX_IRRX, 165, - "uart3_rx_irrx", NULL, NULL, NULL, - "gpio_165", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART3_TX_IRTX, 166, - "uart3_tx_irtx", NULL, NULL, NULL, - "gpio_166", NULL, NULL, "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Signals different on CBC package compared to the superset - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC) -struct omap_mux __initdata omap3_cbc_subset[] = { - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cbc_subset NULL -#endif - -/* - * Balls for CBC package - * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom) - * - * FIXME: What's up with the outdated TI documentation? See: - * - * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package - * http://community.ti.com/forums/t/10982.aspx - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBC) -struct omap_ball __initdata omap3_cbc_ball[] = { - _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL), - _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL), - _OMAP3_BALLENTRY(CAM_D10, "d25", NULL), - _OMAP3_BALLENTRY(CAM_D11, "e26", NULL), - _OMAP3_BALLENTRY(CAM_D2, "a24", NULL), - _OMAP3_BALLENTRY(CAM_D3, "b24", NULL), - _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), - _OMAP3_BALLENTRY(CAM_D5, "c24", NULL), - _OMAP3_BALLENTRY(CAM_D6, "p25", NULL), - _OMAP3_BALLENTRY(CAM_D7, "p26", NULL), - _OMAP3_BALLENTRY(CAM_D8, "n25", NULL), - _OMAP3_BALLENTRY(CAM_D9, "n26", NULL), - _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL), - _OMAP3_BALLENTRY(CAM_HS, "c23", NULL), - _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL), - _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL), - _OMAP3_BALLENTRY(CAM_VS, "d23", NULL), - _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL), - _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), - _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL), - _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL), - _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL), - _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL), - _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL), - _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL), - _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL), - _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL), - _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL), - _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL), - _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL), - _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL), - _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL), - _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL), - _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL), - _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL), - _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL), - _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL), - _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL), - _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL), - _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL), - _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL), - _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL), - _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL), - _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL), - _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL), - _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL), - _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL), - _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL), - _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL), - _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL), - _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL), - _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL), - _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL), - _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL), - _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL), - _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL), - _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL), - _OMAP3_BALLENTRY(ETK_D11, "af6", NULL), - _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL), - _OMAP3_BALLENTRY(ETK_D13, "af7", NULL), - _OMAP3_BALLENTRY(ETK_D14, "af9", NULL), - _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL), - _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL), - _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL), - _OMAP3_BALLENTRY(ETK_D4, "y3", NULL), - _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL), - _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL), - _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL), - _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL), - _OMAP3_BALLENTRY(ETK_D9, "v2", NULL), - _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL), - _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL), - _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL), - _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL), - _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL), - _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL), - _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL), - _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL), - _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL), - _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL), - _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"), - _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"), - _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"), - _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"), - _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"), - _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"), - _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"), - _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"), - _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"), - _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL), - _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL), - _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"), - _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL), - _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL), - _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL), - _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL), - _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL), - _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL), - _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"), - _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"), - _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL), - _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL), - _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL), - _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL), - _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL), - _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL), - _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL), - _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL), - _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL), - _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL), - _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL), - _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL), - _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL), - _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL), - _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL), - _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL), - _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL), - _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL), - _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL), - _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL), - _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL), - _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL), - _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL), - _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL), - _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL), - _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL), - _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL), - _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL), - _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL), - _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL), - _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL), - _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL), - _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL), - _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL), - _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL), - _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL), - _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL), - _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL), - _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL), - _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL), - _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL), - _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL), - _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL), - _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"), - _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL), - _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL), - _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL), - _OMAP3_BALLENTRY(UART1_RX, "h3", NULL), - _OMAP3_BALLENTRY(UART1_TX, "l4", NULL), - _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL), - _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL), - _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL), - _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL), - _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL), - _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL), - _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL), - _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cbc_ball NULL -#endif - -/* - * Signals different on CUS package compared to superset - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_mux __initdata omap3_cus_subset[] = { - _OMAP3_MUXENTRY(CAM_D10, 109, - "cam_d10", NULL, NULL, NULL, - "gpio_109", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D11, 110, - "cam_d11", NULL, NULL, NULL, - "gpio_110", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D2, 101, - "cam_d2", NULL, NULL, NULL, - "gpio_101", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D3, 102, - "cam_d3", NULL, NULL, NULL, - "gpio_102", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D4, 103, - "cam_d4", NULL, NULL, NULL, - "gpio_103", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D5, 104, - "cam_d5", NULL, NULL, NULL, - "gpio_104", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_FLD, 98, - "cam_fld", NULL, "cam_global_reset", NULL, - "gpio_98", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_HS, 94, - "cam_hs", NULL, NULL, NULL, - "gpio_94", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_PCLK, 97, - "cam_pclk", NULL, NULL, NULL, - "gpio_97", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_STROBE, 126, - "cam_strobe", NULL, NULL, NULL, - "gpio_126", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_VS, 95, - "cam_vs", NULL, NULL, NULL, - "gpio_95", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_WEN, 167, - "cam_wen", NULL, "cam_shutter", NULL, - "gpio_167", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA6, 76, - "dss_data6", NULL, "uart1_tx", NULL, - "gpio_76", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA7, 77, - "dss_data7", NULL, "uart1_rx", NULL, - "gpio_77", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA8, 78, - "dss_data8", NULL, NULL, NULL, - "gpio_78", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA9, 79, - "dss_data9", NULL, NULL, NULL, - "gpio_79", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_HSYNC, 67, - "dss_hsync", NULL, NULL, NULL, - "gpio_67", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_PCLK, 66, - "dss_pclk", NULL, NULL, NULL, - "gpio_66", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(ETK_CLK, 12, - "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", - "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL), - _OMAP3_MUXENTRY(ETK_CTL, 13, - "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", - "gpio_13", NULL, "hsusb1_tll_clk", NULL), - _OMAP3_MUXENTRY(ETK_D0, 14, - "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", - "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL), - _OMAP3_MUXENTRY(ETK_D1, 15, - "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", - "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL), - _OMAP3_MUXENTRY(ETK_D10, 24, - "etk_d10", NULL, "uart1_rx", "hsusb2_clk", - "gpio_24", NULL, "hsusb2_tll_clk", NULL), - _OMAP3_MUXENTRY(ETK_D11, 25, - "etk_d11", NULL, NULL, "hsusb2_stp", - "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL), - _OMAP3_MUXENTRY(ETK_D12, 26, - "etk_d12", NULL, NULL, "hsusb2_dir", - "gpio_26", NULL, "hsusb2_tll_dir", NULL), - _OMAP3_MUXENTRY(ETK_D13, 27, - "etk_d13", NULL, NULL, "hsusb2_nxt", - "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL), - _OMAP3_MUXENTRY(ETK_D14, 28, - "etk_d14", NULL, NULL, "hsusb2_data0", - "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL), - _OMAP3_MUXENTRY(ETK_D15, 29, - "etk_d15", NULL, NULL, "hsusb2_data1", - "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL), - _OMAP3_MUXENTRY(ETK_D2, 16, - "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", - "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL), - _OMAP3_MUXENTRY(ETK_D3, 17, - "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", - "gpio_17", NULL, "hsusb1_tll_data7", NULL), - _OMAP3_MUXENTRY(ETK_D4, 18, - "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", - "gpio_18", NULL, "hsusb1_tll_data4", NULL), - _OMAP3_MUXENTRY(ETK_D5, 19, - "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", - "gpio_19", NULL, "hsusb1_tll_data5", NULL), - _OMAP3_MUXENTRY(ETK_D6, 20, - "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", - "gpio_20", NULL, "hsusb1_tll_data6", NULL), - _OMAP3_MUXENTRY(ETK_D7, 21, - "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", - "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL), - _OMAP3_MUXENTRY(ETK_D8, 22, - "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", - "gpio_22", NULL, "hsusb1_tll_dir", NULL), - _OMAP3_MUXENTRY(ETK_D9, 23, - "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", - "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL), - _OMAP3_MUXENTRY(MCBSP3_CLKX, 142, - "mcbsp3_clkx", "uart2_tx", NULL, NULL, - "gpio_142", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_DR, 141, - "mcbsp3_dr", "uart2_rts", NULL, NULL, - "gpio_141", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_DX, 140, - "mcbsp3_dx", "uart2_cts", NULL, NULL, - "gpio_140", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP3_FSX, 143, - "mcbsp3_fsx", "uart2_rx", NULL, NULL, - "gpio_143", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT5, 137, - "sdmmc2_dat5", "sdmmc2_dir_dat1", - "cam_global_reset", "sdmmc3_dat1", - "gpio_137", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT6, 138, - "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2", - "gpio_138", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC2_DAT7, 139, - "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3", - "gpio_139", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_CTS, 150, - "uart1_cts", NULL, NULL, NULL, - "gpio_150", NULL, NULL, "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cus_subset NULL -#endif - -/* - * Balls for CUS package - * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_ball __initdata omap3_cus_ball[] = { - _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), - _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), - _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), - _OMAP3_BALLENTRY(CAM_D11, "g21", NULL), - _OMAP3_BALLENTRY(CAM_D2, "g19", NULL), - _OMAP3_BALLENTRY(CAM_D3, "f19", NULL), - _OMAP3_BALLENTRY(CAM_D4, "g20", NULL), - _OMAP3_BALLENTRY(CAM_D5, "b21", NULL), - _OMAP3_BALLENTRY(CAM_D6, "l24", NULL), - _OMAP3_BALLENTRY(CAM_D7, "k24", NULL), - _OMAP3_BALLENTRY(CAM_D8, "j23", NULL), - _OMAP3_BALLENTRY(CAM_D9, "k23", NULL), - _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL), - _OMAP3_BALLENTRY(CAM_HS, "a22", NULL), - _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL), - _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL), - _OMAP3_BALLENTRY(CAM_VS, "e18", NULL), - _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL), - _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL), - _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL), - _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL), - _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL), - _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL), - _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL), - _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL), - _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL), - _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL), - _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL), - _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL), - _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL), - _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL), - _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL), - _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL), - _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL), - _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL), - _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL), - _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL), - _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL), - _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL), - _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL), - _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL), - _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL), - _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL), - _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL), - _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL), - _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL), - _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL), - _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL), - _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL), - _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL), - _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL), - _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL), - _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL), - _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL), - _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL), - _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL), - _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL), - _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL), - _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL), - _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL), - _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL), - _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL), - _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL), - _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL), - _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL), - _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL), - _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL), - _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL), - _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL), - _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL), - _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL), - _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL), - _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL), - _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL), - _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL), - _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL), - _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL), - _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL), - _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL), - _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL), - _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL), - _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL), - _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL), - _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL), - _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL), - _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL), - _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL), - _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL), - _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL), - _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL), - _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL), - _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL), - _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL), - _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL), - _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL), - _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL), - _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL), - _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL), - _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL), - _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL), - _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL), - _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL), - _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL), - _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL), - _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL), - _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL), - _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL), - _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL), - _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL), - _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL), - _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL), - _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL), - _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL), - _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL), - _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL), - _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL), - _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL), - _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL), - _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL), - _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL), - _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL), - _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL), - _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL), - _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL), - _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL), - _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL), - _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL), - _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL), - _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL), - _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL), - _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL), - _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL), - _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL), - _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL), - _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL), - _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL), - _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL), - _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL), - _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL), - _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL), - _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL), - _OMAP3_BALLENTRY(UART1_RX, "v7", NULL), - _OMAP3_BALLENTRY(UART1_TX, "w7", NULL), - _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL), - _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL), - _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL), - _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cus_ball NULL -#endif - -/* - * Signals different on CBB package comapared to superset - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_mux __initdata omap3_cbb_subset[] = { - _OMAP3_MUXENTRY(CAM_D10, 109, - "cam_d10", NULL, NULL, NULL, - "gpio_109", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D11, 110, - "cam_d11", NULL, NULL, NULL, - "gpio_110", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D2, 101, - "cam_d2", NULL, NULL, NULL, - "gpio_101", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D3, 102, - "cam_d3", NULL, NULL, NULL, - "gpio_102", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D4, 103, - "cam_d4", NULL, NULL, NULL, - "gpio_103", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D5, 104, - "cam_d5", NULL, NULL, NULL, - "gpio_104", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_FLD, 98, - "cam_fld", NULL, "cam_global_reset", NULL, - "gpio_98", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_HS, 94, - "cam_hs", NULL, NULL, NULL, - "gpio_94", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_PCLK, 97, - "cam_pclk", NULL, NULL, NULL, - "gpio_97", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_STROBE, 126, - "cam_strobe", NULL, NULL, NULL, - "gpio_126", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_VS, 95, - "cam_vs", NULL, NULL, NULL, - "gpio_95", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_WEN, 167, - "cam_wen", NULL, "cam_shutter", NULL, - "gpio_167", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA6, 76, - "dss_data6", NULL, "uart1_tx", NULL, - "gpio_76", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA7, 77, - "dss_data7", NULL, "uart1_rx", NULL, - "gpio_77", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA8, 78, - "dss_data8", NULL, NULL, NULL, - "gpio_78", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA9, 79, - "dss_data9", NULL, NULL, NULL, - "gpio_79", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_HSYNC, 67, - "dss_hsync", NULL, NULL, NULL, - "gpio_67", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_PCLK, 66, - "dss_pclk", NULL, NULL, NULL, - "gpio_66", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(ETK_CLK, 12, - "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp", - "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL), - _OMAP3_MUXENTRY(ETK_CTL, 13, - "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk", - "gpio_13", NULL, "hsusb1_tll_clk", NULL), - _OMAP3_MUXENTRY(ETK_D0, 14, - "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0", - "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL), - _OMAP3_MUXENTRY(ETK_D1, 15, - "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1", - "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL), - _OMAP3_MUXENTRY(ETK_D10, 24, - "etk_d10", NULL, "uart1_rx", "hsusb2_clk", - "gpio_24", NULL, "hsusb2_tll_clk", NULL), - _OMAP3_MUXENTRY(ETK_D11, 25, - "etk_d11", NULL, NULL, "hsusb2_stp", - "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL), - _OMAP3_MUXENTRY(ETK_D12, 26, - "etk_d12", NULL, NULL, "hsusb2_dir", - "gpio_26", NULL, "hsusb2_tll_dir", NULL), - _OMAP3_MUXENTRY(ETK_D13, 27, - "etk_d13", NULL, NULL, "hsusb2_nxt", - "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL), - _OMAP3_MUXENTRY(ETK_D14, 28, - "etk_d14", NULL, NULL, "hsusb2_data0", - "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL), - _OMAP3_MUXENTRY(ETK_D15, 29, - "etk_d15", NULL, NULL, "hsusb2_data1", - "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL), - _OMAP3_MUXENTRY(ETK_D2, 16, - "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2", - "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL), - _OMAP3_MUXENTRY(ETK_D3, 17, - "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7", - "gpio_17", NULL, "hsusb1_tll_data7", NULL), - _OMAP3_MUXENTRY(ETK_D4, 18, - "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4", - "gpio_18", NULL, "hsusb1_tll_data4", NULL), - _OMAP3_MUXENTRY(ETK_D5, 19, - "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5", - "gpio_19", NULL, "hsusb1_tll_data5", NULL), - _OMAP3_MUXENTRY(ETK_D6, 20, - "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6", - "gpio_20", NULL, "hsusb1_tll_data6", NULL), - _OMAP3_MUXENTRY(ETK_D7, 21, - "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3", - "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL), - _OMAP3_MUXENTRY(ETK_D8, 22, - "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir", - "gpio_22", NULL, "hsusb1_tll_dir", NULL), - _OMAP3_MUXENTRY(ETK_D9, 23, - "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt", - "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cbb_subset NULL -#endif - -/* - * Balls for CBB package - * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_ball __initdata omap3_cbb_ball[] = { - _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), - _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), - _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), - _OMAP3_BALLENTRY(CAM_D11, "c26", NULL), - _OMAP3_BALLENTRY(CAM_D2, "b24", NULL), - _OMAP3_BALLENTRY(CAM_D3, "c24", NULL), - _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), - _OMAP3_BALLENTRY(CAM_D5, "a25", NULL), - _OMAP3_BALLENTRY(CAM_D6, "k28", NULL), - _OMAP3_BALLENTRY(CAM_D7, "l28", NULL), - _OMAP3_BALLENTRY(CAM_D8, "k27", NULL), - _OMAP3_BALLENTRY(CAM_D9, "l27", NULL), - _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL), - _OMAP3_BALLENTRY(CAM_HS, "a24", NULL), - _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL), - _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL), - _OMAP3_BALLENTRY(CAM_VS, "a23", NULL), - _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL), - _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), - _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL), - _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL), - _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL), - _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL), - _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL), - _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL), - _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL), - _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL), - _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL), - _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL), - _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL), - _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL), - _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL), - _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL), - _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL), - _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL), - _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL), - _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL), - _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL), - _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL), - _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL), - _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL), - _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL), - _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL), - _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL), - _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL), - _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL), - _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL), - _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL), - _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL), - _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL), - _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL), - _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL), - _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL), - _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL), - _OMAP3_BALLENTRY(ETK_D0, "af11", NULL), - _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL), - _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL), - _OMAP3_BALLENTRY(ETK_D11, "af7", NULL), - _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL), - _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL), - _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL), - _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL), - _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL), - _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL), - _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL), - _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL), - _OMAP3_BALLENTRY(ETK_D6, "af13", NULL), - _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL), - _OMAP3_BALLENTRY(ETK_D8, "af9", NULL), - _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL), - _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"), - _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"), - _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"), - _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"), - _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"), - _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"), - _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"), - _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"), - _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), - _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), - _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), - _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), - _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), - _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), - _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), - _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), - _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), - _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"), - _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), - _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), - _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), - _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), - _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), - _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), - _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), - _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), - _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), - _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL), - _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL), - _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), - _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), - _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), - _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), - _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), - _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), - _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL), - _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL), - _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), - _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), - _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), - _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), - _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL), - _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL), - _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL), - _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL), - _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL), - _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL), - _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL), - _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL), - _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL), - _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL), - _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL), - _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL), - _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL), - _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL), - _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL), - _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL), - _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL), - _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL), - _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL), - _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL), - _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL), - _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL), - _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL), - _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), - _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), - _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), - _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), - _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL), - _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL), - _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL), - _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL), - _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL), - _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL), - _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL), - _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL), - _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL), - _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL), - _OMAP3_BALLENTRY(UART1_RX, "y8", NULL), - _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL), - _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL), - _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL), - _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL), - _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL), - _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL), - _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL), - _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL), - _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap3_cbb_ball NULL -#endif - -/* - * Signals different on 36XX CBP package comapared to 34XX CBC package - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) -struct omap_mux __initdata omap36xx_cbp_subset[] = { - _OMAP3_MUXENTRY(CAM_D0, 99, - "cam_d0", NULL, "csi2_dx2", NULL, - "gpio_99", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D1, 100, - "cam_d1", NULL, "csi2_dy2", NULL, - "gpio_100", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D10, 109, - "cam_d10", "ssi2_wake", NULL, NULL, - "gpio_109", "hw_dbg8", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D2, 101, - "cam_d2", "ssi2_rdy_tx", NULL, NULL, - "gpio_101", "hw_dbg4", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D3, 102, - "cam_d3", "ssi2_dat_rx", NULL, NULL, - "gpio_102", "hw_dbg5", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D4, 103, - "cam_d4", "ssi2_flag_rx", NULL, NULL, - "gpio_103", "hw_dbg6", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_D5, 104, - "cam_d5", "ssi2_rdy_rx", NULL, NULL, - "gpio_104", "hw_dbg7", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_HS, 94, - "cam_hs", "ssi2_dat_tx", NULL, NULL, - "gpio_94", "hw_dbg0", NULL, "safe_mode"), - _OMAP3_MUXENTRY(CAM_VS, 95, - "cam_vs", "ssi2_flag_tx", NULL, NULL, - "gpio_95", "hw_dbg1", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA0, 70, - "dss_data0", "dsi_dx0", "uart1_cts", NULL, - "gpio_70", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA1, 71, - "dss_data1", "dsi_dy0", "uart1_rts", NULL, - "gpio_71", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA2, 72, - "dss_data2", "dsi_dx1", NULL, NULL, - "gpio_72", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA3, 73, - "dss_data3", "dsi_dy1", NULL, NULL, - "gpio_73", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA4, 74, - "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL, - "gpio_74", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA5, 75, - "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL, - "gpio_75", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA6, 76, - "dss_data6", NULL, "uart1_tx", "dssvenc656_data6", - "gpio_76", "hw_dbg14", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA7, 77, - "dss_data7", NULL, "uart1_rx", "dssvenc656_data7", - "gpio_77", "hw_dbg15", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA8, 78, - "dss_data8", NULL, "uart3_rx_irrx", NULL, - "gpio_78", "hw_dbg16", NULL, "safe_mode"), - _OMAP3_MUXENTRY(DSS_DATA9, 79, - "dss_data9", NULL, "uart3_tx_irtx", NULL, - "gpio_79", "hw_dbg17", NULL, "safe_mode"), - _OMAP3_MUXENTRY(ETK_D12, 26, - "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir", - "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"), - _OMAP3_MUXENTRY(GPMC_A11, 0, - "gpmc_a11", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_WAIT2, 64, - "gpmc_wait2", NULL, "uart4_tx", NULL, - "gpio_64", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(GPMC_WAIT3, 65, - "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL, - "gpio_65", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA0, 125, - "hsusb0_data0", NULL, "uart3_tx_irtx", NULL, - "gpio_125", "uart2_tx", NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA1, 130, - "hsusb0_data1", NULL, "uart3_rx_irrx", NULL, - "gpio_130", "uart2_rx", NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA2, 131, - "hsusb0_data2", NULL, "uart3_rts_sd", NULL, - "gpio_131", "uart2_rts", NULL, "safe_mode"), - _OMAP3_MUXENTRY(HSUSB0_DATA3, 169, - "hsusb0_data3", NULL, "uart3_cts_rctx", NULL, - "gpio_169", "uart2_cts", NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_CLKR, 156, - "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL, - "gpio_156", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP1_FSR, 157, - "mcbsp1_fsr", "adpllv2d_dithering_en1", - "cam_global_reset", NULL, - "gpio_157", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_CLKX, 152, - "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL, - "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_DR, 153, - "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL, - "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_DX, 154, - "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL, - "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"), - _OMAP3_MUXENTRY(MCBSP4_FSX, 155, - "mcbsp4_fsx", "ssi1_wake", NULL, NULL, - "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"), - _OMAP3_MUXENTRY(MCSPI1_CS1, 175, - "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd", - "gpio_175", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0, - "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD28, 0, - "sad2d_mcad28", "mad2d_mcad28", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD29, 0, - "sad2d_mcad29", "mad2d_mcad29", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD32, 0, - "sad2d_mcad32", "mad2d_mcad32", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD33, 0, - "sad2d_mcad33", "mad2d_mcad33", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD34, 0, - "sad2d_mcad34", "mad2d_mcad34", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD35, 0, - "sad2d_mcad35", "mad2d_mcad35", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MCAD36, 0, - "sad2d_mcad36", "mad2d_mcad36", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MREAD, 0, - "sad2d_mread", "mad2d_sread", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_MWRITE, 0, - "sad2d_mwrite", "mad2d_swrite", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0, - "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_SREAD, 0, - "sad2d_sread", "mad2d_mread", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SAD2D_SWRITE, 0, - "sad2d_swrite", "mad2d_mwrite", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP3_MUXENTRY(SDMMC1_CLK, 120, - "sdmmc1_clk", "ms_clk", NULL, NULL, - "gpio_120", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_CMD, 121, - "sdmmc1_cmd", "ms_bs", NULL, NULL, - "gpio_121", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT0, 122, - "sdmmc1_dat0", "ms_dat0", NULL, NULL, - "gpio_122", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT1, 123, - "sdmmc1_dat1", "ms_dat1", NULL, NULL, - "gpio_123", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT2, 124, - "sdmmc1_dat2", "ms_dat2", NULL, NULL, - "gpio_124", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDMMC1_DAT3, 125, - "sdmmc1_dat3", "ms_dat3", NULL, NULL, - "gpio_125", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SDRC_CKE0, 0, - "sdrc_cke0", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode_out1"), - _OMAP3_MUXENTRY(SDRC_CKE1, 0, - "sdrc_cke1", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode_out1"), - _OMAP3_MUXENTRY(SIM_IO, 126, - "sim_io", "sim_io_low_impedance", NULL, NULL, - "gpio_126", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SIM_CLK, 127, - "sim_clk", NULL, NULL, NULL, - "gpio_127", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SIM_PWRCTRL, 128, - "sim_pwrctrl", NULL, NULL, NULL, - "gpio_128", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SIM_RST, 129, - "sim_rst", NULL, NULL, NULL, - "gpio_129", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT0, 2, - "sys_boot0", NULL, NULL, "dss_data18", - "gpio_2", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT1, 3, - "sys_boot1", NULL, NULL, "dss_data19", - "gpio_3", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT3, 5, - "sys_boot3", NULL, NULL, "dss_data20", - "gpio_5", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT4, 6, - "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21", - "gpio_6", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT5, 7, - "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22", - "gpio_7", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(SYS_BOOT6, 8, - "sys_boot6", NULL, NULL, "dss_data23", - "gpio_8", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_CTS, 150, - "uart1_cts", "ssi1_rdy_tx", NULL, NULL, - "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_RTS, 149, - "uart1_rts", "ssi1_flag_tx", NULL, NULL, - "gpio_149", NULL, NULL, "safe_mode"), - _OMAP3_MUXENTRY(UART1_TX, 148, - "uart1_tx", "ssi1_dat_tx", NULL, NULL, - "gpio_148", NULL, NULL, "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap36xx_cbp_subset NULL -#endif - -/* - * Balls for 36XX CBP package - * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined (CONFIG_OMAP_PACKAGE_CBP) -struct omap_ball __initdata omap36xx_cbp_ball[] = { - _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), - _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), - _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), - _OMAP3_BALLENTRY(CAM_D11, "c26", NULL), - _OMAP3_BALLENTRY(CAM_D2, "b24", NULL), - _OMAP3_BALLENTRY(CAM_D3, "c24", NULL), - _OMAP3_BALLENTRY(CAM_D4, "d24", NULL), - _OMAP3_BALLENTRY(CAM_D5, "a25", NULL), - _OMAP3_BALLENTRY(CAM_D6, "k28", NULL), - _OMAP3_BALLENTRY(CAM_D7, "l28", NULL), - _OMAP3_BALLENTRY(CAM_D8, "k27", NULL), - _OMAP3_BALLENTRY(CAM_D9, "l27", NULL), - _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL), - _OMAP3_BALLENTRY(CAM_HS, "a24", NULL), - _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL), - _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL), - _OMAP3_BALLENTRY(CAM_VS, "a23", NULL), - _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL), - _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL), - _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL), - _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL), - _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL), - _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL), - _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL), - _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL), - _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL), - _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL), - _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL), - _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL), - _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL), - _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL), - _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL), - _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL), - _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL), - _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL), - _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL), - _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL), - _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL), - _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL), - _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL), - _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL), - _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL), - _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL), - _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL), - _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL), - _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL), - _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL), - _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL), - _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL), - _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL), - _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL), - _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL), - _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL), - _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL), - _OMAP3_BALLENTRY(ETK_D0, "af11", NULL), - _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL), - _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL), - _OMAP3_BALLENTRY(ETK_D11, "af7", NULL), - _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL), - _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL), - _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL), - _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL), - _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL), - _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL), - _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL), - _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL), - _OMAP3_BALLENTRY(ETK_D6, "af13", NULL), - _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL), - _OMAP3_BALLENTRY(ETK_D8, "af9", NULL), - _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL), - _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"), - _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"), - _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"), - _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"), - _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"), - _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"), - _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"), - _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"), - _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"), - _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), - _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), - _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), - _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"), - _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"), - _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), - _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), - _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), - _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), - _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), - _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), - _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"), - _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"), - _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"), - _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"), - _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"), - _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"), - _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"), - _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), - _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"), - _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), - _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), - _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"), - _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), - _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), - _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), - _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"), - _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"), - _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), - _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"), - _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), - _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), - _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), - _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL), - _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL), - _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL), - _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), - _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), - _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), - _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL), - _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL), - _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), - _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), - _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), - _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL), - _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL), - _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), - _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), - _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), - _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL), - _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL), - _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL), - _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL), - _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), - _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), - _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), - _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL), - _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL), - _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL), - _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL), - _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL), - _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL), - _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL), - _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL), - _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL), - _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL), - _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL), - _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL), - _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL), - _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL), - _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL), - _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL), - _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL), - _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL), - _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL), - _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL), - _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL), - _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL), - _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL), - _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL), - _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL), - _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL), - _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL), - _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), - _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), - _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"), - _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"), - _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"), - _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"), - _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"), - _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"), - _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"), - _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"), - _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"), - _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"), - _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"), - _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"), - _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"), - _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"), - _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"), - _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"), - _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"), - _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"), - _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"), - _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"), - _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"), - _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"), - _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"), - _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"), - _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"), - _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"), - _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"), - _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"), - _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"), - _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"), - _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"), - _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"), - _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"), - _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"), - _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"), - _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"), - _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"), - _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"), - _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"), - _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"), - _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"), - _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"), - _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"), - _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"), - _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"), - _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"), - _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"), - _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"), - _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"), - _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"), - _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"), - _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"), - _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"), - _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"), - _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"), - _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"), - _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"), - _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"), - _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"), - _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"), - _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"), - _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"), - _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"), - _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"), - _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"), - _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"), - _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL), - _OMAP3_BALLENTRY(SIM_IO, "p27", NULL), - _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL), - _OMAP3_BALLENTRY(SIM_RST, "r25", NULL), - _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL), - _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), - _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), - _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), - _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL), - _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL), - _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL), - _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL), - _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL), - _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL), - _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL), - _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL), - _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL), - _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL), - _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL), - _OMAP3_BALLENTRY(UART1_RX, "y8", NULL), - _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL), - _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL), - _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL), - _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL), - _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL), - _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL), - _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL), - _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL), - _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap36xx_cbp_ball NULL -#endif - -int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) -{ - struct omap_mux *package_subset; - struct omap_ball *package_balls; - - switch (flags & OMAP_PACKAGE_MASK) { - case (OMAP_PACKAGE_CBC): - package_subset = omap3_cbc_subset; - package_balls = omap3_cbc_ball; - break; - case (OMAP_PACKAGE_CBB): - package_subset = omap3_cbb_subset; - package_balls = omap3_cbb_ball; - break; - case (OMAP_PACKAGE_CUS): - package_subset = omap3_cus_subset; - package_balls = omap3_cus_ball; - break; - case (OMAP_PACKAGE_CBP): - package_subset = omap36xx_cbp_subset; - package_balls = omap36xx_cbp_ball; - break; - default: - printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); - return -EINVAL; - } - - return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, - OMAP3_CONTROL_PADCONF_MUX_SIZE, - omap3_muxmodes, package_subset, board_subset, - package_balls); -} diff --git a/trunk/arch/arm/mach-omap2/mux34xx.h b/trunk/arch/arm/mach-omap2/mux34xx.h deleted file mode 100644 index 6543ebf8ecfc..000000000000 --- a/trunk/arch/arm/mach-omap2/mux34xx.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU - -#define OMAP3_MUX(mode0, mux_value) \ -{ \ - .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \ - .value = (mux_value), \ -} - -/* - * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing - * - * Extracted from the TRM. Add 0x48002030 to these values to get the - * absolute addresses. The name in the macro is the mode-0 name of - * the pin. NOTE: These registers are 16-bits wide. - * - * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead - * of CHASSIS for some registers. For the defines, we follow the - * 36XX naming, and use SDMMC and CHASSIS. - */ -#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000 -#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002 -#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004 -#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006 -#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008 -#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a -#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c -#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e -#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010 -#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012 -#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014 -#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016 -#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018 -#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a -#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c -#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e -#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020 -#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022 -#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024 -#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026 -#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028 -#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a -#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c -#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e -#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030 -#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032 -#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034 -#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036 -#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 -#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a -#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c -#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e -#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040 -#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042 -#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044 -#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046 -#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048 -#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a -#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c -#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e -#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050 -#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052 -#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054 -#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056 -#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058 -#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a -#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c -#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e -#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060 -#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062 -#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064 -#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066 -#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068 -#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a -#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c -#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e -#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070 -#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072 -#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074 -#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076 -#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078 -#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a -#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c -#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e -#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080 -#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082 -#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084 -#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086 -#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088 -#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a -#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c -#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e -#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090 -#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092 -#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094 -#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096 -#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098 -#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a -#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c -#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e -#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0 -#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2 -#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4 -#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6 -#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8 -#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa -#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac -#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae -#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0 -#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2 -#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4 -#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6 -#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8 -#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba -#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc -#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be -#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0 -#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2 -#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4 -#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6 -#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8 -#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca -#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc -#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce -#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0 -#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2 -#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4 -#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6 -#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8 -#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da -#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc -#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de -#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0 -#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2 -#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4 -#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6 -#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8 -#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea -#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec -#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee -#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0 -#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2 -#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4 -#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6 -#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8 -#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa -#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc -#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe -#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100 -#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102 -#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104 -#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106 -#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108 -#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a -#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c -#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e -#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110 -#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112 -#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114 -#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116 -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118 -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e - -/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */ -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120 -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122 -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124 -#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126 - -#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128 -#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130 -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132 -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134 -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136 -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138 -#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a -#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c -#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e -#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140 -#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142 -#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144 -#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146 -#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148 -#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a -#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c -#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e -#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150 -#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152 -#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154 -#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156 -#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158 -#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a -#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c -#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e -#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160 -#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162 -#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164 -#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166 -#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168 -#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a -#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c -#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e -#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170 -#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172 -#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176 -#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186 -#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188 -#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a -#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c -#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e -#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190 -#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192 -#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194 -#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196 -#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198 -#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a -#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c -#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e -#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0 -#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2 -#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4 -#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6 -#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8 -#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa -#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac -#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae -#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0 -#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8 -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa -#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc - -/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */ -#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe -#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200 -#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202 -#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204 -#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206 -#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208 -#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a -#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c -#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e -#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210 -#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212 -#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214 -#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216 -#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218 -#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a -#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c -#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e -#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220 -#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222 -#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224 - -#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226 -#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228 -#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a -#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c -#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e -#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230 -#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232 -#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234 - -/* 36xx only */ -#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236 -#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570 -#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572 -#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574 -#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576 -#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578 -#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a -#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c -#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e -#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580 -#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582 -#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584 -#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586 -#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588 -#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a -#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c -#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e -#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590 -#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592 -#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594 -#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596 -#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598 -#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a -#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c -#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e -#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0 -#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2 -#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4 - -/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */ -#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120 -#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122 -#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124 -#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126 - -#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8 -#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa -#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac -#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae -#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0 -#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2 -#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4 -#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6 -#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8 -#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba -#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc -#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be -#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0 -#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2 -#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4 -#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6 -#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8 -#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca -#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0 -#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2 -#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4 -#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6 -#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8 -#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da -#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc -#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de -#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0 -#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2 -#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4 -#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6 -#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8 -#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea -#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec -#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee -#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0 -#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2 -#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4 -#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6 -#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c -#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e -#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20 - -#define OMAP3_CONTROL_PADCONF_MUX_SIZE \ - (OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2) diff --git a/trunk/arch/arm/mach-omap2/omap-headsmp.S b/trunk/arch/arm/mach-omap2/omap-headsmp.S index aa3f65c2ac97..4afadba09477 100644 --- a/trunk/arch/arm/mach-omap2/omap-headsmp.S +++ b/trunk/arch/arm/mach-omap2/omap-headsmp.S @@ -27,39 +27,20 @@ * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. - * The primary core will update this flag using a hardware - * register AuxCoreBoot0. + * The primary core will update the this flag using a hardware + * register AuxCoreBoot1. */ ENTRY(omap_secondary_startup) -hold: ldr r12,=0x103 - dsb - smc @ read from AuxCoreBoot0 - mov r0, r0, lsr #9 - mrc p15, 0, r4, c0, c0, 5 - and r4, r4, #0x0f - cmp r0, r4 + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #0x0f +hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1 + ldr r2, [r1] + cmp r2, r0 bne hold /* - * we've been released from the wait loop,secondary_stack + * we've been released from the cpu_release,secondary_stack * should now contain the SVC stack for this core */ b secondary_startup -END(omap_secondary_startup) - -ENTRY(omap_modify_auxcoreboot0) - stmfd sp!, {r1-r12, lr} - ldr r12, =0x104 - dsb - smc - ldmfd sp!, {r1-r12, pc} -END(omap_modify_auxcoreboot0) - -ENTRY(omap_auxcoreboot_addr) - stmfd sp!, {r2-r12, lr} - ldr r12, =0x105 - dsb - smc - ldmfd sp!, {r2-r12, pc} -END(omap_auxcoreboot_addr) diff --git a/trunk/arch/arm/mach-omap2/omap-smp.c b/trunk/arch/arm/mach-omap2/omap-smp.c index 38153e5fbca0..4890bcf4dadd 100644 --- a/trunk/arch/arm/mach-omap2/omap-smp.c +++ b/trunk/arch/arm/mach-omap2/omap-smp.c @@ -17,15 +17,19 @@ */ #include #include +#include #include #include -#include #include #include #include #include +/* Registers used for communicating startup information */ +static void __iomem *omap4_auxcoreboot_reg0; +static void __iomem *omap4_auxcoreboot_reg1; + /* SCU base address */ static void __iomem *scu_base; @@ -61,6 +65,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { + unsigned long timeout; + /* * Set synchronisation state between this boot processor * and the secondary one @@ -68,15 +74,18 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) spin_lock(&boot_lock); /* - * Update the AuxCoreBoot0 with boot state for secondary core. + * Update the AuxCoreBoot1 with boot state for secondary core. * omap_secondary_startup() routine will hold the secondary core till * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ - omap_modify_auxcoreboot0(0x200, 0x0); - flush_cache_all(); + __raw_writel(cpu, omap4_auxcoreboot_reg1); smp_wmb(); + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) + ; + /* * Now the secondary core is starting up let it run its * calibrations, then wait for it to finish @@ -90,18 +99,17 @@ static void __init wakeup_secondary(void) { /* * Write the address of secondary startup routine into the - * AuxCoreBoot1 where ROM code will jump and start executing + * AuxCoreBoot0 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); + __raw_writel(virt_to_phys(omap_secondary_startup), \ + omap4_auxcoreboot_reg0); smp_wmb(); /* * Send a 'sev' to wake the secondary core from WFE. - * Drain the outstanding writes to memory */ - dsb(); set_event(); mb(); } @@ -128,6 +136,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) { unsigned int ncores = get_core_count(); unsigned int cpu = smp_processor_id(); + void __iomem *omap4_wkupgen_base; int i; /* sanity check */ @@ -159,6 +168,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus) for (i = 0; i < max_cpus; i++) set_cpu_present(i, true); + /* Never released */ + omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); + BUG_ON(!omap4_wkupgen_base); + omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800; + omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804; + if (max_cpus > 1) { /* * Enable the local timer or broadcast device for the diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index d8c8545875b1..633b216a8b26 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -45,7 +45,6 @@ #include #include -#include #include #include #include @@ -210,32 +209,6 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) return 0; } -/** - * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v - * @oh: struct omap_hwmod * - * @autoidle: desired AUTOIDLE bitfield value (0 or 1) - * @v: pointer to register contents to modify - * - * Update the module autoidle bit in @v to be @autoidle for the @oh - * hwmod. The autoidle bit controls whether the module can gate - * internal clocks automatically when it isn't doing anything; the - * exact function of this bit varies on a per-module basis. This - * function does not write to the hardware. Returns -EINVAL upon - * error or 0 upon success. - */ -static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, - u32 *v) -{ - if (!oh->sysconfig || - !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)) - return -EINVAL; - - *v &= ~SYSC_AUTOIDLE_MASK; - *v |= autoidle << SYSC_AUTOIDLE_SHIFT; - - return 0; -} - /** * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware * @oh: struct omap_hwmod * @@ -353,9 +326,6 @@ static int _init_main_clk(struct omap_hwmod *oh) ret = -EINVAL; oh->_clk = c; - WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n", - oh->clkdev_con_id, c->name); - return ret; } @@ -587,19 +557,8 @@ static void _sysc_enable(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } - if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) { - idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? - 0 : 1; - _set_module_autoidle(oh, idlemode, &v); - } - - /* XXX OCP ENAWAKEUP bit? */ + /* XXX OCP AUTOIDLE bit? */ - /* - * XXX The clock framework should handle this, by - * calling into this code. But this must wait until the - * clock structures are tagged with omap_hwmod entries - */ if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) _set_clockactivity(oh, oh->sysconfig->clockact, &v); @@ -663,8 +622,7 @@ static void _sysc_shutdown(struct omap_hwmod *oh) if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); - if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) - _set_module_autoidle(oh, 1, &v); + /* XXX clear OCP AUTOIDLE bit? */ _write_sysconfig(v, oh); } @@ -778,7 +736,7 @@ static int _wait_target_ready(struct omap_hwmod *oh) static int _reset(struct omap_hwmod *oh) { u32 r, v; - int c = 0; + int c; if (!oh->sysconfig || !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || @@ -800,9 +758,13 @@ static int _reset(struct omap_hwmod *oh) return r; _write_sysconfig(v, oh); - omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & - SYSS_RESETDONE_MASK), - MAX_MODULE_RESET_WAIT, c); + c = 0; + while (c < MAX_MODULE_RESET_WAIT && + !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & + SYSS_RESETDONE_MASK)) { + udelay(1); + c++; + } if (c == MAX_MODULE_RESET_WAIT) WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", @@ -921,6 +883,33 @@ static int _shutdown(struct omap_hwmod *oh) return 0; } +/** + * _write_clockact_lock - set the module's clockactivity bits + * @oh: struct omap_hwmod * + * @clockact: CLOCKACTIVITY field bits + * + * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh + * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the + * wrong state or returns 0. + */ +static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact) +{ + u32 v; + + if (!oh->sysconfig || + !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) + return -EINVAL; + + mutex_lock(&omap_hwmod_mutex); + v = oh->_sysc_cache; + _set_clockactivity(oh, clockact, &v); + _write_sysconfig(v, oh); + mutex_unlock(&omap_hwmod_mutex); + + return 0; +} + + /** * _setup - do initial configuration of omap_hwmod * @oh: struct omap_hwmod * @@ -959,19 +948,11 @@ static int _setup(struct omap_hwmod *oh) _enable(oh); - if (!(oh->flags & HWMOD_INIT_NO_RESET)) { - /* - * XXX Do the OCP_SYSCONFIG bits need to be - * reprogrammed after a reset? If not, then this can - * be removed. If they do, then probably the - * _enable() function should be split to avoid the - * rewrite of the OCP_SYSCONFIG register. - */ - if (oh->sysconfig) { - _update_sysc_cache(oh); - _sysc_enable(oh); - } - } + if (!(oh->flags & HWMOD_INIT_NO_RESET)) + _reset(oh); + + /* XXX OCP AUTOIDLE bit? */ + /* XXX OCP ENAWAKEUP bit? */ if (!(oh->flags & HWMOD_INIT_NO_IDLE)) _idle(oh); @@ -1367,9 +1348,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) /* For each IRQ, DMA, memory area, fill in array.*/ for (i = 0; i < oh->mpu_irqs_cnt; i++) { - (res + r)->name = (oh->mpu_irqs + i)->name; - (res + r)->start = (oh->mpu_irqs + i)->irq; - (res + r)->end = (oh->mpu_irqs + i)->irq; + (res + r)->start = *(oh->mpu_irqs + i); + (res + r)->end = *(oh->mpu_irqs + i); (res + r)->flags = IORESOURCE_IRQ; r++; } @@ -1473,6 +1453,62 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, return _del_initiator_dep(oh, init_oh); } +/** + * omap_hwmod_set_clockact_none - set clockactivity test to BOTH + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to MAIN + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to ICLK + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK); +} + +/** + * omap_hwmod_set_clockact_none - set clockactivity test to NONE + * @oh: struct omap_hwmod * + * + * On some modules, this function can affect the wakeup latency vs. + * power consumption balance. Intended to be called by the + * omap_device layer. Passes along the return value from + * _write_clockact_lock(). + */ +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh) +{ + return _write_clockact_lock(oh, CLOCKACT_TEST_NONE); +} + /** * omap_hwmod_enable_wakeup - allow device to wake up the system * @oh: struct omap_hwmod * diff --git a/trunk/arch/arm/mach-omap2/opp2420_data.c b/trunk/arch/arm/mach-omap2/opp2420_data.c deleted file mode 100644 index 126a9396b3a8..000000000000 --- a/trunk/arch/arm/mach-omap2/opp2420_data.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * opp2420_data.c - old-style "OPP" table for OMAP2420 - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Richard Woodruff - * - * The OMAP2 processor can be run at several discrete 'PRCM configurations'. - * These configurations are characterized by voltage and speed for clocks. - * The device is only validated for certain combinations. One way to express - * these combinations is via the 'ratio's' which the clocks operate with - * respect to each other. These ratio sets are for a given voltage/DPLL - * setting. All configurations can be described by a DPLL setting and a ratio - * There are 3 ratio sets for the 2430 and X ratio sets for 2420. - * - * 2430 differs from 2420 in that there are no more phase synchronizers used. - * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs - * 2430 (iva2.1, NOdsp, mdm) - * - * XXX Missing voltage data. - * - * THe format described in this file is deprecated. Once a reasonable - * OPP API exists, the data in this file should be converted to use it. - * - * This is technically part of the OMAP2xxx clock code. - */ - -#include "opp2xxx.h" -#include "sdrc.h" -#include "clock.h" - -/*------------------------------------------------------------------------- - * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, - * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, - * CM_CLKSEL2_PLL, CM_CLKSEL_MDM - * - * Filling in table based on H4 boards and 2430-SDPs variants available. - * There are quite a few more rates combinations which could be defined. - * - * When multiple values are defined the start up will try and choose the - * fastest one. If a 'fast' value is defined, then automatically, the /2 - * one should be included as it can be used. Generally having more that - * one fast set does not make sense, as static timings need to be changed - * to change the set. The exception is the bypass setting which is - * availble for low power bypass. - * - * Note: This table needs to be sorted, fastest to slowest. - *-------------------------------------------------------------------------*/ -const struct prcm_config omap2420_rate_table[] = { - /* PRCM I - FAST */ - {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ - RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, - RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, - RATE_IN_242X}, - - /* PRCM II - FAST */ - {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, - RATE_IN_242X}, - - {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, - RATE_IN_242X}, - - /* PRCM III - FAST */ - {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, - RATE_IN_242X}, - - {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, - RATE_IN_242X}, - - /* PRCM II - SLOW */ - {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, - RATE_IN_242X}, - - {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ - RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, - RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, - RATE_IN_242X}, - - /* PRCM III - SLOW */ - {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, - RATE_IN_242X}, - - {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ - RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, - RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, - RATE_IN_242X}, - - /* PRCM-VII (boot-bypass) */ - {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ - RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, - RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, - RATE_IN_242X}, - - /* PRCM-VII (boot-bypass) */ - {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ - RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, - RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, - RATE_IN_242X}, - - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; diff --git a/trunk/arch/arm/mach-omap2/opp2430_data.c b/trunk/arch/arm/mach-omap2/opp2430_data.c deleted file mode 100644 index edb81672c844..000000000000 --- a/trunk/arch/arm/mach-omap2/opp2430_data.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * opp2420_data.c - old-style "OPP" table for OMAP2420 - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Richard Woodruff - * - * The OMAP2 processor can be run at several discrete 'PRCM configurations'. - * These configurations are characterized by voltage and speed for clocks. - * The device is only validated for certain combinations. One way to express - * these combinations is via the 'ratio's' which the clocks operate with - * respect to each other. These ratio sets are for a given voltage/DPLL - * setting. All configurations can be described by a DPLL setting and a ratio - * There are 3 ratio sets for the 2430 and X ratio sets for 2420. - * - * 2430 differs from 2420 in that there are no more phase synchronizers used. - * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs - * 2430 (iva2.1, NOdsp, mdm) - * - * XXX Missing voltage data. - * - * THe format described in this file is deprecated. Once a reasonable - * OPP API exists, the data in this file should be converted to use it. - * - * This is technically part of the OMAP2xxx clock code. - */ - -#include "opp2xxx.h" -#include "sdrc.h" -#include "clock.h" - -/*------------------------------------------------------------------------- - * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, - * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, - * CM_CLKSEL2_PLL, CM_CLKSEL_MDM - * - * Filling in table based on H4 boards and 2430-SDPs variants available. - * There are quite a few more rates combinations which could be defined. - * - * When multiple values are defined the start up will try and choose the - * fastest one. If a 'fast' value is defined, then automatically, the /2 - * one should be included as it can be used. Generally having more that - * one fast set does not make sense, as static timings need to be changed - * to change the set. The exception is the bypass setting which is - * availble for low power bypass. - * - * Note: This table needs to be sorted, fastest to slowest. - *-------------------------------------------------------------------------*/ -const struct prcm_config omap2430_rate_table[] = { - /* PRCM #4 - ratio2 (ES2.1) - FAST */ - {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ - R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, - R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_133MHz, - RATE_IN_243X}, - - /* PRCM #2 - ratio1 (ES2) - FAST */ - {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_165MHz, - RATE_IN_243X}, - - /* PRCM #5a - ratio1 - FAST */ - {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_133MHz, - RATE_IN_243X}, - - /* PRCM #5b - ratio1 - FAST */ - {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_100MHz, - RATE_IN_243X}, - - /* PRCM #4 - ratio1 (ES2.1) - SLOW */ - {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ - R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, - R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_133MHz, - RATE_IN_243X}, - - /* PRCM #2 - ratio1 (ES2) - SLOW */ - {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_165MHz, - RATE_IN_243X}, - - /* PRCM #5a - ratio1 - SLOW */ - {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_133MHz, - RATE_IN_243X}, - - /* PRCM #5b - ratio1 - SLOW*/ - {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ - R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, - R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_100MHz, - RATE_IN_243X}, - - /* PRCM-boot/bypass */ - {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ - RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, - RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, - MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_BYPASS, - RATE_IN_243X}, - - /* PRCM-boot/bypass */ - {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ - RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, - RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, - MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, - SDRC_RFR_CTRL_BYPASS, - RATE_IN_243X}, - - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, -}; diff --git a/trunk/arch/arm/mach-omap2/opp2xxx.h b/trunk/arch/arm/mach-omap2/opp2xxx.h deleted file mode 100644 index ed6df04e2f29..000000000000 --- a/trunk/arch/arm/mach-omap2/opp2xxx.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Richard Woodruff - * - * The OMAP2 processor can be run at several discrete 'PRCM configurations'. - * These configurations are characterized by voltage and speed for clocks. - * The device is only validated for certain combinations. One way to express - * these combinations is via the 'ratio's' which the clocks operate with - * respect to each other. These ratio sets are for a given voltage/DPLL - * setting. All configurations can be described by a DPLL setting and a ratio - * There are 3 ratio sets for the 2430 and X ratio sets for 2420. - * - * 2430 differs from 2420 in that there are no more phase synchronizers used. - * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs - * 2430 (iva2.1, NOdsp, mdm) - * - * XXX Missing voltage data. - * - * THe format described in this file is deprecated. Once a reasonable - * OPP API exists, the data in this file should be converted to use it. - * - * This is technically part of the OMAP2xxx clock code. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H -#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H - -/** - * struct prcm_config - define clock rates on a per-OPP basis (24xx) - * - * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. - * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP - * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM - * - * This is deprecated. As soon as we have a decent OPP API, we should - * move all this stuff to it. - */ -struct prcm_config { - unsigned long xtal_speed; /* crystal rate */ - unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ - unsigned long mpu_speed; /* speed of MPU */ - unsigned long cm_clksel_mpu; /* mpu divider */ - unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ - unsigned long cm_clksel_gfx; /* gfx dividers */ - unsigned long cm_clksel1_core; /* major subsystem dividers */ - unsigned long cm_clksel1_pll; /* m,n */ - unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ - unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ - unsigned long base_sdrc_rfr; /* base refresh timing for a set */ - unsigned char flags; -}; - - -/* Core fields for cm_clksel, not ratio governed */ -#define RX_CLKSEL_DSS1 (0x10 << 8) -#define RX_CLKSEL_DSS2 (0x0 << 13) -#define RX_CLKSEL_SSI (0x5 << 20) - -/*------------------------------------------------------------------------- - * Voltage/DPLL ratios - *-------------------------------------------------------------------------*/ - -/* 2430 Ratio's, 2430-Ratio Config 1 */ -#define R1_CLKSEL_L3 (4 << 0) -#define R1_CLKSEL_L4 (2 << 5) -#define R1_CLKSEL_USB (4 << 25) -#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ - R1_CLKSEL_L4 | R1_CLKSEL_L3) -#define R1_CLKSEL_MPU (2 << 0) -#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU -#define R1_CLKSEL_DSP (2 << 0) -#define R1_CLKSEL_DSP_IF (2 << 5) -#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) -#define R1_CLKSEL_GFX (2 << 0) -#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX -#define R1_CLKSEL_MDM (4 << 0) -#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM - -/* 2430-Ratio Config 2 */ -#define R2_CLKSEL_L3 (6 << 0) -#define R2_CLKSEL_L4 (2 << 5) -#define R2_CLKSEL_USB (2 << 25) -#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ - R2_CLKSEL_L4 | R2_CLKSEL_L3) -#define R2_CLKSEL_MPU (2 << 0) -#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU -#define R2_CLKSEL_DSP (2 << 0) -#define R2_CLKSEL_DSP_IF (3 << 5) -#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) -#define R2_CLKSEL_GFX (2 << 0) -#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX -#define R2_CLKSEL_MDM (6 << 0) -#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM - -/* 2430-Ratio Bootm (BYPASS) */ -#define RB_CLKSEL_L3 (1 << 0) -#define RB_CLKSEL_L4 (1 << 5) -#define RB_CLKSEL_USB (1 << 25) -#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ - RB_CLKSEL_L4 | RB_CLKSEL_L3) -#define RB_CLKSEL_MPU (1 << 0) -#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU -#define RB_CLKSEL_DSP (1 << 0) -#define RB_CLKSEL_DSP_IF (1 << 5) -#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) -#define RB_CLKSEL_GFX (1 << 0) -#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX -#define RB_CLKSEL_MDM (1 << 0) -#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM - -/* 2420 Ratio Equivalents */ -#define RXX_CLKSEL_VLYNQ (0x12 << 15) -#define RXX_CLKSEL_SSI (0x8 << 20) - -/* 2420-PRCM III 532MHz core */ -#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ -#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ -#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ -#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ - RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ - RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ - RIII_CLKSEL_L3) -#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ -#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU -#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ -#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ -#define RIII_SYNC_DSP (1 << 7) /* Enable sync */ -#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ -#define RIII_SYNC_IVA (1 << 13) /* Enable sync */ -#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ - RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ - RIII_CLKSEL_DSP) -#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ -#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX - -/* 2420-PRCM II 600MHz core */ -#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ -#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ -#define RII_CLKSEL_USB (2 << 25) /* 50MHz */ -#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ - RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ - RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ - RII_CLKSEL_L3) -#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ -#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU -#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ -#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ -#define RII_SYNC_DSP (0 << 7) /* Bypass sync */ -#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ -#define RII_SYNC_IVA (0 << 13) /* Bypass sync */ -#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ - RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ - RII_CLKSEL_DSP) -#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ -#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX - -/* 2420-PRCM I 660MHz core */ -#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ -#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ -#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ -#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ - RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ - RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ - RI_CLKSEL_L4 | RI_CLKSEL_L3) -#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ -#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU -#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ -#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ -#define RI_SYNC_DSP (1 << 7) /* Activate sync */ -#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ -#define RI_SYNC_IVA (0 << 13) /* Bypass sync */ -#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ - RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ - RI_CLKSEL_DSP) -#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ -#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX - -/* 2420-PRCM VII (boot) */ -#define RVII_CLKSEL_L3 (1 << 0) -#define RVII_CLKSEL_L4 (1 << 5) -#define RVII_CLKSEL_DSS1 (1 << 8) -#define RVII_CLKSEL_DSS2 (0 << 13) -#define RVII_CLKSEL_VLYNQ (1 << 15) -#define RVII_CLKSEL_SSI (1 << 20) -#define RVII_CLKSEL_USB (1 << 25) - -#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ - RVII_CLKSEL_VLYNQ | \ - RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ - RVII_CLKSEL_L4 | RVII_CLKSEL_L3) - -#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ -#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU - -#define RVII_CLKSEL_DSP (1 << 0) -#define RVII_CLKSEL_DSP_IF (1 << 5) -#define RVII_SYNC_DSP (0 << 7) -#define RVII_CLKSEL_IVA (1 << 8) -#define RVII_SYNC_IVA (0 << 13) -#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ - RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ - RVII_CLKSEL_DSP) - -#define RVII_CLKSEL_GFX (1 << 0) -#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX - -/*------------------------------------------------------------------------- - * 2430 Target modes: Along with each configuration the CPU has several - * modes which goes along with them. Modes mainly are the addition of - * describe DPLL combinations to go along with a ratio. - *-------------------------------------------------------------------------*/ - -/* Hardware governed */ -#define MX_48M_SRC (0 << 3) -#define MX_54M_SRC (0 << 5) -#define MX_APLLS_CLIKIN_12 (3 << 23) -#define MX_APLLS_CLIKIN_13 (2 << 23) -#define MX_APLLS_CLIKIN_19_2 (0 << 23) - -/* - * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed - * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz - */ -#define M5A_DPLL_MULT_12 (133 << 12) -#define M5A_DPLL_DIV_12 (5 << 8) -#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) -#define M5A_DPLL_MULT_13 (61 << 12) -#define M5A_DPLL_DIV_13 (2 << 8) -#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) -#define M5A_DPLL_MULT_19 (55 << 12) -#define M5A_DPLL_DIV_19 (3 << 8) -#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ - MX_APLLS_CLIKIN_19_2) -/* #5b (ratio1) target DPLL = 200*2 = 400MHz */ -#define M5B_DPLL_MULT_12 (50 << 12) -#define M5B_DPLL_DIV_12 (2 << 8) -#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) -#define M5B_DPLL_MULT_13 (200 << 12) -#define M5B_DPLL_DIV_13 (12 << 8) - -#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) -#define M5B_DPLL_MULT_19 (125 << 12) -#define M5B_DPLL_DIV_19 (31 << 8) -#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ - MX_APLLS_CLIKIN_19_2) -/* - * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz - */ -#define M4_DPLL_MULT_12 (133 << 12) -#define M4_DPLL_DIV_12 (3 << 8) -#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) - -#define M4_DPLL_MULT_13 (399 << 12) -#define M4_DPLL_DIV_13 (12 << 8) -#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) - -#define M4_DPLL_MULT_19 (145 << 12) -#define M4_DPLL_DIV_19 (6 << 8) -#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ - MX_APLLS_CLIKIN_19_2) - -/* - * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz - */ -#define M3_DPLL_MULT_12 (55 << 12) -#define M3_DPLL_DIV_12 (1 << 8) -#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) -#define M3_DPLL_MULT_13 (76 << 12) -#define M3_DPLL_DIV_13 (2 << 8) -#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) -#define M3_DPLL_MULT_19 (17 << 12) -#define M3_DPLL_DIV_19 (0 << 8) -#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ - MX_APLLS_CLIKIN_19_2) - -/* - * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz - */ -#define M2_DPLL_MULT_12 (55 << 12) -#define M2_DPLL_DIV_12 (1 << 8) -#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) - -/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, - * relock time issue */ -/* Core frequency changed from 330/165 to 329/164 MHz*/ -#define M2_DPLL_MULT_13 (76 << 12) -#define M2_DPLL_DIV_13 (2 << 8) -#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) - -#define M2_DPLL_MULT_19 (17 << 12) -#define M2_DPLL_DIV_19 (0 << 8) -#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ - MX_APLLS_CLIKIN_19_2) - -/* boot (boot) */ -#define MB_DPLL_MULT (1 << 12) -#define MB_DPLL_DIV (0 << 8) -#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - MB_DPLL_DIV | MB_DPLL_MULT | \ - MX_APLLS_CLIKIN_12) - -#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - MB_DPLL_DIV | MB_DPLL_MULT | \ - MX_APLLS_CLIKIN_13) - -#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ - MB_DPLL_DIV | MB_DPLL_MULT | \ - MX_APLLS_CLIKIN_19) - -/* - * 2430 - chassis (sedna) - * 165 (ratio1) same as above #2 - * 150 (ratio1) - * 133 (ratio2) same as above #4 - * 110 (ratio2) same as above #3 - * 104 (ratio2) - * boot (boot) - */ - -/* PRCM I target DPLL = 2*330MHz = 660MHz */ -#define MI_DPLL_MULT_12 (55 << 12) -#define MI_DPLL_DIV_12 (1 << 8) -#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) - -/* - * 2420 Equivalent - mode registers - * PRCM II , target DPLL = 2*300MHz = 600MHz - */ -#define MII_DPLL_MULT_12 (50 << 12) -#define MII_DPLL_DIV_12 (1 << 8) -#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ - MX_APLLS_CLIKIN_12) -#define MII_DPLL_MULT_13 (300 << 12) -#define MII_DPLL_DIV_13 (12 << 8) -#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ - MX_APLLS_CLIKIN_13) - -/* PRCM III target DPLL = 2*266 = 532MHz*/ -#define MIII_DPLL_MULT_12 (133 << 12) -#define MIII_DPLL_DIV_12 (5 << 8) -#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ - MIII_DPLL_DIV_12 | \ - MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) -#define MIII_DPLL_MULT_13 (266 << 12) -#define MIII_DPLL_DIV_13 (12 << 8) -#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ - MIII_DPLL_DIV_13 | \ - MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) - -/* PRCM VII (boot bypass) */ -#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL -#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL - -/* High and low operation value */ -#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) -#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) - -/* MPU speed defines */ -#define S12M 12000000 -#define S13M 13000000 -#define S19M 19200000 -#define S26M 26000000 -#define S100M 100000000 -#define S133M 133000000 -#define S150M 150000000 -#define S164M 164000000 -#define S165M 165000000 -#define S199M 199000000 -#define S200M 200000000 -#define S266M 266000000 -#define S300M 300000000 -#define S329M 329000000 -#define S330M 330000000 -#define S399M 399000000 -#define S400M 400000000 -#define S532M 532000000 -#define S600M 600000000 -#define S658M 658000000 -#define S660M 660000000 -#define S798M 798000000 - - -extern const struct prcm_config omap2420_rate_table[]; -extern const struct prcm_config omap2430_rate_table[]; -extern const struct prcm_config *rate_table; -extern const struct prcm_config *curr_prcm_set; - -#endif diff --git a/trunk/arch/arm/mach-omap2/pm-debug.c b/trunk/arch/arm/mach-omap2/pm-debug.c index 860b755d2220..8baa30d2acfb 100644 --- a/trunk/arch/arm/mach-omap2/pm-debug.c +++ b/trunk/arch/arm/mach-omap2/pm-debug.c @@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set) return 0; } -static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { +static const char pwrdm_state_names[][4] = { "OFF", "RET", "INA", @@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) seq_printf(s, "%s (%s)", pwrdm->name, pwrdm_state_names[pwrdm->state]); - for (i = 0; i < PWRDM_MAX_PWRSTS; i++) + for (i = 0; i < 4; i++) seq_printf(s, ",%s:%d", pwrdm_state_names[i], pwrdm->state_counter[i]); diff --git a/trunk/arch/arm/mach-omap2/powerdomain.c b/trunk/arch/arm/mach-omap2/powerdomain.c index 26b3f3ee82a3..b6990e377783 100644 --- a/trunk/arch/arm/mach-omap2/powerdomain.c +++ b/trunk/arch/arm/mach-omap2/powerdomain.c @@ -10,7 +10,9 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#undef DEBUG +#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN +# define DEBUG +#endif #include #include @@ -158,7 +160,7 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm) { int i; - for (i = 0; i < PWRDM_MAX_PWRSTS; i++) + for (i = 0; i < 4; i++) pwrdm->state_counter[i] = 0; pwrdm_wait_transition(pwrdm); @@ -478,7 +480,7 @@ int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) if (IS_ERR(p)) { pr_debug("powerdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n", @@ -511,7 +513,7 @@ int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) if (IS_ERR(p)) { pr_debug("powerdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } pr_debug("powerdomain: hardware will no longer wake up %s after %s " @@ -548,7 +550,7 @@ int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) if (IS_ERR(p)) { pr_debug("powerdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP, @@ -571,10 +573,10 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) { struct powerdomain *p; - if (!cpu_is_omap34xx()) + if (!pwrdm1) return -EINVAL; - if (!pwrdm1) + if (!cpu_is_omap34xx()) return -EINVAL; p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); @@ -582,7 +584,7 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) pr_debug("powerdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n", @@ -610,10 +612,10 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) { struct powerdomain *p; - if (!cpu_is_omap34xx()) + if (!pwrdm1) return -EINVAL; - if (!pwrdm1) + if (!cpu_is_omap34xx()) return -EINVAL; p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); @@ -621,7 +623,7 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) pr_debug("powerdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } pr_debug("powerdomain: will no longer prevent %s from sleeping if " @@ -653,10 +655,10 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) { struct powerdomain *p; - if (!cpu_is_omap34xx()) + if (!pwrdm1) return -EINVAL; - if (!pwrdm1) + if (!cpu_is_omap34xx()) return -EINVAL; p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs); @@ -664,7 +666,7 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2) pr_debug("powerdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", pwrdm1->name, pwrdm2->name); - return PTR_ERR(p); + return IS_ERR(p); } return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP, @@ -983,9 +985,6 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) if (pwrdm->banks < (bank + 1)) return -EEXIST; - if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) - bank = 1; - /* * The register bit names below may not correspond to the * actual names of the bits in each powerdomain's register, @@ -1033,9 +1032,6 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) if (pwrdm->banks < (bank + 1)) return -EEXIST; - if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) - bank = 1; - /* * The register bit names below may not correspond to the * actual names of the bits in each powerdomain's register, diff --git a/trunk/arch/arm/mach-omap2/powerdomains34xx.h b/trunk/arch/arm/mach-omap2/powerdomains34xx.h index 588f7e07d0ea..fd09b0827df0 100644 --- a/trunk/arch/arm/mach-omap2/powerdomains34xx.h +++ b/trunk/arch/arm/mach-omap2/powerdomains34xx.h @@ -190,7 +190,6 @@ static struct powerdomain mpu_34xx_pwrdm = { .wkdep_srcs = mpu_34xx_wkdeps, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, - .flags = PWRDM_HAS_MPU_QUIRK, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, diff --git a/trunk/arch/arm/mach-omap2/prcm-common.h b/trunk/arch/arm/mach-omap2/prcm-common.h index 61ac2a418bd0..cb1ae84e0925 100644 --- a/trunk/arch/arm/mach-omap2/prcm-common.h +++ b/trunk/arch/arm/mach-omap2/prcm-common.h @@ -4,12 +4,10 @@ /* * OMAP2/3 PRCM base and module definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley - * OMAP4 defines in this file are automatically generated from the OMAP hardware - * databases. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -51,73 +49,6 @@ #define OMAP3430_NEON_MOD 0xb00 #define OMAP3430ES2_USBHOST_MOD 0xc00 -#define BITS(n_bit) \ - (((1 << n_bit) - 1) | (1 << n_bit)) - -#define BITFIELD(l_bit, u_bit) \ - (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) - -/* OMAP44XX specific module offsets */ - -/* CM1 instances */ - -#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_CM1_CKGEN_MOD 0x0100 -#define OMAP4430_CM1_MPU_MOD 0x0300 -#define OMAP4430_CM1_TESLA_MOD 0x0400 -#define OMAP4430_CM1_ABE_MOD 0x0500 -#define OMAP4430_CM1_RESTORE_MOD 0x0e00 -#define OMAP4430_CM1_INSTR_MOD 0x0f00 - -/* CM2 instances */ - -#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_CM2_CKGEN_MOD 0x0100 -#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 -#define OMAP4430_CM2_CORE_MOD 0x0700 -#define OMAP4430_CM2_IVAHD_MOD 0x0f00 -#define OMAP4430_CM2_CAM_MOD 0x1000 -#define OMAP4430_CM2_DSS_MOD 0x1100 -#define OMAP4430_CM2_GFX_MOD 0x1200 -#define OMAP4430_CM2_L3INIT_MOD 0x1300 -#define OMAP4430_CM2_L4PER_MOD 0x1400 -#define OMAP4430_CM2_CEFUSE_MOD 0x1600 -#define OMAP4430_CM2_RESTORE_MOD 0x1e00 -#define OMAP4430_CM2_INSTR_MOD 0x1f00 - -/* PRM instances */ - -#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 -#define OMAP4430_PRM_CKGEN_MOD 0x0100 -#define OMAP4430_PRM_MPU_MOD 0x0300 -#define OMAP4430_PRM_TESLA_MOD 0x0400 -#define OMAP4430_PRM_ABE_MOD 0x0500 -#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 -#define OMAP4430_PRM_CORE_MOD 0x0700 -#define OMAP4430_PRM_IVAHD_MOD 0x0f00 -#define OMAP4430_PRM_CAM_MOD 0x1000 -#define OMAP4430_PRM_DSS_MOD 0x1100 -#define OMAP4430_PRM_GFX_MOD 0x1200 -#define OMAP4430_PRM_L3INIT_MOD 0x1300 -#define OMAP4430_PRM_L4PER_MOD 0x1400 -#define OMAP4430_PRM_CEFUSE_MOD 0x1600 -#define OMAP4430_PRM_WKUP_MOD 0x1700 -#define OMAP4430_PRM_WKUP_CM_MOD 0x1800 -#define OMAP4430_PRM_EMU_MOD 0x1900 -#define OMAP4430_PRM_EMU_CM_MOD 0x1a00 -#define OMAP4430_PRM_DEVICE_MOD 0x1b00 -#define OMAP4430_PRM_INSTR_MOD 0x1f00 - -/* SCRM instances */ - -#define OMAP4430_SCRM_SCRM_MOD 0x0000 - -/* CHIRONSS instances */ - -#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000 -#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200 -#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400 -#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800 /* 24XX register bits shared between CM & PRM registers */ diff --git a/trunk/arch/arm/mach-omap2/prcm.c b/trunk/arch/arm/mach-omap2/prcm.c index 3ea8177ffb25..029d376198d4 100644 --- a/trunk/arch/arm/mach-omap2/prcm.c +++ b/trunk/arch/arm/mach-omap2/prcm.c @@ -34,7 +34,6 @@ static void __iomem *prm_base; static void __iomem *cm_base; -static void __iomem *cm2_base; #define MAX_MODULE_ENABLE_WAIT 100000 @@ -171,12 +170,14 @@ u32 prm_read_mod_reg(s16 module, u16 idx) { return __omap_prcm_read(prm_base, module, idx); } +EXPORT_SYMBOL(prm_read_mod_reg); /* Write into a register in a PRM module */ void prm_write_mod_reg(u32 val, s16 module, u16 idx) { __omap_prcm_write(val, prm_base, module, idx); } +EXPORT_SYMBOL(prm_write_mod_reg); /* Read-modify-write a register in a PRM module. Caller must lock */ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) @@ -190,18 +191,21 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) return v; } +EXPORT_SYMBOL(prm_rmw_mod_reg_bits); /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { return __omap_prcm_read(cm_base, module, idx); } +EXPORT_SYMBOL(cm_read_mod_reg); /* Write into a register in a CM module */ void cm_write_mod_reg(u32 val, s16 module, u16 idx) { __omap_prcm_write(val, cm_base, module, idx); } +EXPORT_SYMBOL(cm_write_mod_reg); /* Read-modify-write a register in a CM module. Caller must lock */ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) @@ -215,6 +219,7 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) return v; } +EXPORT_SYMBOL(cm_rmw_mod_reg_bits); /** * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness @@ -242,8 +247,9 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name) BUG(); /* Wait for lock */ - omap_test_timeout(((__raw_readl(reg) & mask) == ena), - MAX_MODULE_ENABLE_WAIT, i); + while (((__raw_readl(reg) & mask) != ena) && + (i++ < MAX_MODULE_ENABLE_WAIT)) + udelay(1); if (i < MAX_MODULE_ENABLE_WAIT) pr_debug("cm: Module associated with clock %s ready after %d " @@ -259,7 +265,6 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) { prm_base = omap2_globals->prm; cm_base = omap2_globals->cm; - cm2_base = omap2_globals->cm2; } #ifdef CONFIG_ARCH_OMAP3 diff --git a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h b/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h deleted file mode 100644 index 301c810fb269..000000000000 --- a/trunk/arch/arm/mach-omap2/prm-regbits-44xx.h +++ /dev/null @@ -1,2205 +0,0 @@ -/* - * OMAP44xx Power Management register bits - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H - -#include "prm.h" - - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT (1 << 1) -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT (1 << 2) -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_ABB_IVA_DONE_EN_SHIFT (1 << 31) -#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_ABB_IVA_DONE_ST_SHIFT (1 << 31) -#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_EN_SHIFT (1 << 7) -#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_ST_SHIFT (1 << 7) -#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_FBB_SEL_SHIFT (1 << 2) -#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_RBB_SEL_SHIFT (1 << 1) -#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_AESSMEM_STATEST_SHIFT (1 << 4) -#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_AIPOFF_SHIFT (1 << 8) -#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT (1 << 0) -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT (1 << 4) -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT (1 << 2) -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) - -/* Used by PM_CAM_PWRSTCTRL */ -#define OMAP4430_CAM_MEM_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_CAM_PWRSTST */ -#define OMAP4430_CAM_MEM_STATEST_SHIFT (1 << 4) -#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) - -/* Used by PRM_CLKREQCTRL */ -#define OMAP4430_CLKREQ_COND_SHIFT (1 << 0) -#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT (1 << 0) -#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT (1 << 8) -#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT (1 << 16) -#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_CORE_L_SHIFT (1 << 4) -#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_IVA_L_SHIFT (1 << 12) -#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_MPU_L_SHIFT (1 << 17) -#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT (1 << 18) -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT (1 << 9) -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT (1 << 6) -#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT (1 << 4) -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_DATA_SHIFT (1 << 16) -#define OMAP4430_DATA_MASK BITFIELD(16, 23) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT (1 << 0) -#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_DFILTEREN_SHIFT (1 << 6) -#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) - -/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT (1 << 4) -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) - -/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT (1 << 4) -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT (1 << 0) -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT (1 << 0) -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT (1 << 6) -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT (1 << 6) -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT (1 << 2) -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT (1 << 2) -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT (1 << 1) -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT (1 << 1) -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT (1 << 3) -#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT (1 << 3) -#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT (1 << 7) -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT (1 << 7) -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT (1 << 5) -#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT (1 << 5) -#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_DSS_PWRSTST */ -#define OMAP4430_DSS_MEM_STATEST_SHIFT (1 << 4) -#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT (1 << 20) -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT (1 << 10) -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT (1 << 8) -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT (1 << 22) -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT (1 << 11) -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT (1 << 10) -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_EMULATION_RST_SHIFT (1 << 0) -#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST1ST_SHIFT (1 << 3) -#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST2ST_SHIFT (1 << 4) -#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT (1 << 3) -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT (1 << 4) -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) - -/* Used by PM_EMU_PWRSTCTRL */ -#define OMAP4430_EMU_BANK_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_EMU_PWRSTST */ -#define OMAP4430_EMU_BANK_STATEST_SHIFT (1 << 4) -#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT (1 << 0) -#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC1_SHIFT (1 << 3) -#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC3_SHIFT (1 << 5) -#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC4_SHIFT (1 << 6) -#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC5_SHIFT (1 << 7) -#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERRORGAIN_SHIFT (1 << 16) -#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERROROFFSET_SHIFT (1 << 24) -#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) - -/* Used by PRM_RSTST */ -#define OMAP4430_EXTERNAL_WARM_RST_SHIFT (1 << 5) -#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_FORCEUPDATE_SHIFT (1 << 1) -#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_FORCEUPDATEWAIT_SHIFT (1 << 8) -#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ -#define OMAP4430_FORCEWKUP_EN_SHIFT (1 << 10) -#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_FORCEWKUP_ST_SHIFT (1 << 10) -#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) - -/* Used by PM_GFX_PWRSTCTRL */ -#define OMAP4430_GFX_MEM_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_GFX_PWRSTST */ -#define OMAP4430_GFX_MEM_STATEST_SHIFT (1 << 4) -#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) - -/* Used by PRM_RSTST */ -#define OMAP4430_GLOBAL_COLD_RST_SHIFT (1 << 0) -#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) - -/* Used by PRM_RSTST */ -#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT (1 << 1) -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_GLOBAL_WUEN_SHIFT (1 << 16) -#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMCODE_SHIFT (1 << 0) -#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMODEEN_SHIFT (1 << 3) -#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLH_SHIFT (1 << 16) -#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLL_SHIFT (1 << 24) -#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_HWA_MEM_STATEST_SHIFT (1 << 4) -#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT (1 << 1) -#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST1ST_SHIFT (1 << 5) -#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST2ST_SHIFT (1 << 6) -#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT (1 << 5) -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT (1 << 6) -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) - -/* Used by PRM_RSTST */ -#define OMAP4430_ICEPICK_RST_SHIFT (1 << 9) -#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVDD_SHIFT (1 << 2) -#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVOLTAGE_SHIFT (1 << 8) -#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) - -/* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST - */ -#define OMAP4430_INTRANSITION_SHIFT (1 << 20) -#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_IO_EN_SHIFT (1 << 9) -#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_IO_ON_STATUS_SHIFT (1 << 5) -#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_IO_ST_SHIFT (1 << 9) -#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_OVERRIDE_SHIFT (1 << 0) -#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_STATUS_SHIFT (1 << 1) -#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOOVR_EXTEND_SHIFT (1 << 4) -#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) - -/* Used by PRM_IO_COUNT */ -#define OMAP4430_ISO_2_ON_TIME_SHIFT (1 << 0) -#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT (1 << 4) -#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL - */ -#define OMAP4430_LOGICRETSTATE_SHIFT (1 << 2) -#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) - -/* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST - */ -#define OMAP4430_LOGICSTATEST_SHIFT (1 << 2) -#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) - -/* - * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, - * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, - * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, - * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, - * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, - * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, - * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, - * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, - * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, - * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, - * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, - * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, - * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, - * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, - * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, - * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, - * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, - * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, - * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, - * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, - * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, - * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_DFF_SHIFT (1 << 0) -#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, - * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, - * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, - * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, - * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, - * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, - * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, - * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_RFF_SHIFT (1 << 1) -#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) - -/* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP4430_LOSTMEM_AESSMEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) - -/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) - -/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) - -/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT (1 << 9) -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) - -/* Used by RM_L3_2_OCMC_RAM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, - * RM_SDMA_SDMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) - -/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT (1 << 9) -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) - -/* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) - -/* Used by RM_GFX_GFX_CONTEXT */ -#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT (1 << 10) -#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) - -/* - * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, - * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT - */ -#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L1_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L2_SHIFT (1 << 9) -#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT (1 << 10) -#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) - -/* - * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT - */ -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) - -/* - * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, - * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT - */ -#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) - -/* - * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_CRYPTODMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) - -/* Used by RM_IVAHD_SL2_CONTEXT */ -#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT (1 << 9) -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT (1 << 10) -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT (1 << 9) -#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) - -/* Used by RM_WKUP_SARRAM_CONTEXT */ -#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT (1 << 8) -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) - -/* - * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, - * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL - */ -#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT (1 << 4) -#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_MEMORYCHANGE_SHIFT (1 << 3) -#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_READY_SHIFT (1 << 1) -#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT (1 << 9) -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SLEEP_ST_SHIFT (1 << 16) -#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_WAKE_IRQ_SHIFT (1 << 8) -#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L1_STATEST_SHIFT (1 << 4) -#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_ONSTATE_SHIFT (1 << 18) -#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_RETSTATE_SHIFT (1 << 9) -#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L2_STATEST_SHIFT (1 << 6) -#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_ONSTATE_SHIFT (1 << 20) -#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_RETSTATE_SHIFT (1 << 10) -#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_RAM_STATEST_SHIFT (1 << 8) -#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) - -/* Used by PRM_RSTST */ -#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT (1 << 2) -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) - -/* Used by PRM_RSTST */ -#define OMAP4430_MPU_WDT_RST_SHIFT (1 << 3) -#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT (1 << 18) -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT (1 << 9) -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT (1 << 6) -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT (1 << 24) -#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT (1 << 12) -#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT (1 << 12) -#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP4430_OFF_SHIFT (1 << 0) -#define OMAP4430_OFF_MASK BITFIELD(0, 7) - -/* Used by PRM_LDO_BANDGAP_CTRL */ -#define OMAP4430_OFF_ENABLE_SHIFT (1 << 0) -#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP4430_ON_SHIFT (1 << 24) -#define OMAP4430_ON_MASK BITFIELD(24, 31) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP4430_ONLP_SHIFT (1 << 16) -#define OMAP4430_ONLP_MASK BITFIELD(16, 23) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_CHANGE_SHIFT (1 << 2) -#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_SEL_SHIFT (1 << 0) -#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_PCHARGECNT_VALUE_SHIFT (1 << 0) -#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PCHARGE_TIME_SHIFT (1 << 0) -#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT (1 << 20) -#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT (1 << 10) -#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_PERIPHMEM_STATEST_SHIFT (1 << 8) -#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) - -/* Used by PRM_PHASE1_CNDP */ -#define OMAP4430_PHASE1_CNDP_SHIFT (1 << 0) -#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) - -/* Used by PRM_PHASE2A_CNDP */ -#define OMAP4430_PHASE2A_CNDP_SHIFT (1 << 0) -#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) - -/* Used by PRM_PHASE2B_CNDP */ -#define OMAP4430_PHASE2B_CNDP_SHIFT (1 << 0) -#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT (1 << 8) -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) - -/* - * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, - * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL - */ -#define OMAP4430_POWERSTATE_SHIFT (1 << 0) -#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) - -/* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST - */ -#define OMAP4430_POWERSTATEST_SHIFT (1 << 0) -#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) - -/* Used by PRM_PWRREQCTRL */ -#define OMAP4430_PWRREQ_COND_SHIFT (1 << 0) -#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_CORE_L_SHIFT (1 << 3) -#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_IVA_L_SHIFT (1 << 11) -#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_MPU_L_SHIFT (1 << 20) -#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_CORE_L_SHIFT (1 << 2) -#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_IVA_L_SHIFT (1 << 10) -#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_MPU_L_SHIFT (1 << 19) -#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_DOWN_COUNT_SHIFT (1 << 16) -#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT (1 << 24) -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_UP_COUNT_SHIFT (1 << 0) -#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_UP_PRESCAL_SHIFT (1 << 8) -#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_CORE_L_SHIFT (1 << 1) -#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_IVA_L_SHIFT (1 << 9) -#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_MPU_L_SHIFT (1 << 18) -#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_REGADDR_SHIFT (1 << 8) -#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP4430_RET_SHIFT (1 << 8) -#define OMAP4430_RET_MASK BITFIELD(8, 15) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_RETAINED_BANK_STATEST_SHIFT (1 << 4) -#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_RETMODE_ENABLE_SHIFT (1 << 0) -#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) - -/* Used by REVISION_PRM */ -#define OMAP4430_REV_SHIFT (1 << 0) -#define OMAP4430_REV_MASK BITFIELD(0, 7) - -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST1_SHIFT (1 << 0) -#define OMAP4430_RST1_MASK BITFIELD(0, 0) - -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST1ST_SHIFT (1 << 0) -#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) - -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST2_SHIFT (1 << 1) -#define OMAP4430_RST2_MASK BITFIELD(1, 1) - -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST2ST_SHIFT (1 << 1) -#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST3_SHIFT (1 << 2) -#define OMAP4430_RST3_MASK BITFIELD(2, 2) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST3ST_SHIFT (1 << 2) -#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME1_SHIFT (1 << 0) -#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME2_SHIFT (1 << 10) -#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT (1 << 1) -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT (1 << 0) -#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_CORE_L_SHIFT (1 << 0) -#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) - -/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT (1 << 0) -#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_IVA_L_SHIFT (1 << 8) -#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) - -/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT (1 << 8) -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_SA_VDD_MPU_L_SHIFT (1 << 16) -#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) - -/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT (1 << 16) -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_SCLH_SHIFT (1 << 0) -#define OMAP4430_SCLH_MASK BITFIELD(0, 7) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_SCLL_SHIFT (1 << 8) -#define OMAP4430_SCLL_MASK BITFIELD(8, 15) - -/* Used by PRM_RSTST */ -#define OMAP4430_SECURE_WDT_RST_SHIFT (1 << 4) -#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_ONSTATE_SHIFT (1 << 18) -#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_RETSTATE_SHIFT (1 << 9) -#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_SL2_MEM_STATEST_SHIFT (1 << 6) -#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_SLAVEADDR_SHIFT (1 << 0) -#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SLEEP_RBB_SEL_SHIFT (1 << 3) -#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_SLPCNT_VALUE_SHIFT (1 << 16) -#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP4430_SMPSWAITTIMEMAX_SHIFT (1 << 8) -#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP4430_SMPSWAITTIMEMIN_SHIFT (1 << 8) -#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2EN_SHIFT (1 << 0) -#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_IN_TRANSITION_SHIFT (1 << 6) -#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_STATUS_SHIFT (1 << 3) -#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2_WTCNT_VALUE_SHIFT (1 << 8) -#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAMLDO_STATUS_SHIFT (1 << 8) -#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAM_IN_TRANSITION_SHIFT (1 << 9) -#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_SRMODEEN_SHIFT (1 << 4) -#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_COUNT_SHIFT (1 << 0) -#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_PRESCAL_SHIFT (1 << 8) -#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT (1 << 20) -#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT (1 << 10) -#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM1_MEM_STATEST_SHIFT (1 << 8) -#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT (1 << 22) -#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT (1 << 11) -#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM2_MEM_STATEST_SHIFT (1 << 10) -#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLASS_EMU_RSTST_SHIFT (1 << 2) -#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT (1 << 3) -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT (1 << 20) -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT (1 << 10) -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_EDMA_STATEST_SHIFT (1 << 8) -#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_ONSTATE_SHIFT (1 << 16) -#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_RETSTATE_SHIFT (1 << 8) -#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L1_STATEST_SHIFT (1 << 4) -#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_ONSTATE_SHIFT (1 << 18) -#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_RETSTATE_SHIFT (1 << 9) -#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L2_STATEST_SHIFT (1 << 6) -#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_TIMEOUT_SHIFT (1 << 0) -#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_TIMEOUTEN_SHIFT (1 << 3) -#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_TRANSITION_EN_SHIFT (1 << 8) -#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_TRANSITION_ST_SHIFT (1 << 8) -#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_VALID_SHIFT (1 << 24) -#define OMAP4430_VALID_MASK BITFIELD(24, 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_BYPASSACK_EN_SHIFT (1 << 14) -#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_BYPASSACK_ST_SHIFT (1 << 14) -#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_IVA_VPACK_EN_SHIFT (1 << 30) -#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_IVA_VPACK_ST_SHIFT (1 << 30) -#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_EN_SHIFT (1 << 6) -#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_ST_SHIFT (1 << 6) -#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_RAERR_EN_SHIFT (1 << 12) -#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_RAERR_ST_SHIFT (1 << 12) -#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_SAERR_EN_SHIFT (1 << 11) -#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_SAERR_ST_SHIFT (1 << 11) -#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_TOERR_EN_SHIFT (1 << 13) -#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_TOERR_ST_SHIFT (1 << 13) -#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_VDDMAX_SHIFT (1 << 24) -#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP4430_VDDMIN_SHIFT (1 << 16) -#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT (1 << 12) -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) - -/* Used by PRM_RSTST */ -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT (1 << 8) -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT (1 << 14) -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_PRESENCE_SHIFT (1 << 9) -#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) - -/* Used by PRM_RSTST */ -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT (1 << 7) -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT (1 << 13) -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_PRESENCE_SHIFT (1 << 8) -#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) - -/* Used by PRM_RSTST */ -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT (1 << 6) -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT (1 << 0) -#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT (1 << 8) -#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT (1 << 16) -#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_VPENABLE_SHIFT (1 << 0) -#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) - -/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP4430_VPINIDLE_SHIFT (1 << 0) -#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_VPVOLTAGE_SHIFT (1 << 0) -#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT (1 << 20) -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT (1 << 20) -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT (1 << 18) -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT (1 << 18) -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT (1 << 17) -#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT (1 << 17) -#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT (1 << 19) -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT (1 << 19) -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT (1 << 16) -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT (1 << 16) -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT (1 << 21) -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT (1 << 21) -#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT (1 << 28) -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT (1 << 28) -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT (1 << 26) -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT (1 << 26) -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT (1 << 25) -#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT (1 << 25) -#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT (1 << 27) -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT (1 << 27) -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT (1 << 24) -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT (1 << 24) -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT (1 << 29) -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT (1 << 29) -#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT (1 << 4) -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT (1 << 4) -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT (1 << 2) -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT (1 << 2) -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT (1 << 1) -#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT (1 << 1) -#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT (1 << 3) -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT (1 << 3) -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT (1 << 0) -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT (1 << 0) -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT (1 << 5) -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT (1 << 5) -#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_VSETUPCNT_VALUE_SHIFT (1 << 8) -#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP4430_VSTEPMAX_SHIFT (1 << 0) -#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP4430_VSTEPMIN_SHIFT (1 << 0) -#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_WAKE_MODEM_SHIFT (1 << 0) -#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_DMTIMER10_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_DMTIMER2_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT (1 << 5) -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT (1 << 4) -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT (1 << 9) -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT (1 << 8) -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT (1 << 11) -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT (1 << 10) -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT (1 << 19) -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT (1 << 13) -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT (1 << 12) -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT (1 << 14) -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) - -/* Used by PM_L4PER_HECC1_WKDEP */ -#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_HECC2_WKDEP */ -#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_KEYBOARD_WKDEP */ -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_WKUP_RTC_WKDEP */ -#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT (1 << 7) -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT (1 << 6) -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ALWON_SR_MPU_WKDEP */ -#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_TIMER12_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_TIMER1_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT (1 << 2) -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT (1 << 3) -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_ABE_WDT3_WKDEP */ -#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT (1 << 0) -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT (1 << 8) -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) - -/* Used by PM_L3INIT_XHPI_WKDEP */ -#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT (1 << 1) -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_CTRL_SHIFT (1 << 8) -#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_STATUS_SHIFT (1 << 9) -#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) -#endif diff --git a/trunk/arch/arm/mach-omap2/prm.h b/trunk/arch/arm/mach-omap2/prm.h index ea050ce188a7..a117f853ea39 100644 --- a/trunk/arch/arm/mach-omap2/prm.h +++ b/trunk/arch/arm/mach-omap2/prm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Power/Reset Management (PRM) register definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation * * Written by Paul Walmsley * @@ -22,10 +22,6 @@ OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) -#define OMAP44XX_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) - -#include "prm44xx.h" /* * Architecture-specific global PRM registers diff --git a/trunk/arch/arm/mach-omap2/prm44xx.h b/trunk/arch/arm/mach-omap2/prm44xx.h deleted file mode 100644 index 89be97f0589d..000000000000 --- a/trunk/arch/arm/mach-omap2/prm44xx.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * OMAP44xx PRM instance offset macros - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H - - -/* PRM */ - - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) -#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) -#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) -#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) -#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) -#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) -#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) -#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) -#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) -#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) - -/* PRM.CKGEN_PRM register offsets */ -#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) -#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) -#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) -#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) -#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) - -/* PRM.MPU_PRM register offsets */ -#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) -#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) -#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) -#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) - -/* PRM.TESLA_PRM register offsets */ -#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) -#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) -#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) -#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) -#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) - -/* PRM.ABE_PRM register offsets */ -#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) -#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) -#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) -#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) -#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) -#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) -#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) -#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) -#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) -#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) -#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) -#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) -#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) -#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) -#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) -#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) -#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) -#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) -#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) -#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) -#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) -#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) -#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) -#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) -#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) -#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) -#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) - -/* PRM.ALWAYS_ON_PRM register offsets */ -#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) -#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) -#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) -#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) -#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) -#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) -#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) - -/* PRM.CORE_PRM register offsets */ -#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) -#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) -#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) -#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) -#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) -#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) -#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) -#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) -#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) -#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) -#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) -#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) -#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) -#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) -#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) -#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) -#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) -#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) -#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) -#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) -#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) -#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) -#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) -#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) -#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) -#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) -#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) -#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) - -/* PRM.IVAHD_PRM register offsets */ -#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) -#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) -#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) -#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) -#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) -#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) - -/* PRM.CAM_PRM register offsets */ -#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) -#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) -#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) -#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) - -/* PRM.DSS_PRM register offsets */ -#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) -#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) -#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) -#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) -#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) - -/* PRM.GFX_PRM register offsets */ -#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) -#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) -#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) - -/* PRM.L3INIT_PRM register offsets */ -#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) -#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) -#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) -#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) -#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) -#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) -#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) -#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) -#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) -#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) -#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) -#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) -#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) -#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) -#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) -#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) -#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) -#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) -#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) -#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) -#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) -#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) -#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) -#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) -#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) -#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) -#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) -#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) -#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) -#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) -#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) - -/* PRM.L4PER_PRM register offsets */ -#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) -#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) -#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) -#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) -#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) -#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) -#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) -#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) -#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) -#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) -#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) -#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) -#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) -#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) -#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) -#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) -#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) -#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) -#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) -#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) -#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) -#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) -#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) -#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) -#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) -#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) -#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) -#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) -#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) -#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) -#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) -#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) -#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) -#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) -#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) -#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) -#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) -#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) -#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) -#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) -#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) -#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) -#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) -#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) -#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) -#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) -#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) -#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) -#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) -#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) -#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) -#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) -#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) -#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) -#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) -#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) -#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) -#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) -#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) -#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) -#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) -#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) -#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) -#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) -#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) -#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) -#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) -#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) -#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) -#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) -#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) -#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) -#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) -#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) -#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) -#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) -#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) -#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) -#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) -#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) -#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) - -/* PRM.CEFUSE_PRM register offsets */ -#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) -#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) -#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) - -/* PRM.WKUP_PRM register offsets */ -#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) -#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) -#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) -#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) -#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) -#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) -#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) -#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) -#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) -#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) -#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) -#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) -#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) -#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) -#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) -#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) -#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) -#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) - -/* PRM.WKUP_CM register offsets */ -#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) -#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) -#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) -#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) -#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) -#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) -#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) -#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) -#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) -#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) -#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) -#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) -#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) - -/* PRM.EMU_PRM register offsets */ -#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) -#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) -#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) - -/* PRM.EMU_CM register offsets */ -#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) -#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) -#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) - -/* PRM.DEVICE_PRM register offsets */ -#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) -#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) -#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) -#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) -#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) -#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) -#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) -#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) -#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) -#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) -#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) -#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) -#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) -#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) -#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) -#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) -#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) -#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) -#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) -#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) -#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) -#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) -#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) -#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) -#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) -#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) -#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) -#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) -#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) -#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) -#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) -#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) -#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) -#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) -#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) -#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) -#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) -#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) -#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) -#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) -#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) -#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) -#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) -#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) -#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) -#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) -#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) -#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) -#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) -#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) -#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) -#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) -#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) -#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) -#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) -#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) -#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) -#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) -#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) -#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) -#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) -#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) - -/* CHIRON_PRCM */ - - -/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ -#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) - -/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ -#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) - -/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ -#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) - -/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ -#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) -#endif diff --git a/trunk/arch/arm/mach-omap2/sdrc.h b/trunk/arch/arm/mach-omap2/sdrc.h index 68f57bb67fc5..48207b018989 100644 --- a/trunk/arch/arm/mach-omap2/sdrc.h +++ b/trunk/arch/arm/mach-omap2/sdrc.h @@ -18,9 +18,6 @@ #include #ifndef __ASSEMBLER__ - -#include - extern void __iomem *omap2_sdrc_base; extern void __iomem *omap2_sms_base; @@ -59,20 +56,4 @@ static inline u32 sms_read_reg(u16 reg) OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) #endif /* __ASSEMBLER__ */ -/* Minimum frequency that the SDRC DLL can lock at */ -#define MIN_SDRC_DLL_LOCK_FREQ 83000000 - -/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ -#define SDRC_MPURATE_SCALE 8 - -/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ -#define SDRC_MPURATE_BASE_SHIFT 9 - -/* - * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at - * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize - */ -#define SDRC_MPURATE_LOOPS 96 - - #endif diff --git a/trunk/arch/arm/mach-omap2/serial.c b/trunk/arch/arm/mach-omap2/serial.c index 39b797bc14d6..2e17b57f5b23 100644 --- a/trunk/arch/arm/mach-omap2/serial.c +++ b/trunk/arch/arm/mach-omap2/serial.c @@ -33,7 +33,6 @@ #include "pm.h" #include "prm-regbits-34xx.h" -#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ #define DEFAULT_TIMEOUT (5 * HZ) @@ -573,23 +572,6 @@ static struct omap_uart_state omap_uart[] = { #endif }; -/* - * Override the default 8250 read handler: mem_serial_in() - * Empty RX fifo read causes an abort on omap3630 and omap4 - * This function makes sure that an empty rx fifo is not read on these silicons - * (OMAP1/2/3430 are not affected) - */ -static unsigned int serial_in_override(struct uart_port *up, int offset) -{ - if (UART_RX == offset) { - unsigned int lsr; - lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR); - if (!(lsr & UART_LSR_DR)) - return -EPERM; - } - return serial_read_reg(omap_uart[up->line].p, offset); -} - void __init omap_serial_early_init(void) { int i; @@ -649,64 +631,24 @@ void __init omap_serial_early_init(void) } } -/** - * omap_serial_init_port() - initialize single serial port - * @port: serial port number (0-3) - * - * This function initialies serial driver for given @port only. - * Platforms can call this function instead of omap_serial_init() - * if they don't plan to use all available UARTs as serial ports. - * - * Don't mix calls to omap_serial_init_port() and omap_serial_init(), - * use only one of the two. - */ -void __init omap_serial_init_port(int port) +void __init omap_serial_init(void) { - struct omap_uart_state *uart; - struct platform_device *pdev; - struct device *dev; - - BUG_ON(port < 0); - BUG_ON(port >= ARRAY_SIZE(omap_uart)); - - uart = &omap_uart[port]; - pdev = &uart->pdev; - dev = &pdev->dev; + int i; - omap_uart_reset(uart); - omap_uart_idle_init(uart); + for (i = 0; i < ARRAY_SIZE(omap_uart); i++) { + struct omap_uart_state *uart = &omap_uart[i]; + struct platform_device *pdev = &uart->pdev; + struct device *dev = &pdev->dev; - if (WARN_ON(platform_device_register(pdev))) - return; + omap_uart_reset(uart); + omap_uart_idle_init(uart); - if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { - device_init_wakeup(dev, true); - DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); + if (WARN_ON(platform_device_register(pdev))) + continue; + if ((cpu_is_omap34xx() && uart->padconf) || + (uart->wk_en && uart->wk_mask)) { + device_init_wakeup(dev, true); + DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); + } } - - /* omap44xx: Never read empty UART fifo - * omap3xxx: Never read empty UART fifo on UARTs - * with IP rev >=0x52 - */ - if (cpu_is_omap44xx()) - uart->p->serial_in = serial_in_override; - else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) - uart->p->serial_in = serial_in_override; -} - -/** - * omap_serial_init() - intialize all supported serial ports - * - * Initializes all available UARTs as serial ports. Platforms - * can call this function when they want to have default behaviour - * for serial ports (e.g initialize them all as serial ports). - */ -void __init omap_serial_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(omap_uart); i++) - omap_serial_init_port(i); } diff --git a/trunk/arch/arm/mach-omap2/sram34xx.S b/trunk/arch/arm/mach-omap2/sram34xx.S index de99ba2a57ab..82aa4a3d160c 100644 --- a/trunk/arch/arm/mach-omap2/sram34xx.S +++ b/trunk/arch/arm/mach-omap2/sram34xx.S @@ -91,19 +91,8 @@ * new SDRC_ACTIM_CTRL_B_1 register contents * new SDRC_MR_1 register value * - * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into - * the SDRC CS1 registers - * - * NOTE: This code no longer attempts to program the SDRC AC timing and MR - * registers. This is because the code currently cannot ensure that all - * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the - * SDRAM when the registers are written. If the registers are changed while - * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC - * may enter an unpredictable state. In the future, the intent is to - * re-enable this code in cases where we can ensure that no initiators are - * touching the SDRAM. Until that time, users who know that their use case - * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING - * option. + * If the param SDRC_RFR_CTRL_1 is 0, the parameters + * are not programmed into the SDRC CS1 registers */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack @@ -230,7 +219,6 @@ configure_sdrc: ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM str r12, [r11] @ store -#ifdef CONFIG_OMAP3_SDRC_AC_TIMING ldr r12, omap_sdrc_actim_ctrl_a_0_val ldr r11, omap3_sdrc_actim_ctrl_a_0 str r12, [r11] @@ -240,13 +228,11 @@ configure_sdrc: ldr r12, omap_sdrc_mr_0_val ldr r11, omap3_sdrc_mr_0 str r12, [r11] -#endif ldr r12, omap_sdrc_rfr_ctrl_1_val cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, beq skip_cs1_prog @ do not program cs1 params ldr r11, omap3_sdrc_rfr_ctrl_1 str r12, [r11] -#ifdef CONFIG_OMAP3_SDRC_AC_TIMING ldr r12, omap_sdrc_actim_ctrl_a_1_val ldr r11, omap3_sdrc_actim_ctrl_a_1 str r12, [r11] @@ -256,7 +242,6 @@ configure_sdrc: ldr r12, omap_sdrc_mr_1_val ldr r11, omap3_sdrc_mr_1 str r12, [r11] -#endif skip_cs1_prog: ldr r12, [r11] @ posted-write barrier for SDRC bx lr diff --git a/trunk/arch/arm/mach-omap2/usb-ehci.c b/trunk/arch/arm/mach-omap2/usb-ehci.c index f1df873d59db..e448abd5ec5d 100644 --- a/trunk/arch/arm/mach-omap2/usb-ehci.c +++ b/trunk/arch/arm/mach-omap2/usb-ehci.c @@ -27,8 +27,6 @@ #include #include -#include "mux.h" - #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) static struct resource ehci_resources[] = { @@ -74,44 +72,32 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) { switch (port_mode[0]) { case EHCI_HCD_OMAP_MODE_PHY: - omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT); - omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT); - omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN); + omap_cfg_reg(Y9_3430_USB1HS_PHY_STP); + omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK); + omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR); + omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT); + omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0); + omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1); + omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2); + omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3); + omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4); + omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5); + omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6); + omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7); break; case EHCI_HCD_OMAP_MODE_TLL: - omap_mux_init_signal("hsusb1_tll_stp", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("hsusb1_tll_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb1_tll_data7", - OMAP_PIN_INPUT_PULLDOWN); + omap_cfg_reg(Y9_3430_USB1HS_TLL_STP); + omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK); + omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR); + omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT); + omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0); + omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1); + omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2); + omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3); + omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4); + omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5); + omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6); + omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7); break; case EHCI_HCD_OMAP_MODE_UNKNOWN: /* FALLTHROUGH */ @@ -121,52 +107,32 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) switch (port_mode[1]) { case EHCI_HCD_OMAP_MODE_PHY: - omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT); - omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT); - omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_data7", - OMAP_PIN_INPUT_PULLDOWN); + omap_cfg_reg(AA10_3430_USB2HS_PHY_STP); + omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK); + omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR); + omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT); + omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0); + omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1); + omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2); + omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3); + omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4); + omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5); + omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6); + omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7); break; case EHCI_HCD_OMAP_MODE_TLL: - omap_mux_init_signal("hsusb2_tll_stp", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("hsusb2_tll_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb2_tll_data7", - OMAP_PIN_INPUT_PULLDOWN); + omap_cfg_reg(AA10_3430_USB2HS_TLL_STP); + omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK); + omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR); + omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT); + omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0); + omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1); + omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2); + omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3); + omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4); + omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5); + omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6); + omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7); break; case EHCI_HCD_OMAP_MODE_UNKNOWN: /* FALLTHROUGH */ @@ -179,30 +145,18 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); break; case EHCI_HCD_OMAP_MODE_TLL: - omap_mux_init_signal("hsusb3_tll_stp", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("hsusb3_tll_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("hsusb3_tll_data7", - OMAP_PIN_INPUT_PULLDOWN); + omap_cfg_reg(AB3_3430_USB3HS_TLL_STP); + omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK); + omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR); + omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT); + omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0); + omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1); + omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2); + omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3); + omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4); + omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5); + omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6); + omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7); break; case EHCI_HCD_OMAP_MODE_UNKNOWN: /* FALLTHROUGH */ diff --git a/trunk/arch/arm/mach-pxa/Kconfig b/trunk/arch/arm/mach-pxa/Kconfig index e6d8e10ae5d1..d89c6adbe8bc 100644 --- a/trunk/arch/arm/mach-pxa/Kconfig +++ b/trunk/arch/arm/mach-pxa/Kconfig @@ -63,15 +63,6 @@ config ARCH_VIPER select HAVE_PWM select PXA_HAVE_BOARD_IRQS select PXA_HAVE_ISA_IRQS - select ARCOM_PCMCIA - -config MACH_ARCOM_ZEUS - bool "Arcom/Eurotech ZEUS SBC" - select PXA27x - select ISA - select PXA_HAVE_BOARD_IRQS - select PXA_HAVE_ISA_IRQS - select ARCOM_PCMCIA config MACH_BALLOON3 bool "Balloon 3 board" @@ -188,11 +179,6 @@ config MACH_TRIZEPS_ANY endchoice -config ARCOM_PCMCIA - bool - help - Generic option for Arcom Viper/Zeus PCMCIA - config TRIZEPS_PCMCIA bool help diff --git a/trunk/arch/arm/mach-pxa/Makefile b/trunk/arch/arm/mach-pxa/Makefile index f64afda7e6f6..b5d29e60a341 100644 --- a/trunk/arch/arm/mach-pxa/Makefile +++ b/trunk/arch/arm/mach-pxa/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_MACH_SAAR) += saar.o # 3rd Party Dev Platforms obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_ARCH_VIPER) += viper.o -obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o obj-$(CONFIG_MACH_BALLOON3) += balloon3.o obj-$(CONFIG_MACH_CSB726) += csb726.o obj-$(CONFIG_CSB726_CSB701) += csb701.o diff --git a/trunk/arch/arm/mach-pxa/em-x270.c b/trunk/arch/arm/mach-pxa/em-x270.c index c8a01bc85fde..1c0de808b54d 100644 --- a/trunk/arch/arm/mach-pxa/em-x270.c +++ b/trunk/arch/arm/mach-pxa/em-x270.c @@ -497,15 +497,16 @@ static int em_x270_usb_hub_init(void) goto err_free_vbus_gpio; /* USB Hub power-on and reset */ - gpio_direction_output(usb_hub_reset, 1); - gpio_direction_output(GPIO9_USB_VBUS_EN, 0); + gpio_direction_output(usb_hub_reset, 0); regulator_enable(em_x270_usb_ldo); - gpio_set_value(usb_hub_reset, 0); gpio_set_value(usb_hub_reset, 1); + gpio_set_value(usb_hub_reset, 0); regulator_disable(em_x270_usb_ldo); regulator_enable(em_x270_usb_ldo); - gpio_set_value(usb_hub_reset, 0); - gpio_set_value(GPIO9_USB_VBUS_EN, 1); + gpio_set_value(usb_hub_reset, 1); + + /* enable VBUS */ + gpio_direction_output(GPIO9_USB_VBUS_EN, 1); return 0; diff --git a/trunk/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h b/trunk/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h deleted file mode 100644 index d428be4db44c..000000000000 --- a/trunk/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ARCOM_PCMCIA_H -#define __ARCOM_PCMCIA_H - -struct arcom_pcmcia_pdata { - int cd_gpio; - int rdy_gpio; - int pwr_gpio; - void (*reset)(int state); -}; - -#endif diff --git a/trunk/arch/arm/mach-pxa/include/mach/viper.h b/trunk/arch/arm/mach-pxa/include/mach/viper.h index 5f5fbf1f6489..10988c270ca3 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/viper.h +++ b/trunk/arch/arm/mach-pxa/include/mach/viper.h @@ -85,6 +85,8 @@ /* Interrupt and Configuration Register (VIPER_ICR) */ /* This is a write only register. Only CF_RST is used under Linux */ +extern void viper_cf_rst(int state); + #define VIPER_ICR_RETRIG (1 << 0) #define VIPER_ICR_AUTO_CLR (1 << 1) #define VIPER_ICR_R_DIS (1 << 2) diff --git a/trunk/arch/arm/mach-pxa/include/mach/zeus.h b/trunk/arch/arm/mach-pxa/include/mach/zeus.h deleted file mode 100644 index c387046d2f28..000000000000 --- a/trunk/arch/arm/mach-pxa/include/mach/zeus.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/zeus.h - * - * Author: David Vrabel - * Created: Sept 28, 2005 - * Copyright: Arcom Control Systems Ltd. - * - * Maintained by: Marc Zyngier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _MACH_ZEUS_H -#define _MACH_ZEUS_H - -/* Physical addresses */ -#define ZEUS_FLASH_PHYS PXA_CS0_PHYS -#define ZEUS_ETH0_PHYS PXA_CS1_PHYS -#define ZEUS_ETH1_PHYS PXA_CS2_PHYS -#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) -#define ZEUS_SRAM_PHYS PXA_CS5_PHYS -#define ZEUS_PC104IO_PHYS (0x30000000) - -#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) -#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) -#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) -#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) - -/* GPIOs */ -#define ZEUS_AC97_GPIO 0 -#define ZEUS_WAKEUP_GPIO 1 -#define ZEUS_UARTA_GPIO 9 -#define ZEUS_UARTB_GPIO 10 -#define ZEUS_UARTC_GPIO 12 -#define ZEUS_UARTD_GPIO 11 -#define ZEUS_ETH0_GPIO 14 -#define ZEUS_ISA_GPIO 17 -#define ZEUS_BKLEN_GPIO 19 -#define ZEUS_USB2_PWREN_GPIO 22 -#define ZEUS_PTT_GPIO 27 -#define ZEUS_CF_CD_GPIO 35 -#define ZEUS_MMC_WP_GPIO 52 -#define ZEUS_MMC_CD_GPIO 53 -#define ZEUS_EXTGPIO_GPIO 91 -#define ZEUS_CF_PWEN_GPIO 97 -#define ZEUS_CF_RDY_GPIO 99 -#define ZEUS_LCD_EN_GPIO 101 -#define ZEUS_ETH1_GPIO 113 -#define ZEUS_CAN_GPIO 116 - -#define ZEUS_EXT0_GPIO_BASE 128 -#define ZEUS_EXT1_GPIO_BASE 160 -#define ZEUS_USER_GPIO_BASE 192 - -#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) -#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) -#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) - -/* - * CPLD registers: - * Only 4 registers, but spreaded over a 32MB address space. - * Be gentle, and remap that over 32kB... - */ - -#define ZEUS_CPLD (0xf0000000) -#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) -#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) -#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) -#define ZEUS_CPLD_EXTWDOG (ZEUS_CPLD + 0x3000) - -/* CPLD register bits */ -#define ZEUS_CPLD_CONTROL_CF_RST 0x01 - -#define ZEUS_PC104IO (0xf1000000) - -#define ZEUS_SRAM_SIZE (256 * 1024) - -#endif - - diff --git a/trunk/arch/arm/mach-pxa/viper.c b/trunk/arch/arm/mach-pxa/viper.c index 5352b4e5a7dd..cf0d71b7797e 100644 --- a/trunk/arch/arm/mach-pxa/viper.c +++ b/trunk/arch/arm/mach-pxa/viper.c @@ -47,7 +47,6 @@ #include #include #include -#include #include #include @@ -77,28 +76,14 @@ static void viper_icr_clear_bit(unsigned int bit) } /* This function is used from the pcmcia module to reset the CF */ -static void viper_cf_reset(int state) +void viper_cf_rst(int state) { if (state) viper_icr_set_bit(VIPER_ICR_CF_RST); else viper_icr_clear_bit(VIPER_ICR_CF_RST); } - -static struct arcom_pcmcia_pdata viper_pcmcia_info = { - .cd_gpio = VIPER_CF_CD_GPIO, - .rdy_gpio = VIPER_CF_RDY_GPIO, - .pwr_gpio = VIPER_CF_POWER_GPIO, - .reset = viper_cf_reset, -}; - -static struct platform_device viper_pcmcia_device = { - .name = "viper-pcmcia", - .id = -1, - .dev = { - .platform_data = &viper_pcmcia_info, - }, -}; +EXPORT_SYMBOL(viper_cf_rst); /* * The CPLD version register was not present on VIPER boards prior to @@ -700,7 +685,6 @@ static struct platform_device *viper_devs[] __initdata = { &viper_mtd_devices[0], &viper_mtd_devices[1], &viper_backlight_device, - &viper_pcmcia_device, }; static mfp_cfg_t viper_pin_config[] __initdata = { diff --git a/trunk/arch/arm/mach-pxa/zeus.c b/trunk/arch/arm/mach-pxa/zeus.c deleted file mode 100644 index 5b986a8bd9e6..000000000000 --- a/trunk/arch/arm/mach-pxa/zeus.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * Support for the Arcom ZEUS. - * - * Copyright (C) 2006 Arcom Control Systems Ltd. - * - * Loosely based on Arcom's 2.6.16.28. - * Maintained by Marc Zyngier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "generic.h" - -/* - * Interrupt handling - */ - -static unsigned long zeus_irq_enabled_mask; -static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, }; -static const int zeus_isa_irq_map[] = { - 0, /* ISA irq #0, invalid */ - 0, /* ISA irq #1, invalid */ - 0, /* ISA irq #2, invalid */ - 1 << 0, /* ISA irq #3 */ - 1 << 1, /* ISA irq #4 */ - 1 << 2, /* ISA irq #5 */ - 1 << 3, /* ISA irq #6 */ - 1 << 4, /* ISA irq #7 */ - 0, /* ISA irq #8, invalid */ - 0, /* ISA irq #9, invalid */ - 1 << 5, /* ISA irq #10 */ - 1 << 6, /* ISA irq #11 */ - 1 << 7, /* ISA irq #12 */ -}; - -static inline int zeus_irq_to_bitmask(unsigned int irq) -{ - return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)]; -} - -static inline int zeus_bit_to_irq(int bit) -{ - return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); -} - -static void zeus_ack_irq(unsigned int irq) -{ - __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ); -} - -static void zeus_mask_irq(unsigned int irq) -{ - zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq)); -} - -static void zeus_unmask_irq(unsigned int irq) -{ - zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq); -} - -static inline unsigned long zeus_irq_pending(void) -{ - return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask; -} - -static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - unsigned long pending; - - pending = zeus_irq_pending(); - do { - /* we're in a chained irq handler, - * so ack the interrupt by hand */ - desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO)); - - if (likely(pending)) { - irq = zeus_bit_to_irq(__ffs(pending)); - generic_handle_irq(irq); - } - pending = zeus_irq_pending(); - } while (pending); -} - -static struct irq_chip zeus_irq_chip = { - .name = "ISA", - .ack = zeus_ack_irq, - .mask = zeus_mask_irq, - .unmask = zeus_unmask_irq, -}; - -static void __init zeus_init_irq(void) -{ - int level; - int isa_irq; - - pxa27x_init_irq(); - - /* Peripheral IRQs. It would be nice to move those inside driver - configuration, but it is not supported at the moment. */ - set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); - set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); - - /* Setup ISA IRQs */ - for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { - isa_irq = zeus_bit_to_irq(level); - set_irq_chip(isa_irq, &zeus_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); - set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); - } - - set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); -} - - -/* - * Platform devices - */ - -/* Flash */ -static struct resource zeus_mtd_resources[] = { - [0] = { /* NOR Flash (up to 64MB) */ - .start = ZEUS_FLASH_PHYS, - .end = ZEUS_FLASH_PHYS + SZ_64M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* SRAM */ - .start = ZEUS_SRAM_PHYS, - .end = ZEUS_SRAM_PHYS + SZ_512K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct physmap_flash_data zeus_flash_data[] = { - [0] = { - .width = 2, - .parts = NULL, - .nr_parts = 0, - }, -}; - -static struct platform_device zeus_mtd_devices[] = { - [0] = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &zeus_flash_data[0], - }, - .resource = &zeus_mtd_resources[0], - .num_resources = 1, - }, -}; - -/* Serial */ -static struct resource zeus_serial_resources[] = { - { - .start = 0x10000000, - .end = 0x1000000f, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x10800000, - .end = 0x1080000f, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x11000000, - .end = 0x1100000f, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x40100000, - .end = 0x4010001f, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x40200000, - .end = 0x4020001f, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x40700000, - .end = 0x4070001f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct plat_serial8250_port serial_platform_data[] = { - /* External UARTs */ - /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ - { /* COM1 */ - .mapbase = 0x10000000, - .irq = gpio_to_irq(ZEUS_UARTA_GPIO), - .irqflags = IRQF_TRIGGER_RISING, - .uartclk = 14745600, - .regshift = 1, - .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { /* COM2 */ - .mapbase = 0x10800000, - .irq = gpio_to_irq(ZEUS_UARTB_GPIO), - .irqflags = IRQF_TRIGGER_RISING, - .uartclk = 14745600, - .regshift = 1, - .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { /* COM3 */ - .mapbase = 0x11000000, - .irq = gpio_to_irq(ZEUS_UARTC_GPIO), - .irqflags = IRQF_TRIGGER_RISING, - .uartclk = 14745600, - .regshift = 1, - .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { /* COM4 */ - .mapbase = 0x11800000, - .irq = gpio_to_irq(ZEUS_UARTD_GPIO), - .irqflags = IRQF_TRIGGER_RISING, - .uartclk = 14745600, - .regshift = 1, - .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - /* Internal UARTs */ - { /* FFUART */ - .membase = (void *)&FFUART, - .mapbase = __PREG(FFUART), - .irq = IRQ_FFUART, - .uartclk = 921600 * 16, - .regshift = 2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { /* BTUART */ - .membase = (void *)&BTUART, - .mapbase = __PREG(BTUART), - .irq = IRQ_BTUART, - .uartclk = 921600 * 16, - .regshift = 2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { /* STUART */ - .membase = (void *)&STUART, - .mapbase = __PREG(STUART), - .irq = IRQ_STUART, - .uartclk = 921600 * 16, - .regshift = 2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - }, - { }, -}; - -static struct platform_device zeus_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, - .num_resources = ARRAY_SIZE(zeus_serial_resources), - .resource = zeus_serial_resources, -}; - -/* Ethernet */ -static struct resource zeus_dm9k0_resource[] = { - [0] = { - .start = ZEUS_ETH0_PHYS, - .end = ZEUS_ETH0_PHYS + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = ZEUS_ETH0_PHYS + 2, - .end = ZEUS_ETH0_PHYS + 3, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = gpio_to_irq(ZEUS_ETH0_GPIO), - .end = gpio_to_irq(ZEUS_ETH0_GPIO), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct resource zeus_dm9k1_resource[] = { - [0] = { - .start = ZEUS_ETH1_PHYS, - .end = ZEUS_ETH1_PHYS + 1, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = ZEUS_ETH1_PHYS + 2, - .end = ZEUS_ETH1_PHYS + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = gpio_to_irq(ZEUS_ETH1_GPIO), - .end = gpio_to_irq(ZEUS_ETH1_GPIO), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct dm9000_plat_data zeus_dm9k_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device zeus_dm9k0_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(zeus_dm9k0_resource), - .resource = zeus_dm9k0_resource, - .dev = { - .platform_data = &zeus_dm9k_platdata, - } -}; - -static struct platform_device zeus_dm9k1_device = { - .name = "dm9000", - .id = 1, - .num_resources = ARRAY_SIZE(zeus_dm9k1_resource), - .resource = zeus_dm9k1_resource, - .dev = { - .platform_data = &zeus_dm9k_platdata, - } -}; - -/* External SRAM */ -static struct resource zeus_sram_resource = { - .start = ZEUS_SRAM_PHYS, - .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device zeus_sram_device = { - .name = "pxa2xx-8bit-sram", - .id = 0, - .num_resources = 1, - .resource = &zeus_sram_resource, -}; - -/* SPI interface on SSP3 */ -static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { - .num_chipselect = 1, - .enable_dma = 1, -}; - -static struct platform_device pxa2xx_spi_ssp3_device = { - .name = "pxa2xx-spi", - .id = 3, - .dev = { - .platform_data = &pxa2xx_spi_ssp3_master_info, - }, -}; - -/* Leds */ -static struct gpio_led zeus_leds[] = { - [0] = { - .name = "zeus:yellow:1", - .default_trigger = "heartbeat", - .gpio = ZEUS_EXT0_GPIO(3), - .active_low = 1, - }, - [1] = { - .name = "zeus:yellow:2", - .default_trigger = "default-on", - .gpio = ZEUS_EXT0_GPIO(4), - .active_low = 1, - }, - [2] = { - .name = "zeus:yellow:3", - .default_trigger = "default-on", - .gpio = ZEUS_EXT0_GPIO(5), - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data zeus_leds_info = { - .leds = zeus_leds, - .num_leds = ARRAY_SIZE(zeus_leds), -}; - -static struct platform_device zeus_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &zeus_leds_info, - }, -}; - -static void zeus_cf_reset(int state) -{ - u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL); - - if (state) - cpld_state |= ZEUS_CPLD_CONTROL_CF_RST; - else - cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST; - - __raw_writew(cpld_state, ZEUS_CPLD_CONTROL); -} - -static struct arcom_pcmcia_pdata zeus_pcmcia_info = { - .cd_gpio = ZEUS_CF_CD_GPIO, - .rdy_gpio = ZEUS_CF_RDY_GPIO, - .pwr_gpio = ZEUS_CF_PWEN_GPIO, - .reset = zeus_cf_reset, -}; - -static struct platform_device zeus_pcmcia_device = { - .name = "zeus-pcmcia", - .id = -1, - .dev = { - .platform_data = &zeus_pcmcia_info, - }, -}; - -static struct platform_device *zeus_devices[] __initdata = { - &zeus_serial_device, - &zeus_mtd_devices[0], - &zeus_dm9k0_device, - &zeus_dm9k1_device, - &zeus_sram_device, - &pxa2xx_spi_ssp3_device, - &zeus_leds_device, - &zeus_pcmcia_device, -}; - -/* AC'97 */ -static pxa2xx_audio_ops_t zeus_ac97_info = { - .reset_gpio = 95, -}; - - -/* - * USB host - */ - -static int zeus_ohci_init(struct device *dev) -{ - int err; - - /* Switch on port 2. */ - if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) { - dev_err(dev, "Can't request USB2_PWREN\n"); - return err; - } - - if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) { - gpio_free(ZEUS_USB2_PWREN_GPIO); - dev_err(dev, "Can't enable USB2_PWREN\n"); - return err; - } - - /* Port 2 is shared between host and client interface. */ - UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; - - return 0; -} - -static void zeus_ohci_exit(struct device *dev) -{ - /* Power-off port 2 */ - gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0); - gpio_free(ZEUS_USB2_PWREN_GPIO); -} - -static struct pxaohci_platform_data zeus_ohci_platform_data = { - .port_mode = PMM_NPS_MODE, - .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, - .init = zeus_ohci_init, - .exit = zeus_ohci_exit, -}; - -/* - * Flat Panel - */ - -static void zeus_lcd_power(int on, struct fb_var_screeninfo *si) -{ - gpio_set_value(ZEUS_LCD_EN_GPIO, on); -} - -static void zeus_backlight_power(int on) -{ - gpio_set_value(ZEUS_BKLEN_GPIO, on); -} - -static int zeus_setup_fb_gpios(void) -{ - int err; - - if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN"))) - goto out_err; - - if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0))) - goto out_err_lcd; - - if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN"))) - goto out_err_lcd; - - if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0))) - goto out_err_bkl; - - return 0; - -out_err_bkl: - gpio_free(ZEUS_BKLEN_GPIO); -out_err_lcd: - gpio_free(ZEUS_LCD_EN_GPIO); -out_err: - return err; -} - -static struct pxafb_mode_info zeus_fb_mode_info[] = { - { - .pixclock = 39722, - - .xres = 640, - .yres = 480, - - .bpp = 16, - - .hsync_len = 63, - .left_margin = 16, - .right_margin = 81, - - .vsync_len = 2, - .upper_margin = 12, - .lower_margin = 31, - - .sync = 0, - }, -}; - -static struct pxafb_mach_info zeus_fb_info = { - .modes = zeus_fb_mode_info, - .num_modes = 1, - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, - .pxafb_lcd_power = zeus_lcd_power, - .pxafb_backlight_power = zeus_backlight_power, -}; - -/* - * MMC/SD Device - * - * The card detect interrupt isn't debounced so we delay it by 250ms - * to give the card a chance to fully insert/eject. - */ - -static struct pxamci_platform_data zeus_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .detect_delay = HZ/4, - .gpio_card_detect = ZEUS_MMC_CD_GPIO, - .gpio_card_ro = ZEUS_MMC_WP_GPIO, - .gpio_card_ro_invert = 1, - .gpio_power = -1 -}; - -/* - * USB Device Controller - */ -static void zeus_udc_command(int cmd) -{ - switch (cmd) { - case PXA2XX_UDC_CMD_DISCONNECT: - pr_info("zeus: disconnecting USB client\n"); - UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; - break; - - case PXA2XX_UDC_CMD_CONNECT: - pr_info("zeus: connecting USB client\n"); - UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE; - break; - } -} - -static struct pxa2xx_udc_mach_info zeus_udc_info = { - .udc_command = zeus_udc_command, -}; - -static void zeus_power_off(void) -{ - local_irq_disable(); - pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP); -} - -int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio, - unsigned ngpio, void *context) -{ - int i; - u8 pcb_info = 0; - - for (i = 0; i < 8; i++) { - int pcb_bit = gpio + i + 8; - - if (gpio_request(pcb_bit, "pcb info")) { - dev_err(&client->dev, "Can't request pcb info %d\n", i); - continue; - } - - if (gpio_direction_input(pcb_bit)) { - dev_err(&client->dev, "Can't read pcb info %d\n", i); - gpio_free(pcb_bit); - continue; - } - - pcb_info |= !!gpio_get_value(pcb_bit) << i; - - gpio_free(pcb_bit); - } - - dev_info(&client->dev, "Zeus PCB version %d issue %d\n", - pcb_info >> 4, pcb_info & 0xf); - - return 0; -} - -static struct pca953x_platform_data zeus_pca953x_pdata[] = { - [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, }, - [1] = { - .gpio_base = ZEUS_EXT1_GPIO_BASE, - .setup = zeus_get_pcb_info, - }, - [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, }, -}; - -static struct i2c_board_info __initdata zeus_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9535", 0x21), - .platform_data = &zeus_pca953x_pdata[0], - }, - { - I2C_BOARD_INFO("pca9535", 0x22), - .platform_data = &zeus_pca953x_pdata[1], - }, - { - I2C_BOARD_INFO("pca9535", 0x20), - .platform_data = &zeus_pca953x_pdata[2], - .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO), - }, - { I2C_BOARD_INFO("lm75a", 0x48) }, - { I2C_BOARD_INFO("24c01", 0x50) }, - { I2C_BOARD_INFO("isl1208", 0x6f) }, -}; - -static mfp_cfg_t zeus_pin_config[] __initdata = { - GPIO15_nCS_1, - GPIO78_nCS_2, - GPIO80_nCS_4, - GPIO33_nCS_5, - - GPIO22_GPIO, - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, - - GPIO88_USBH1_PWR, - GPIO89_USBH1_PEN, - GPIO119_USBH2_PWR, - GPIO120_USBH2_PEN, - - GPIO86_LCD_LDD_16, - GPIO87_LCD_LDD_17, - - GPIO102_GPIO, - GPIO104_CIF_DD_2, - GPIO105_CIF_DD_1, - - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO85_nPCE_1, - GPIO54_nPCE_2, - GPIO79_PSKTSEL, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - GPIO36_GPIO, /* CF CD */ - GPIO97_GPIO, /* CF PWREN */ - GPIO99_GPIO, /* CF RDY */ -}; - -static void __init zeus_init(void) -{ - u16 dm9000_msc = 0xe279; - - system_rev = __raw_readw(ZEUS_CPLD_VERSION); - pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); - - /* Fix timings for dm9000s (CS1/CS2)*/ - MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16); - MSC1 = (MSC1 & 0xffff0000) | dm9000_msc; - - pm_power_off = zeus_power_off; - - pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config)); - - platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices)); - - pxa_set_ohci_info(&zeus_ohci_platform_data); - - if (zeus_setup_fb_gpios()) - pr_err("Failed to setup fb gpios\n"); - else - set_pxa_fb_info(&zeus_fb_info); - - pxa_set_mci_info(&zeus_mci_platform_data); - pxa_set_udc_info(&zeus_udc_info); - pxa_set_ac97_info(&zeus_ac97_info); - pxa_set_i2c_info(NULL); - i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices)); -} - -static struct map_desc zeus_io_desc[] __initdata = { - { - .virtual = ZEUS_CPLD_VERSION, - .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS), - .length = 0x1000, - .type = MT_DEVICE, - }, - { - .virtual = ZEUS_CPLD_ISA_IRQ, - .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS), - .length = 0x1000, - .type = MT_DEVICE, - }, - { - .virtual = ZEUS_CPLD_CONTROL, - .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS), - .length = 0x1000, - .type = MT_DEVICE, - }, - { - .virtual = ZEUS_CPLD_EXTWDOG, - .pfn = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS), - .length = 0x1000, - .type = MT_DEVICE, - }, - { - .virtual = ZEUS_PC104IO, - .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), - .length = 0x00800000, - .type = MT_DEVICE, - }, -}; - -static void __init zeus_map_io(void) -{ - pxa_map_io(); - - iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); - - /* Clear PSPR to ensure a full restart on wake-up. */ - PMCR = PSPR = 0; - - /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */ - OSCC |= OSCC_OON; - - /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...). - * float chip selects and PCMCIA */ - PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP; -} - -MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS") - /* Maintainer: Marc Zyngier */ - .phys_io = 0x40000000, - .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc), - .boot_params = 0xa0000100, - .map_io = zeus_map_io, - .init_irq = zeus_init_irq, - .timer = &pxa_timer, - .init_machine = zeus_init, -MACHINE_END - diff --git a/trunk/arch/arm/mach-realview/Kconfig b/trunk/arch/arm/mach-realview/Kconfig index ee5e392430e8..c48e1f2c3349 100644 --- a/trunk/arch/arm/mach-realview/Kconfig +++ b/trunk/arch/arm/mach-realview/Kconfig @@ -70,7 +70,7 @@ config MACH_REALVIEW_PBX bool "Support RealView/PBX platform" select ARM_GIC select HAVE_PATA_PLATFORM - select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET + select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM help Include support for the ARM(R) RealView PBX platform. diff --git a/trunk/arch/arm/plat-omap/Kconfig b/trunk/arch/arm/plat-omap/Kconfig index e2ea04a4c8a1..f348ddfb0492 100644 --- a/trunk/arch/arm/plat-omap/Kconfig +++ b/trunk/arch/arm/plat-omap/Kconfig @@ -27,7 +27,6 @@ config ARCH_OMAP4 bool "TI OMAP4" select CPU_V7 select ARM_GIC - select COMMON_CLKDEV endchoice @@ -43,6 +42,28 @@ config OMAP_DEBUG_LEDS depends on OMAP_DEBUG_DEVICES default y if LEDS || LEDS_OMAP_DEBUG +config OMAP_DEBUG_POWERDOMAIN + bool "Emit debug messages from powerdomain layer" + depends on ARCH_OMAP2 || ARCH_OMAP3 + help + Say Y here if you want to compile in powerdomain layer + debugging messages for OMAP2/3. These messages can + provide more detail as to why some powerdomain calls + may be failing, and will also emit a descriptive message + for every powerdomain register write. However, the + extra detail costs some memory. + +config OMAP_DEBUG_CLOCKDOMAIN + bool "Emit debug messages from clockdomain layer" + depends on ARCH_OMAP2 || ARCH_OMAP3 + help + Say Y here if you want to compile in clockdomain layer + debugging messages for OMAP2/3. These messages can + provide more detail as to why some clockdomain calls + may be failing, and will also emit a descriptive message + for every clockdomain register write. However, the + extra detail costs some memory. + config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" depends on ARCH_OMAP @@ -57,28 +78,28 @@ config OMAP_RESET_CLOCKS config OMAP_MUX bool "OMAP multiplexing support" - depends on ARCH_OMAP + depends on ARCH_OMAP default y - help - Pin multiplexing support for OMAP boards. If your bootloader - sets the multiplexing correctly, say N. Otherwise, or if unsure, - say Y. + help + Pin multiplexing support for OMAP boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. config OMAP_MUX_DEBUG bool "Multiplexing debug output" - depends on OMAP_MUX - help - Makes the multiplexing functions print out a lot of debug info. - This is useful if you want to find out the correct values of the - multiplexing registers. + depends on OMAP_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. config OMAP_MUX_WARNINGS bool "Warn about pins the bootloader didn't set up" - depends on OMAP_MUX - default y - help + depends on OMAP_MUX + default y + help Choose Y here to warn whenever driver initialization logic needs - to change the pin multiplexing setup. When there are no warnings + to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect OMAP_MUX for your product. config OMAP_MCBSP @@ -104,7 +125,7 @@ config OMAP_IOMMU_DEBUG tristate choice - prompt "System timer" + prompt "System timer" default OMAP_MPU_TIMER config OMAP_MPU_TIMER @@ -127,11 +148,11 @@ config OMAP_32K_TIMER endchoice config OMAP_32K_TIMER_HZ - int "Kernel internal timer frequency for 32KHz timer" - range 32 1024 - depends on OMAP_32K_TIMER - default "128" - help + int "Kernel internal timer frequency for 32KHz timer" + range 32 1024 + depends on OMAP_32K_TIMER + default "128" + help Kernel internal timer frequency should be a divisor of 32768, such as 64 or 128. diff --git a/trunk/arch/arm/plat-omap/clock.c b/trunk/arch/arm/plat-omap/clock.c index 89cafc937249..681bfc37ebb2 100644 --- a/trunk/arch/arm/plat-omap/clock.c +++ b/trunk/arch/arm/plat-omap/clock.c @@ -40,10 +40,36 @@ static struct clk_functions *arch_clock; * clock framework is not up , it is defined here to avoid rework in * every driver. Also dummy prcm reset function is added */ +/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */ +#if defined(CONFIG_ARCH_OMAP4) +struct clk *clk_get(struct device *dev, const char *id) +{ + return NULL; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +void omap2_clk_prepare_for_reboot(void) +{ +} +EXPORT_SYMBOL(omap2_clk_prepare_for_reboot); + +void omap_prcm_arch_reset(char mode) +{ +} +EXPORT_SYMBOL(omap_prcm_arch_reset); +#endif int clk_enable(struct clk *clk) { unsigned long flags; int ret = 0; + if (cpu_is_omap44xx()) + /* OMAP4 clk framework not supported yet */ + return 0; if (clk == NULL || IS_ERR(clk)) return -EINVAL; diff --git a/trunk/arch/arm/plat-omap/common.c b/trunk/arch/arm/plat-omap/common.c index bf1eaf3a27d4..cc050b3313bd 100644 --- a/trunk/arch/arm/plat-omap/common.c +++ b/trunk/arch/arm/plat-omap/common.c @@ -280,18 +280,16 @@ void __init omap2_set_globals_343x(void) #if defined(CONFIG_ARCH_OMAP4) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + .tap = OMAP2_L4_IO_ADDRESS(0x4830a000), .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), - .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), }; void __init omap2_set_globals_443x(void) { omap2_set_globals_tap(&omap4_globals); omap2_set_globals_control(&omap4_globals); - omap2_set_globals_prcm(&omap4_globals); } #endif diff --git a/trunk/arch/arm/plat-omap/debug-devices.c b/trunk/arch/arm/plat-omap/debug-devices.c index 923c9621096b..09c1107637f6 100644 --- a/trunk/arch/arm/plat-omap/debug-devices.c +++ b/trunk/arch/arm/plat-omap/debug-devices.c @@ -13,7 +13,6 @@ #include #include #include -#include #include @@ -25,12 +24,6 @@ * platforms include H2, H3, H4, and Perseus2. */ -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - static struct resource smc91x_resources[] = { [0] = { .flags = IORESOURCE_MEM, @@ -43,9 +36,6 @@ static struct resource smc91x_resources[] = { static struct platform_device smc91x_device = { .name = "smc91x", .id = -1, - .dev = { - .platform_data = &smc91x_info, - }, .num_resources = ARRAY_SIZE(smc91x_resources), .resource = smc91x_resources, }; diff --git a/trunk/arch/arm/plat-omap/devices.c b/trunk/arch/arm/plat-omap/devices.c index 30b5db73017a..f86617869b38 100644 --- a/trunk/arch/arm/plat-omap/devices.c +++ b/trunk/arch/arm/plat-omap/devices.c @@ -242,39 +242,6 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base, /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) - -#ifdef CONFIG_ARCH_OMAP24XX -#define OMAP_RNG_BASE 0x480A0000 -#else -#define OMAP_RNG_BASE 0xfffe5000 -#endif - -static struct resource rng_resources[] = { - { - .start = OMAP_RNG_BASE, - .end = OMAP_RNG_BASE + 0x4f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap_rng_device = { - .name = "omap_rng", - .id = -1, - .num_resources = ARRAY_SIZE(rng_resources), - .resource = rng_resources, -}; - -static void omap_init_rng(void) -{ - (void) platform_device_register(&omap_rng_device); -} -#else -static inline void omap_init_rng(void) {} -#endif - -/*-------------------------------------------------------------------------*/ - /* Numbering for the SPI-capable controllers when used for SPI: * spi = 1 * uwire = 2 @@ -357,6 +324,39 @@ static void omap_init_wdt(void) static inline void omap_init_wdt(void) {} #endif +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) + +#ifdef CONFIG_ARCH_OMAP24XX +#define OMAP_RNG_BASE 0x480A0000 +#else +#define OMAP_RNG_BASE 0xfffe5000 +#endif + +static struct resource rng_resources[] = { + { + .start = OMAP_RNG_BASE, + .end = OMAP_RNG_BASE + 0x4f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap_rng_device = { + .name = "omap_rng", + .id = -1, + .num_resources = ARRAY_SIZE(rng_resources), + .resource = rng_resources, +}; + +static void omap_init_rng(void) +{ + (void) platform_device_register(&omap_rng_device); +} +#else +static inline void omap_init_rng(void) {} +#endif + /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -384,9 +384,9 @@ static int __init omap_init_devices(void) */ omap_init_dsp(); omap_init_kp(); - omap_init_rng(); omap_init_uwire(); omap_init_wdt(); + omap_init_rng(); return 0; } arch_initcall(omap_init_devices); diff --git a/trunk/arch/arm/plat-omap/dma.c b/trunk/arch/arm/plat-omap/dma.c index 09d82b3c66ce..d17375e06a1e 100644 --- a/trunk/arch/arm/plat-omap/dma.c +++ b/trunk/arch/arm/plat-omap/dma.c @@ -47,6 +47,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; #endif #define OMAP_DMA_ACTIVE 0x01 +#define OMAP_DMA_CCR_EN (1 << 7) #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) @@ -1119,8 +1120,17 @@ int omap_dma_running(void) { int lch; - if (cpu_class_is_omap1()) - if (omap_lcd_dma_running()) + /* + * On OMAP1510, internal LCD controller will start the transfer + * when it gets enabled, so assume DMA running if LCD enabled. + */ + if (cpu_is_omap1510()) + if (omap_readw(0xfffec000 + 0x00) & (1 << 0)) + return 1; + + /* Check if LCD DMA is running */ + if (cpu_is_omap16xx()) + if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) return 1; for (lch = 0; lch < dma_chan_count; lch++) @@ -1980,6 +1990,377 @@ static struct irqaction omap24xx_dma_irq; /*----------------------------------------------------------------------------*/ +static struct lcd_dma_info { + spinlock_t lock; + int reserved; + void (*callback)(u16 status, void *data); + void *cb_data; + + int active; + unsigned long addr, size; + int rotate, data_type, xres, yres; + int vxres; + int mirror; + int xscale, yscale; + int ext_ctrl; + int src_port; + int single_transfer; +} lcd_dma; + +void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, + int data_type) +{ + lcd_dma.addr = addr; + lcd_dma.data_type = data_type; + lcd_dma.xres = fb_xres; + lcd_dma.yres = fb_yres; +} +EXPORT_SYMBOL(omap_set_lcd_dma_b1); + +void omap_set_lcd_dma_src_port(int port) +{ + lcd_dma.src_port = port; +} + +void omap_set_lcd_dma_ext_controller(int external) +{ + lcd_dma.ext_ctrl = external; +} +EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); + +void omap_set_lcd_dma_single_transfer(int single) +{ + lcd_dma.single_transfer = single; +} +EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); + +void omap_set_lcd_dma_b1_rotation(int rotate) +{ + if (omap_dma_in_1510_mode()) { + printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n"); + BUG(); + return; + } + lcd_dma.rotate = rotate; +} +EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation); + +void omap_set_lcd_dma_b1_mirror(int mirror) +{ + if (omap_dma_in_1510_mode()) { + printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n"); + BUG(); + } + lcd_dma.mirror = mirror; +} +EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); + +void omap_set_lcd_dma_b1_vxres(unsigned long vxres) +{ + if (omap_dma_in_1510_mode()) { + printk(KERN_ERR "DMA virtual resulotion is not supported " + "in 1510 mode\n"); + BUG(); + } + lcd_dma.vxres = vxres; +} +EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres); + +void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) +{ + if (omap_dma_in_1510_mode()) { + printk(KERN_ERR "DMA scale is not supported in 1510 mode\n"); + BUG(); + } + lcd_dma.xscale = xscale; + lcd_dma.yscale = yscale; +} +EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale); + +static void set_b1_regs(void) +{ + unsigned long top, bottom; + int es; + u16 w; + unsigned long en, fn; + long ei, fi; + unsigned long vxres; + unsigned int xscale, yscale; + + switch (lcd_dma.data_type) { + case OMAP_DMA_DATA_TYPE_S8: + es = 1; + break; + case OMAP_DMA_DATA_TYPE_S16: + es = 2; + break; + case OMAP_DMA_DATA_TYPE_S32: + es = 4; + break; + default: + BUG(); + return; + } + + vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres; + xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; + yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; + BUG_ON(vxres < lcd_dma.xres); + +#define PIXADDR(x, y) (lcd_dma.addr + \ + ((y) * vxres * yscale + (x) * xscale) * es) +#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) + + switch (lcd_dma.rotate) { + case 0: + if (!lcd_dma.mirror) { + top = PIXADDR(0, 0); + bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); + /* 1510 DMA requires the bottom address to be 2 more + * than the actual last memory access location. */ + if (omap_dma_in_1510_mode() && + lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) + bottom += 2; + ei = PIXSTEP(0, 0, 1, 0); + fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); + } else { + top = PIXADDR(lcd_dma.xres - 1, 0); + bottom = PIXADDR(0, lcd_dma.yres - 1); + ei = PIXSTEP(1, 0, 0, 0); + fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1); + } + en = lcd_dma.xres; + fn = lcd_dma.yres; + break; + case 90: + if (!lcd_dma.mirror) { + top = PIXADDR(0, lcd_dma.yres - 1); + bottom = PIXADDR(lcd_dma.xres - 1, 0); + ei = PIXSTEP(0, 1, 0, 0); + fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1); + } else { + top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); + bottom = PIXADDR(0, 0); + ei = PIXSTEP(0, 1, 0, 0); + fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1); + } + en = lcd_dma.yres; + fn = lcd_dma.xres; + break; + case 180: + if (!lcd_dma.mirror) { + top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); + bottom = PIXADDR(0, 0); + ei = PIXSTEP(1, 0, 0, 0); + fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0); + } else { + top = PIXADDR(0, lcd_dma.yres - 1); + bottom = PIXADDR(lcd_dma.xres - 1, 0); + ei = PIXSTEP(0, 0, 1, 0); + fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0); + } + en = lcd_dma.xres; + fn = lcd_dma.yres; + break; + case 270: + if (!lcd_dma.mirror) { + top = PIXADDR(lcd_dma.xres - 1, 0); + bottom = PIXADDR(0, lcd_dma.yres - 1); + ei = PIXSTEP(0, 0, 0, 1); + fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0); + } else { + top = PIXADDR(0, 0); + bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1); + ei = PIXSTEP(0, 0, 0, 1); + fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0); + } + en = lcd_dma.yres; + fn = lcd_dma.xres; + break; + default: + BUG(); + return; /* Suppress warning about uninitialized vars */ + } + + if (omap_dma_in_1510_mode()) { + omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); + omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); + omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); + omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); + + return; + } + + /* 1610 regs */ + omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); + omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); + omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); + omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); + + omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); + omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); + + w = omap_readw(OMAP1610_DMA_LCD_CSDP); + w &= ~0x03; + w |= lcd_dma.data_type; + omap_writew(w, OMAP1610_DMA_LCD_CSDP); + + w = omap_readw(OMAP1610_DMA_LCD_CTRL); + /* Always set the source port as SDRAM for now*/ + w &= ~(0x03 << 6); + if (lcd_dma.callback != NULL) + w |= 1 << 1; /* Block interrupt enable */ + else + w &= ~(1 << 1); + omap_writew(w, OMAP1610_DMA_LCD_CTRL); + + if (!(lcd_dma.rotate || lcd_dma.mirror || + lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale)) + return; + + w = omap_readw(OMAP1610_DMA_LCD_CCR); + /* Set the double-indexed addressing mode */ + w |= (0x03 << 12); + omap_writew(w, OMAP1610_DMA_LCD_CCR); + + omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); + omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); + omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); +} + +static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id) +{ + u16 w; + + w = omap_readw(OMAP1610_DMA_LCD_CTRL); + if (unlikely(!(w & (1 << 3)))) { + printk(KERN_WARNING "Spurious LCD DMA IRQ\n"); + return IRQ_NONE; + } + /* Ack the IRQ */ + w |= (1 << 3); + omap_writew(w, OMAP1610_DMA_LCD_CTRL); + lcd_dma.active = 0; + if (lcd_dma.callback != NULL) + lcd_dma.callback(w, lcd_dma.cb_data); + + return IRQ_HANDLED; +} + +int omap_request_lcd_dma(void (*callback)(u16 status, void *data), + void *data) +{ + spin_lock_irq(&lcd_dma.lock); + if (lcd_dma.reserved) { + spin_unlock_irq(&lcd_dma.lock); + printk(KERN_ERR "LCD DMA channel already reserved\n"); + BUG(); + return -EBUSY; + } + lcd_dma.reserved = 1; + spin_unlock_irq(&lcd_dma.lock); + lcd_dma.callback = callback; + lcd_dma.cb_data = data; + lcd_dma.active = 0; + lcd_dma.single_transfer = 0; + lcd_dma.rotate = 0; + lcd_dma.vxres = 0; + lcd_dma.mirror = 0; + lcd_dma.xscale = 0; + lcd_dma.yscale = 0; + lcd_dma.ext_ctrl = 0; + lcd_dma.src_port = 0; + + return 0; +} +EXPORT_SYMBOL(omap_request_lcd_dma); + +void omap_free_lcd_dma(void) +{ + spin_lock(&lcd_dma.lock); + if (!lcd_dma.reserved) { + spin_unlock(&lcd_dma.lock); + printk(KERN_ERR "LCD DMA is not reserved\n"); + BUG(); + return; + } + if (!enable_1510_mode) + omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, + OMAP1610_DMA_LCD_CCR); + lcd_dma.reserved = 0; + spin_unlock(&lcd_dma.lock); +} +EXPORT_SYMBOL(omap_free_lcd_dma); + +void omap_enable_lcd_dma(void) +{ + u16 w; + + /* + * Set the Enable bit only if an external controller is + * connected. Otherwise the OMAP internal controller will + * start the transfer when it gets enabled. + */ + if (enable_1510_mode || !lcd_dma.ext_ctrl) + return; + + w = omap_readw(OMAP1610_DMA_LCD_CTRL); + w |= 1 << 8; + omap_writew(w, OMAP1610_DMA_LCD_CTRL); + + lcd_dma.active = 1; + + w = omap_readw(OMAP1610_DMA_LCD_CCR); + w |= 1 << 7; + omap_writew(w, OMAP1610_DMA_LCD_CCR); +} +EXPORT_SYMBOL(omap_enable_lcd_dma); + +void omap_setup_lcd_dma(void) +{ + BUG_ON(lcd_dma.active); + if (!enable_1510_mode) { + /* Set some reasonable defaults */ + omap_writew(0x5440, OMAP1610_DMA_LCD_CCR); + omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); + omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); + } + set_b1_regs(); + if (!enable_1510_mode) { + u16 w; + + w = omap_readw(OMAP1610_DMA_LCD_CCR); + /* + * If DMA was already active set the end_prog bit to have + * the programmed register set loaded into the active + * register set. + */ + w |= 1 << 11; /* End_prog */ + if (!lcd_dma.single_transfer) + w |= (3 << 8); /* Auto_init, repeat */ + omap_writew(w, OMAP1610_DMA_LCD_CCR); + } +} +EXPORT_SYMBOL(omap_setup_lcd_dma); + +void omap_stop_lcd_dma(void) +{ + u16 w; + + lcd_dma.active = 0; + if (enable_1510_mode || !lcd_dma.ext_ctrl) + return; + + w = omap_readw(OMAP1610_DMA_LCD_CCR); + w &= ~(1 << 7); + omap_writew(w, OMAP1610_DMA_LCD_CCR); + + w = omap_readw(OMAP1610_DMA_LCD_CTRL); + w &= ~(1 << 8); + omap_writew(w, OMAP1610_DMA_LCD_CTRL); +} +EXPORT_SYMBOL(omap_stop_lcd_dma); + void omap_dma_global_context_save(void) { omap_dma_global_context.dma_irqenable_l0 = @@ -2084,6 +2465,14 @@ static int __init omap_init_dma(void) dma_chan_count = 16; } else dma_chan_count = 9; + if (cpu_is_omap16xx()) { + u16 w; + + /* this would prevent OMAP sleep */ + w = omap_readw(OMAP1610_DMA_LCD_CTRL); + w &= ~(1 << 8); + omap_writew(w, OMAP1610_DMA_LCD_CTRL); + } } else if (cpu_class_is_omap2()) { u8 revision = dma_read(REVISION) & 0xff; printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", @@ -2094,6 +2483,7 @@ static int __init omap_init_dma(void) return 0; } + spin_lock_init(&lcd_dma.lock); spin_lock_init(&dma_chan_lock); for (ch = 0; ch < dma_chan_count; ch++) { @@ -2158,6 +2548,22 @@ static int __init omap_init_dma(void) } } + + /* FIXME: Update LCD DMA to work on 24xx */ + if (cpu_class_is_omap1()) { + r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, + "LCD DMA", NULL); + if (r != 0) { + int i; + + printk(KERN_ERR "unable to request IRQ for LCD DMA " + "(error %d)\n", r); + for (i = 0; i < dma_chan_count; i++) + free_irq(omap1_dma_irq[i], (void *) (i + 1)); + goto out_free; + } + } + return 0; out_free: diff --git a/trunk/arch/arm/plat-omap/i2c.c b/trunk/arch/arm/plat-omap/i2c.c index 33fff4ef382d..c08362dbb8ed 100644 --- a/trunk/arch/arm/plat-omap/i2c.c +++ b/trunk/arch/arm/plat-omap/i2c.c @@ -80,8 +80,47 @@ static struct platform_device omap_i2c_devices[] = { #endif }; +#if defined(CONFIG_ARCH_OMAP24XX) +static const int omap24xx_pins[][2] = { + { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, + { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, +}; +#else +static const int omap24xx_pins[][2] = {}; +#endif +#if defined(CONFIG_ARCH_OMAP34XX) +static const int omap34xx_pins[][2] = { + { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA}, + { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA}, + { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA}, +}; +#else +static const int omap34xx_pins[][2] = {}; +#endif + #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) +static void __init omap_i2c_mux_pins(int bus) +{ + int scl, sda; + + if (cpu_class_is_omap1()) { + scl = I2C_SCL; + sda = I2C_SDA; + } else if (cpu_is_omap24xx()) { + scl = omap24xx_pins[bus][0]; + sda = omap24xx_pins[bus][1]; + } else if (cpu_is_omap34xx()) { + scl = omap34xx_pins[bus][0]; + sda = omap34xx_pins[bus][1]; + } else { + return; + } + + omap_cfg_reg(sda); + omap_cfg_reg(scl); +} + static int __init omap_i2c_nr_ports(void) { int ports = 0; @@ -117,6 +156,7 @@ static int __init omap_i2c_add_bus(int bus_id) res[1].start = irq; } + omap_i2c_mux_pins(bus_id - 1); return platform_device_register(pdev); } @@ -169,7 +209,7 @@ static int __init omap_register_i2c_bus_cmdline(void) subsys_initcall(omap_register_i2c_bus_cmdline); /** - * omap_plat_register_i2c_bus - register I2C bus with device descriptors + * omap_register_i2c_bus - register I2C bus with device descriptors * @bus_id: bus id counting from number 1 * @clkrate: clock rate of the bus in kHz * @info: pointer into I2C device descriptor table or NULL @@ -177,7 +217,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline); * * Returns 0 on success or an error code. */ -int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate, +int __init omap_register_i2c_bus(int bus_id, u32 clkrate, struct i2c_board_info const *info, unsigned len) { diff --git a/trunk/arch/arm/plat-omap/include/plat/board.h b/trunk/arch/arm/plat-omap/include/plat/board.h index 376ce18216ff..abb17b604f82 100644 --- a/trunk/arch/arm/plat-omap/include/plat/board.h +++ b/trunk/arch/arm/plat-omap/include/plat/board.h @@ -114,6 +114,15 @@ struct omap_pwm_led_platform_data { void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); }; +/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */ +struct omap_gpio_switch_config { + char name[12]; + u16 gpio; + int flags:4; + int type:4; + int key_code:24; /* Linux key code */ +}; + struct omap_uart_config { /* Bit field of UARTs present; bit 0 --> UART1 */ unsigned int enabled_uarts; diff --git a/trunk/arch/arm/plat-omap/include/plat/clkdev_omap.h b/trunk/arch/arm/plat-omap/include/plat/clkdev_omap.h deleted file mode 100644 index 35b36caf5f91..000000000000 --- a/trunk/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * clkdev <-> OMAP integration - * - * Russell King - * - */ - -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H - -#include - -struct omap_clk { - u16 cpu; - struct clk_lookup lk; -}; - -#define CLK(dev, con, ck, cp) \ - { \ - .cpu = cp, \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - }, \ - } - - -#define CK_310 (1 << 0) -#define CK_7XX (1 << 1) -#define CK_1510 (1 << 2) -#define CK_16XX (1 << 3) -#define CK_243X (1 << 4) -#define CK_242X (1 << 5) -#define CK_343X (1 << 6) -#define CK_3430ES1 (1 << 7) -#define CK_3430ES2 (1 << 8) -#define CK_443X (1 << 9) - -#endif - diff --git a/trunk/arch/arm/plat-omap/include/plat/clock.h b/trunk/arch/arm/plat-omap/include/plat/clock.h index 309b6d1dccdb..4b8b0d65cbf2 100644 --- a/trunk/arch/arm/plat-omap/include/plat/clock.h +++ b/trunk/arch/arm/plat-omap/include/plat/clock.h @@ -13,8 +13,6 @@ #ifndef __ARCH_ARM_OMAP_CLOCK_H #define __ARCH_ARM_OMAP_CLOCK_H -#include - struct module; struct clk; struct clockdomain; @@ -150,8 +148,6 @@ extern const struct clkops clkops_null; #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -#define CLOCK_IN_OMAP4430 (1 << 13) -#define ALWAYS_ENABLED (1 << 14) /* bits 13-31 are currently free */ /* Clksel_rate flags */ @@ -160,7 +156,6 @@ extern const struct clkops clkops_null; #define RATE_IN_243X (1 << 2) #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ -#define RATE_IN_4430 (1 << 5) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) diff --git a/trunk/arch/arm/plat-omap/include/plat/common.h b/trunk/arch/arm/plat-omap/include/plat/common.h index 32c22272425d..064f1730f43b 100644 --- a/trunk/arch/arm/plat-omap/include/plat/common.h +++ b/trunk/arch/arm/plat-omap/include/plat/common.h @@ -27,7 +27,7 @@ #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H #define __ARCH_ARM_MACH_OMAP_COMMON_H -#include +#include struct sys_timer; @@ -36,6 +36,18 @@ extern void __iomem *gic_cpu_base_addr; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) +extern int omap_register_i2c_bus(int bus_id, u32 clkrate, + struct i2c_board_info const *info, + unsigned len); +#else +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, + struct i2c_board_info const *info, + unsigned len) +{ + return 0; +} +#endif /* IO bases for various OMAP processors */ struct omap_globals { @@ -46,7 +58,6 @@ struct omap_globals { void __iomem *ctrl; /* System Control Module */ void __iomem *prm; /* Power and Reset Management */ void __iomem *cm; /* Clock Management */ - void __iomem *cm2; }; void omap2_set_globals_242x(void); @@ -60,24 +71,4 @@ void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); -/** - * omap_test_timeout - busy-loop, testing a condition - * @cond: condition to test until it evaluates to true - * @timeout: maximum number of microseconds in the timeout - * @index: loop index (integer) - * - * Loop waiting for @cond to become true or until at least @timeout - * microseconds have passed. To use, define some integer @index in the - * calling code. After running, if @index == @timeout, then the loop has - * timed out. - */ -#define omap_test_timeout(cond, timeout, index) \ -({ \ - for (index = 0; index < timeout; index++) { \ - if (cond) \ - break; \ - udelay(1); \ - } \ -}) - #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/cpu.h b/trunk/arch/arm/plat-omap/include/plat/cpu.h index 9a028bdebb06..2e1789001dfe 100644 --- a/trunk/arch/arm/plat-omap/include/plat/cpu.h +++ b/trunk/arch/arm/plat-omap/include/plat/cpu.h @@ -176,13 +176,11 @@ IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) -IS_OMAP_CLASS(44xx, 0x44) IS_OMAP_SUBCLASS(242x, 0x242) IS_OMAP_SUBCLASS(243x, 0x243) IS_OMAP_SUBCLASS(343x, 0x343) IS_OMAP_SUBCLASS(363x, 0x363) -IS_OMAP_SUBCLASS(443x, 0x443) #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 @@ -395,11 +393,11 @@ IS_OMAP_TYPE(3517, 0x3517) (!omap3_has_iva()) && \ (!omap3_has_sgx())) # define cpu_is_omap3515() (cpu_is_omap3430() && \ - (!omap3_has_iva()) && \ - (omap3_has_sgx())) + (omap3_has_iva()) && \ + (!omap3_has_sgx())) # define cpu_is_omap3525() (cpu_is_omap3430() && \ - (!omap3_has_sgx()) && \ - (omap3_has_iva())) + (omap3_has_sgx()) && \ + (!omap3_has_iva())) # define cpu_is_omap3530() (cpu_is_omap3430()) # define cpu_is_omap3505() is_omap3505() # define cpu_is_omap3517() is_omap3517() @@ -410,8 +408,8 @@ IS_OMAP_TYPE(3517, 0x3517) # if defined(CONFIG_ARCH_OMAP4) # undef cpu_is_omap44xx # undef cpu_is_omap443x -# define cpu_is_omap44xx() is_omap44xx() -# define cpu_is_omap443x() is_omap443x() +# define cpu_is_omap44xx() 1 +# define cpu_is_omap443x() 1 # endif /* Macros to detect if we have OMAP1 or OMAP2 */ @@ -438,15 +436,14 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3630_REV_ES1_0 0x36300034 #define OMAP35XX_CLASS 0x35000034 -#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) -#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) -#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8)) -#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8)) -#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) -#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) - -#define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 0x44300044 +#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12)) +#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12)) +#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12)) +#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12)) +#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12)) +#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12)) + +#define OMAP443X_CLASS 0x44300034 /* * omap_chip bits diff --git a/trunk/arch/arm/plat-omap/include/plat/dma.h b/trunk/arch/arm/plat-omap/include/plat/dma.h index 4ede9e17a0be..1c017b29b7e9 100644 --- a/trunk/arch/arm/plat-omap/include/plat/dma.h +++ b/trunk/arch/arm/plat-omap/include/plat/dma.h @@ -401,6 +401,33 @@ /*----------------------------------------------------------------------------*/ +/* Hardware registers for LCD DMA */ +#define OMAP1510_DMA_LCD_BASE (0xfffedb00) +#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) +#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) +#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) +#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) +#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) + +#define OMAP1610_DMA_LCD_BASE (0xfffee300) +#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) +#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) +#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) +#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) +#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) +#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) +#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) +#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) +#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) +#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) +#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) +#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) +#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) +#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) +#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) +#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) +#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) + #define OMAP1_DMA_TOUT_IRQ (1 << 0) #define OMAP_DMA_DROP_IRQ (1 << 1) #define OMAP_DMA_HALF_IRQ (1 << 2) @@ -414,8 +441,6 @@ #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) -#define OMAP_DMA_CCR_EN (1 << 7) - #define OMAP_DMA_DATA_TYPE_S8 0x00 #define OMAP_DMA_DATA_TYPE_S16 0x01 #define OMAP_DMA_DATA_TYPE_S32 0x02 @@ -478,6 +503,14 @@ #define DMA_CH_PRIO_HIGH 0x1 #define DMA_CH_PRIO_LOW 0x0 /* Def */ +/* LCD DMA block numbers */ +enum { + OMAP_LCD_DMA_B1_TOP, + OMAP_LCD_DMA_B1_BOTTOM, + OMAP_LCD_DMA_B2_TOP, + OMAP_LCD_DMA_B2_BOTTOM +}; + enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_DIS = 0, OMAP_DMA_DATA_BURST_4, @@ -628,13 +661,20 @@ extern int omap_modify_dma_chain_params(int chain_id, extern int omap_dma_chain_status(int chain_id); #endif -#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) -#include -#else -static inline int omap_lcd_dma_running(void) -{ - return 0; -} -#endif +/* LCD DMA functions */ +extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), + void *data); +extern void omap_free_lcd_dma(void); +extern void omap_setup_lcd_dma(void); +extern void omap_enable_lcd_dma(void); +extern void omap_stop_lcd_dma(void); +extern void omap_set_lcd_dma_ext_controller(int external); +extern void omap_set_lcd_dma_single_transfer(int single); +extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, + int data_type); +extern void omap_set_lcd_dma_b1_rotation(int rotate); +extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); +extern void omap_set_lcd_dma_b1_mirror(int mirror); +extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); #endif /* __ASM_ARCH_DMA_H */ diff --git a/trunk/arch/arm/plat-omap/include/plat/gpmc.h b/trunk/arch/arm/plat-omap/include/plat/gpmc.h index e081338e0b23..696e0ca051b7 100644 --- a/trunk/arch/arm/plat-omap/include/plat/gpmc.h +++ b/trunk/arch/arm/plat-omap/include/plat/gpmc.h @@ -45,7 +45,7 @@ #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) -#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2) +#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) #define GPMC_CONFIG1_MUXADDDATA (1 << 9) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) diff --git a/trunk/arch/arm/plat-omap/include/plat/i2c.h b/trunk/arch/arm/plat-omap/include/plat/i2c.h deleted file mode 100644 index 585d9ca68b97..000000000000 --- a/trunk/arch/arm/plat-omap/include/plat/i2c.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Helper module for board specific I2C bus registration - * - * Copyright (C) 2009 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include - -#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) -extern int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len); -#else -static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len) -{ - return 0; -} -#endif - -int omap_plat_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len); diff --git a/trunk/arch/arm/plat-omap/include/plat/mux.h b/trunk/arch/arm/plat-omap/include/plat/mux.h index 8f069cc80350..ba77de601501 100644 --- a/trunk/arch/arm/plat-omap/include/plat/mux.h +++ b/trunk/arch/arm/plat-omap/include/plat/mux.h @@ -130,11 +130,58 @@ #define OMAP2_PULL_UP (1 << 4) #define OMAP2_ALTELECTRICALSEL (1 << 5) +/* 34xx specific mux bit defines */ +#define OMAP3_INPUT_EN (1 << 8) +#define OMAP3_OFF_EN (1 << 9) +#define OMAP3_OFFOUT_EN (1 << 10) +#define OMAP3_OFFOUT_VAL (1 << 11) +#define OMAP3_OFF_PULL_EN (1 << 12) +#define OMAP3_OFF_PULL_UP (1 << 13) +#define OMAP3_WAKEUP_EN (1 << 14) + +/* 34xx mux mode options for each pin. See TRM for options */ +#define OMAP34XX_MUX_MODE0 0 +#define OMAP34XX_MUX_MODE1 1 +#define OMAP34XX_MUX_MODE2 2 +#define OMAP34XX_MUX_MODE3 3 +#define OMAP34XX_MUX_MODE4 4 +#define OMAP34XX_MUX_MODE5 5 +#define OMAP34XX_MUX_MODE6 6 +#define OMAP34XX_MUX_MODE7 7 + +/* 34xx active pin states */ +#define OMAP34XX_PIN_OUTPUT 0 +#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN +#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \ + | OMAP2_PULL_UP) +#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN) + +/* 34xx off mode states */ +#define OMAP34XX_PIN_OFF_NONE 0 +#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \ + | OMAP3_OFFOUT_VAL) +#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN) +#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \ + | OMAP3_OFF_PULL_UP) +#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN) +#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN + +#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \ + .name = desc, \ + .debug = 0, \ + .mux_reg = reg_offset, \ + .mux_val = mux_value \ +}, + struct pin_config { char *name; const unsigned int mux_reg; unsigned char debug; +#if defined(CONFIG_ARCH_OMAP34XX) + u16 mux_val; /* Wake-up, off mode, pull, mux mode */ +#endif + #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) const unsigned char mask_offset; const unsigned char mask; @@ -172,17 +219,11 @@ enum omap7xx_index { AA17_7XX_USB_DM, W16_7XX_USB_PU_EN, W17_7XX_USB_VBUSI, - W18_7XX_USB_DMCK_OUT, - W19_7XX_USB_DCRST, /* MMC */ MMC_7XX_CMD, MMC_7XX_CLK, MMC_7XX_DAT0, - - /* I2C */ - I2C_7XX_SCL, - I2C_7XX_SDA, }; enum omap1xxx_index { @@ -640,6 +681,181 @@ enum omap24xx_index { }; +enum omap34xx_index { + /* 34xx I2C */ + K21_34XX_I2C1_SCL, + J21_34XX_I2C1_SDA, + AF15_34XX_I2C2_SCL, + AE15_34XX_I2C2_SDA, + AF14_34XX_I2C3_SCL, + AG14_34XX_I2C3_SDA, + AD26_34XX_I2C4_SCL, + AE26_34XX_I2C4_SDA, + + /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/ + Y8_3430_USB1HS_PHY_CLK, + Y9_3430_USB1HS_PHY_STP, + AA14_3430_USB1HS_PHY_DIR, + AA11_3430_USB1HS_PHY_NXT, + W13_3430_USB1HS_PHY_DATA0, + W12_3430_USB1HS_PHY_DATA1, + W11_3430_USB1HS_PHY_DATA2, + Y11_3430_USB1HS_PHY_DATA3, + W9_3430_USB1HS_PHY_DATA4, + Y12_3430_USB1HS_PHY_DATA5, + W8_3430_USB1HS_PHY_DATA6, + Y13_3430_USB1HS_PHY_DATA7, + + /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/ + AA8_3430_USB2HS_PHY_CLK, + AA10_3430_USB2HS_PHY_STP, + AA9_3430_USB2HS_PHY_DIR, + AB11_3430_USB2HS_PHY_NXT, + AB10_3430_USB2HS_PHY_DATA0, + AB9_3430_USB2HS_PHY_DATA1, + W3_3430_USB2HS_PHY_DATA2, + T4_3430_USB2HS_PHY_DATA3, + T3_3430_USB2HS_PHY_DATA4, + R3_3430_USB2HS_PHY_DATA5, + R4_3430_USB2HS_PHY_DATA6, + T2_3430_USB2HS_PHY_DATA7, + + + /* TLL - HSUSB: 12-pin TLL Port 1*/ + Y8_3430_USB1HS_TLL_CLK, + Y9_3430_USB1HS_TLL_STP, + AA14_3430_USB1HS_TLL_DIR, + AA11_3430_USB1HS_TLL_NXT, + W13_3430_USB1HS_TLL_DATA0, + W12_3430_USB1HS_TLL_DATA1, + W11_3430_USB1HS_TLL_DATA2, + Y11_3430_USB1HS_TLL_DATA3, + W9_3430_USB1HS_TLL_DATA4, + Y12_3430_USB1HS_TLL_DATA5, + W8_3430_USB1HS_TLL_DATA6, + Y13_3430_USB1HS_TLL_DATA7, + + /* TLL - HSUSB: 12-pin TLL Port 2*/ + AA8_3430_USB2HS_TLL_CLK, + AA10_3430_USB2HS_TLL_STP, + AA9_3430_USB2HS_TLL_DIR, + AB11_3430_USB2HS_TLL_NXT, + AB10_3430_USB2HS_TLL_DATA0, + AB9_3430_USB2HS_TLL_DATA1, + W3_3430_USB2HS_TLL_DATA2, + T4_3430_USB2HS_TLL_DATA3, + T3_3430_USB2HS_TLL_DATA4, + R3_3430_USB2HS_TLL_DATA5, + R4_3430_USB2HS_TLL_DATA6, + T2_3430_USB2HS_TLL_DATA7, + + /* TLL - HSUSB: 12-pin TLL Port 3*/ + AA6_3430_USB3HS_TLL_CLK, + AB3_3430_USB3HS_TLL_STP, + AA3_3430_USB3HS_TLL_DIR, + Y3_3430_USB3HS_TLL_NXT, + AA5_3430_USB3HS_TLL_DATA0, + Y4_3430_USB3HS_TLL_DATA1, + Y5_3430_USB3HS_TLL_DATA2, + W5_3430_USB3HS_TLL_DATA3, + AB12_3430_USB3HS_TLL_DATA4, + AB13_3430_USB3HS_TLL_DATA5, + AA13_3430_USB3HS_TLL_DATA6, + AA12_3430_USB3HS_TLL_DATA7, + + /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */ + AF10_3430_USB1FS_PHY_MM1_RXDP, + AG9_3430_USB1FS_PHY_MM1_RXDM, + W13_3430_USB1FS_PHY_MM1_RXRCV, + W12_3430_USB1FS_PHY_MM1_TXSE0, + W11_3430_USB1FS_PHY_MM1_TXDAT, + Y11_3430_USB1FS_PHY_MM1_TXEN_N, + + /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */ + AF7_3430_USB2FS_PHY_MM2_RXDP, + AH7_3430_USB2FS_PHY_MM2_RXDM, + AB10_3430_USB2FS_PHY_MM2_RXRCV, + AB9_3430_USB2FS_PHY_MM2_TXSE0, + W3_3430_USB2FS_PHY_MM2_TXDAT, + T4_3430_USB2FS_PHY_MM2_TXEN_N, + + /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */ + AH3_3430_USB3FS_PHY_MM3_RXDP, + AE3_3430_USB3FS_PHY_MM3_RXDM, + AD1_3430_USB3FS_PHY_MM3_RXRCV, + AE1_3430_USB3FS_PHY_MM3_TXSE0, + AD2_3430_USB3FS_PHY_MM3_TXDAT, + AC1_3430_USB3FS_PHY_MM3_TXEN_N, + + /* 34xx GPIO + * - normally these are bidirectional, no internal pullup/pulldown + * - "_UP" suffix (GPIO3_UP) if internal pullup is configured + * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown + * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) + */ + AF26_34XX_GPIO0, + AF22_34XX_GPIO9, + AG9_34XX_GPIO23, + AH8_34XX_GPIO29, + U8_34XX_GPIO54_OUT, + U8_34XX_GPIO54_DOWN, + L8_34XX_GPIO63, + G25_34XX_GPIO86_OUT, + AG4_34XX_GPIO134_OUT, + AF4_34XX_GPIO135_OUT, + AE4_34XX_GPIO136_OUT, + AF6_34XX_GPIO140_UP, + AE6_34XX_GPIO141, + AF5_34XX_GPIO142, + AE5_34XX_GPIO143, + H19_34XX_GPIO164_OUT, + J25_34XX_GPIO170, + + /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ + H16_34XX_SDRC_CKE0, + H17_34XX_SDRC_CKE1, + + /* MMC1 */ + N28_3430_MMC1_CLK, + M27_3430_MMC1_CMD, + N27_3430_MMC1_DAT0, + N26_3430_MMC1_DAT1, + N25_3430_MMC1_DAT2, + P28_3430_MMC1_DAT3, + P27_3430_MMC1_DAT4, + P26_3430_MMC1_DAT5, + R27_3430_MMC1_DAT6, + R25_3430_MMC1_DAT7, + + /* MMC2 */ + AE2_3430_MMC2_CLK, + AG5_3430_MMC2_CMD, + AH5_3430_MMC2_DAT0, + AH4_3430_MMC2_DAT1, + AG4_3430_MMC2_DAT2, + AF4_3430_MMC2_DAT3, + AE4_3430_MMC2_DAT4, + AH3_3430_MMC2_DAT5, + AF3_3430_MMC2_DAT6, + AE3_3430_MMC2_DAT7, + + /* MMC3 */ + AF10_3430_MMC3_CLK, + AC3_3430_MMC3_CMD, + AE11_3430_MMC3_DAT0, + AH9_3430_MMC3_DAT1, + AF13_3430_MMC3_DAT2, + AF13_3430_MMC3_DAT3, + + /* SYS_NIRQ T2 INT1 */ + AF26_34XX_SYS_NIRQ, + + /* EHCI GPIO's for OMAP3EVM (Rev >= E) */ + AH14_34XX_GPIO21, + AF9_34XX_GPIO22, + U3_34XX_GPIO61, +}; + struct omap_mux_cfg { struct pin_config *pins; unsigned long size; @@ -649,14 +865,14 @@ struct omap_mux_cfg { #ifdef CONFIG_OMAP_MUX /* setup pin muxing in Linux */ extern int omap1_mux_init(void); +extern int omap2_mux_init(void); extern int omap_mux_register(struct omap_mux_cfg *); extern int omap_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ static inline int omap1_mux_init(void) { return 0; } +static inline int omap2_mux_init(void) { return 0; } static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } #endif -extern int omap2_mux_init(void); - #endif diff --git a/trunk/arch/arm/plat-omap/include/plat/omap44xx.h b/trunk/arch/arm/plat-omap/include/plat/omap44xx.h index ef870de43c29..e52902a15c1a 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap44xx.h @@ -26,10 +26,8 @@ #define OMAP44XX_EMIF2_BASE 0x4d000000 #define OMAP44XX_DMM_BASE 0x4e000000 #define OMAP4430_32KSYNCT_BASE 0x4a304000 -#define OMAP4430_CM1_BASE 0x4a004000 -#define OMAP4430_CM_BASE OMAP4430_CM1_BASE -#define OMAP4430_CM2_BASE 0x4a008000 -#define OMAP4430_PRM_BASE 0x4a306000 +#define OMAP4430_CM_BASE 0x4a004000 +#define OMAP4430_PRM_BASE 0x48306000 #define OMAP44XX_GPMC_BASE 0x50000000 #define OMAP443X_SCM_BASE 0x4a002000 #define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_device.h b/trunk/arch/arm/plat-omap/include/plat/omap_device.h index dc1fac1d805c..11a9773a4e7f 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_device.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_device.h @@ -50,8 +50,8 @@ * @pm_lats: ptr to an omap_device_pm_latency table * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats * @pm_lat_level: array index of the last odpl entry executed - -1 if never - * @dev_wakeup_lat: dev wakeup latency in nanoseconds - * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM + * @dev_wakeup_lat: dev wakeup latency in microseconds + * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM * @_state: one of OMAP_DEVICE_STATE_* (see above) * @flags: device flags * @@ -137,7 +137,5 @@ struct omap_device_pm_latency { }; -/* Get omap_device pointer from platform_device pointer */ -#define to_omap_device(x) container_of((x), struct omap_device, pdev) - #endif + diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index 007935a921ea..dbdd123eca16 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -50,8 +50,6 @@ struct omap_device; #define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) #define SYSC_SOFTRESET_SHIFT 1 #define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) -#define SYSC_AUTOIDLE_SHIFT 0 -#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 @@ -64,21 +62,7 @@ struct omap_device; /** - * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod - * @name: name of the IRQ channel (module local name) - * @irq_ch: IRQ channel ID - * - * @name should be something short, e.g., "tx" or "rx". It is for use - * by platform_get_resource_byname(). It is defined locally to the - * hwmod. - */ -struct omap_hwmod_irq_info { - const char *name; - u16 irq; -}; - -/** - * struct omap_hwmod_dma_info - DMA channels used by the hwmod + * struct omap_hwmod_dma_info - MPU address space handled by the hwmod * @name: name of the DMA channel (module local name) * @dma_ch: DMA channel ID * @@ -310,17 +294,13 @@ struct omap_hwmod_omap4_prcm { * SDRAM controller, etc. * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM * controller, etc. - * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) - * when module is enabled, rather than the default, which is to - * enable autoidle * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) #define HWMOD_INIT_NO_RESET (1 << 2) #define HWMOD_INIT_NO_IDLE (1 << 3) -#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) -#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4) /* * omap_hwmod._int_flags definitions @@ -393,7 +373,7 @@ struct omap_hwmod_omap4_prcm { struct omap_hwmod { const char *name; struct omap_device *od; - struct omap_hwmod_irq_info *mpu_irqs; + u8 *mpu_irqs; struct omap_hwmod_dma_info *sdma_chs; union { struct omap_hwmod_omap2_prcm omap2; diff --git a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h index 0b960051eaed..3d45ee1d3cf4 100644 --- a/trunk/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/trunk/arch/arm/plat-omap/include/plat/powerdomain.h @@ -28,8 +28,6 @@ #define PWRDM_POWER_INACTIVE 0x2 #define PWRDM_POWER_ON 0x3 -#define PWRDM_MAX_PWRSTS 4 - /* Powerdomain allowable state bitfields */ #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) @@ -42,10 +40,7 @@ /* Powerdomain flags */ #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ -#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits - * in MEM bank 1 position. This is - * true for OMAP3430 - */ + /* * Number of memory banks that are power-controllable. On OMAP3430, the @@ -90,15 +85,15 @@ struct powerdomain { /* Used to represent the OMAP chip types containing this pwrdm */ const struct omap_chip_id omap_chip; + /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ + const u8 dep_bit; + /* Powerdomains that can be told to wake this powerdomain up */ struct pwrdm_dep *wkdep_srcs; /* Powerdomains that can be told to keep this pwrdm from inactivity */ struct pwrdm_dep *sleepdep_srcs; - /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ - const u8 dep_bit; - /* Possible powerdomain power states */ const u8 pwrsts; @@ -123,11 +118,11 @@ struct powerdomain { struct list_head node; int state; - unsigned state_counter[PWRDM_MAX_PWRSTS]; + unsigned state_counter[4]; #ifdef CONFIG_PM_DEBUG s64 timer; - s64 state_timer[PWRDM_MAX_PWRSTS]; + s64 state_timer[4]; #endif }; diff --git a/trunk/arch/arm/plat-omap/include/plat/serial.h b/trunk/arch/arm/plat-omap/include/plat/serial.h index f5a4a92393ef..9951345a25d6 100644 --- a/trunk/arch/arm/plat-omap/include/plat/serial.h +++ b/trunk/arch/arm/plat-omap/include/plat/serial.h @@ -53,7 +53,6 @@ #ifndef __ASSEMBLER__ extern void __init omap_serial_early_init(void); extern void omap_serial_init(void); -extern void omap_serial_init_port(int port); extern int omap_uart_can_sleep(void); extern void omap_uart_check_wakeup(void); extern void omap_uart_prepare_suspend(void); diff --git a/trunk/arch/arm/plat-omap/include/plat/smp.h b/trunk/arch/arm/plat-omap/include/plat/smp.h index 8983d54c4fd2..dcaa8fde7063 100644 --- a/trunk/arch/arm/plat-omap/include/plat/smp.h +++ b/trunk/arch/arm/plat-omap/include/plat/smp.h @@ -28,8 +28,6 @@ /* Needed for secondary core boot */ extern void omap_secondary_startup(void); -extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); -extern void omap_auxcoreboot_addr(u32 cpu_addr); /* * We use Soft IRQ1 as the IPI diff --git a/trunk/arch/arm/plat-omap/mux.c b/trunk/arch/arm/plat-omap/mux.c index 06703635ace1..05aebcad215b 100644 --- a/trunk/arch/arm/plat-omap/mux.c +++ b/trunk/arch/arm/plat-omap/mux.c @@ -54,12 +54,8 @@ int __init_or_module omap_cfg_reg(const unsigned long index) { struct pin_config *reg; - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { - printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", - index); - WARN_ON(1); - return -EINVAL; - } + if (cpu_is_omap44xx()) + return 0; if (mux_cfg == NULL) { printk(KERN_ERR "Pin mux table not initialized\n"); diff --git a/trunk/arch/arm/plat-omap/omap_device.c b/trunk/arch/arm/plat-omap/omap_device.c index 1e5648d3e3d8..bb16e624a557 100644 --- a/trunk/arch/arm/plat-omap/omap_device.c +++ b/trunk/arch/arm/plat-omap/omap_device.c @@ -134,18 +134,18 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) break; - read_persistent_clock(&a); + getnstimeofday(&a); /* XXX check return code */ odpl->activate_func(od); - read_persistent_clock(&b); + getnstimeofday(&b); c = timespec_sub(b, a); - act_lat = timespec_to_ns(&c); + act_lat = timespec_to_ns(&c) * NSEC_PER_USEC; pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " - "%llu nsec\n", od->pdev.name, od->pm_lat_level, + "%llu usec\n", od->pdev.name, od->pm_lat_level, act_lat); WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " @@ -190,18 +190,18 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) od->_dev_wakeup_lat_limit)) break; - read_persistent_clock(&a); + getnstimeofday(&a); /* XXX check return code */ odpl->deactivate_func(od); - read_persistent_clock(&b); + getnstimeofday(&b); c = timespec_sub(b, a); - deact_lat = timespec_to_ns(&c); + deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC; pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " - "%llu nsec\n", od->pdev.name, od->pm_lat_level, + "%llu usec\n", od->pdev.name, od->pm_lat_level, deact_lat); WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " @@ -459,7 +459,7 @@ int omap_device_enable(struct platform_device *pdev) ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT); od->dev_wakeup_lat = 0; - od->_dev_wakeup_lat_limit = UINT_MAX; + od->_dev_wakeup_lat_limit = INT_MAX; od->_state = OMAP_DEVICE_STATE_ENABLED; return ret; diff --git a/trunk/arch/arm/plat-omap/sram.c b/trunk/arch/arm/plat-omap/sram.c index d8d5094b37ed..ad2bf07d30b5 100644 --- a/trunk/arch/arm/plat-omap/sram.c +++ b/trunk/arch/arm/plat-omap/sram.c @@ -48,10 +48,8 @@ #define OMAP3_SRAM_VA 0xfe400000 #define OMAP3_SRAM_PUB_PA 0x40208000 #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) -#define OMAP4_SRAM_PA 0x40300000 -#define OMAP4_SRAM_VA 0xfe400000 -#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) -#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) +#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ +#define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/ #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) #define SRAM_BOOTLOADER_SZ 0x00 @@ -142,10 +140,6 @@ void __init omap_detect_sram(void) } else { omap_sram_size = 0x8000; /* 32K */ } - } else if (cpu_is_omap44xx()) { - omap_sram_base = OMAP4_SRAM_PUB_VA; - omap_sram_start = OMAP4_SRAM_PUB_PA; - omap_sram_size = 0xa000; /* 40K */ } else { omap_sram_base = OMAP2_SRAM_PUB_VA; omap_sram_start = OMAP2_SRAM_PUB_PA; @@ -159,7 +153,7 @@ void __init omap_detect_sram(void) } else if (cpu_is_omap44xx()) { omap_sram_base = OMAP4_SRAM_VA; omap_sram_start = OMAP4_SRAM_PA; - omap_sram_size = 0xe000; /* 56K */ + omap_sram_size = 0x8000; /* 32K */ } else { omap_sram_base = OMAP2_SRAM_VA; omap_sram_start = OMAP2_SRAM_PA; diff --git a/trunk/arch/arm/plat-omap/usb.c b/trunk/arch/arm/plat-omap/usb.c index d3bf17cd36f3..51033a4503c3 100644 --- a/trunk/arch/arm/plat-omap/usb.c +++ b/trunk/arch/arm/plat-omap/usb.c @@ -137,13 +137,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) if (is_device) { if (cpu_is_omap24xx()) omap_cfg_reg(J20_24XX_USB0_PUEN); - else if (cpu_is_omap7xx()) { - omap_cfg_reg(AA17_7XX_USB_DM); - omap_cfg_reg(W16_7XX_USB_PU_EN); - omap_cfg_reg(W17_7XX_USB_VBUSI); - omap_cfg_reg(W18_7XX_USB_DMCK_OUT); - omap_cfg_reg(W19_7XX_USB_DCRST); - } else + else omap_cfg_reg(W4_USB_PUEN); } diff --git a/trunk/arch/powerpc/Kconfig b/trunk/arch/powerpc/Kconfig index 0df57466e783..2ba14e77296c 100644 --- a/trunk/arch/powerpc/Kconfig +++ b/trunk/arch/powerpc/Kconfig @@ -56,16 +56,6 @@ config IRQ_PER_CPU bool default y -config NR_IRQS - int "Number of virtual interrupt numbers" - range 32 512 - default "512" - help - This defines the number of virtual interrupt numbers the kernel - can manage. Virtual interrupt numbers are what you see in - /proc/interrupts. If you configure your system to have too few, - drivers will fail to load or worse - handle with care. - config STACKTRACE_SUPPORT bool default y @@ -209,14 +199,24 @@ config DEFAULT_UIMAGE config REDBOOT bool +config HIBERNATE_32 + bool + depends on (PPC_PMAC && !SMP) || BROKEN + default y + +config HIBERNATE_64 + bool + depends on BROKEN || (PPC_PMAC64 && EXPERIMENTAL) + default y + config ARCH_HIBERNATION_POSSIBLE bool + depends on (PPC64 && HIBERNATE_64) || (PPC32 && HIBERNATE_32) default y config ARCH_SUSPEND_POSSIBLE def_bool y - depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \ - PPC_85xx || PPC_86xx + depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx config PPC_DCR_NATIVE bool @@ -320,10 +320,6 @@ config HOTPLUG_CPU Say N if you are unsure. -config ARCH_CPU_PROBE_RELEASE - def_bool y - depends on HOTPLUG_CPU - config ARCH_ENABLE_MEMORY_HOTPLUG def_bool y @@ -382,19 +378,6 @@ config IRQ_ALL_CPUS CPU. Generally saying Y is safe, although some problems have been reported with SMP Power Macintoshes with this option enabled. -config SPARSE_IRQ - bool "Support sparse irq numbering" - default y - help - This enables support for sparse irqs. This is useful for distro - kernels that want to define a high CONFIG_NR_CPUS value but still - want to have low kernel memory footprint on smaller machines. - - ( Sparse IRQs can also be beneficial on NUMA boxes, as they spread - out the irq_desc[] array in a more NUMA-friendly way. ) - - If you don't know what to do here, say Y. - config NUMA bool "NUMA support" depends on PPC64 @@ -669,14 +652,6 @@ config FSL_PCI select PPC_INDIRECT_PCI select PCI_QUIRKS -config FSL_PMC - bool - default y - depends on SUSPEND && (PPC_85xx || PPC_86xx) - help - Freescale MPC85xx/MPC86xx power management controller support - (suspend/resume). For MPC83xx see platforms/83xx/suspend.c - config 4xx_SOC bool diff --git a/trunk/arch/powerpc/boot/dts/canyonlands.dts b/trunk/arch/powerpc/boot/dts/canyonlands.dts index cd56bb5b347b..c920170b7dfe 100644 --- a/trunk/arch/powerpc/boot/dts/canyonlands.dts +++ b/trunk/arch/powerpc/boot/dts/canyonlands.dts @@ -352,7 +352,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -382,7 +381,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; diff --git a/trunk/arch/powerpc/boot/dts/eiger.dts b/trunk/arch/powerpc/boot/dts/eiger.dts index 48bcf7187924..c4a934f2e886 100644 --- a/trunk/arch/powerpc/boot/dts/eiger.dts +++ b/trunk/arch/powerpc/boot/dts/eiger.dts @@ -316,7 +316,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -346,7 +345,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -377,8 +375,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; /* emac2&3 only */ phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII1>; @@ -407,8 +403,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; /* emac2&3 only */ phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII1>; diff --git a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts index c86114e93f1e..910944edd886 100644 --- a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -118,12 +118,6 @@ }; }; - nvram@3,0 { - device_type = "nvram"; - compatible = "simtek,stk14ca8"; - reg = <0x3 0x0 0x20000>; - }; - fpga@4,0 { compatible = "gef,ppc9a-fpga-regs"; reg = <0x4 0x0 0x40>; diff --git a/trunk/arch/powerpc/boot/dts/gef_sbc310.dts b/trunk/arch/powerpc/boot/dts/gef_sbc310.dts index 820c2b355ab1..2107d3c7cfe1 100644 --- a/trunk/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/trunk/arch/powerpc/boot/dts/gef_sbc310.dts @@ -115,12 +115,6 @@ }; }; - nvram@3,0 { - device_type = "nvram"; - compatible = "simtek,stk14ca8"; - reg = <0x3 0x0 0x20000>; - }; - fpga@4,0 { compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; diff --git a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts index 30911adefc8e..35a63183eecc 100644 --- a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts @@ -84,12 +84,6 @@ 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) - nvram@3,0 { - device_type = "nvram"; - compatible = "simtek,stk14ca8"; - reg = <0x3 0x0 0x20000>; - }; - fpga@4,0 { compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; diff --git a/trunk/arch/powerpc/boot/dts/glacier.dts b/trunk/arch/powerpc/boot/dts/glacier.dts index f6f618939293..f3787a27f634 100644 --- a/trunk/arch/powerpc/boot/dts/glacier.dts +++ b/trunk/arch/powerpc/boot/dts/glacier.dts @@ -292,7 +292,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -322,7 +321,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -353,8 +351,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; /* emac2&3 only */ phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII1>; @@ -383,8 +379,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; /* emac2&3 only */ phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII1>; diff --git a/trunk/arch/powerpc/boot/dts/haleakala.dts b/trunk/arch/powerpc/boot/dts/haleakala.dts index 2b256694eca6..5b2a4947bf82 100644 --- a/trunk/arch/powerpc/boot/dts/haleakala.dts +++ b/trunk/arch/powerpc/boot/dts/haleakala.dts @@ -226,8 +226,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; diff --git a/trunk/arch/powerpc/boot/dts/katmai.dts b/trunk/arch/powerpc/boot/dts/katmai.dts index 51eb6ed5da2d..077819bc3cbd 100644 --- a/trunk/arch/powerpc/boot/dts/katmai.dts +++ b/trunk/arch/powerpc/boot/dts/katmai.dts @@ -16,7 +16,7 @@ / { #address-cells = <2>; - #size-cells = <2>; + #size-cells = <1>; model = "amcc,katmai"; compatible = "amcc,katmai"; dcr-parent = <&{/cpus/cpu@0}>; @@ -49,7 +49,7 @@ memory { device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */ + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */ }; UIC0: interrupt-controller0 { @@ -112,15 +112,7 @@ compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; #address-cells = <2>; #size-cells = <1>; - /* addr-child addr-parent size */ - ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000 - 0xc 0x00000000 0xc 0x00000000 0x20000000 - 0xd 0x00000000 0xd 0x00000000 0x80000000 - 0xd 0x80000000 0xd 0x80000000 0x80000000 - 0xe 0x00000000 0xe 0x00000000 0x80000000 - 0xe 0x80000000 0xe 0x80000000 0x80000000 - 0xf 0x00000000 0xf 0x00000000 0x80000000 - 0xf 0x80000000 0xf 0x80000000 0x80000000>; + ranges; clock-frequency = <0>; /* Filled in by zImage */ SDRAM0: sdram { @@ -253,8 +245,8 @@ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; - /* Inbound 4GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 0 to 0xf */ bus-range = <0x0 0xf>; @@ -297,10 +289,10 @@ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; - /* Inbound 4GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; - /* This drives busses 0x10 to 0x1f */ + /* This drives busses 10 to 0x1f */ bus-range = <0x10 0x1f>; /* Legacy interrupts (note the weird polarity, the bridge seems @@ -338,10 +330,10 @@ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; - /* Inbound 4GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; - /* This drives busses 0x20 to 0x2f */ + /* This drives busses 10 to 0x1f */ bus-range = <0x20 0x2f>; /* Legacy interrupts (note the weird polarity, the bridge seems @@ -379,10 +371,10 @@ ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>; - /* Inbound 4GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; - /* This drives busses 0x30 to 0x3f */ + /* This drives busses 10 to 0x1f */ bus-range = <0x30 0x3f>; /* Legacy interrupts (note the weird polarity, the bridge seems diff --git a/trunk/arch/powerpc/boot/dts/kilauea.dts b/trunk/arch/powerpc/boot/dts/kilauea.dts index 083e68eeaca4..c46561456ede 100644 --- a/trunk/arch/powerpc/boot/dts/kilauea.dts +++ b/trunk/arch/powerpc/boot/dts/kilauea.dts @@ -272,8 +272,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; @@ -302,8 +300,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; diff --git a/trunk/arch/powerpc/boot/dts/kmeter1.dts b/trunk/arch/powerpc/boot/dts/kmeter1.dts index 65b8b4f27efe..167044f7de1d 100644 --- a/trunk/arch/powerpc/boot/dts/kmeter1.dts +++ b/trunk/arch/powerpc/boot/dts/kmeter1.dts @@ -59,13 +59,6 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; /* Filled in by U-Boot */ - pmc: power@b00 { - compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 0x8>; - interrupt-parent = <&ipic>; - }; - i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/trunk/arch/powerpc/boot/dts/makalu.dts b/trunk/arch/powerpc/boot/dts/makalu.dts index 63d48b632c84..ffc246e72670 100644 --- a/trunk/arch/powerpc/boot/dts/makalu.dts +++ b/trunk/arch/powerpc/boot/dts/makalu.dts @@ -227,8 +227,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x0000003f>; /* Start at 6 */ rgmii-device = <&RGMII0>; @@ -257,8 +255,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; - tx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; diff --git a/trunk/arch/powerpc/boot/dts/mpc832x_mds.dts b/trunk/arch/powerpc/boot/dts/mpc832x_mds.dts index 05ad8c98e527..436c9c671dd9 100644 --- a/trunk/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -79,13 +79,6 @@ reg = <0x200 0x100>; }; - pmc: power@b00 { - compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 0x8>; - interrupt-parent = <&ipic>; - }; - i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -170,7 +163,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x4c>; fsl,descriptor-types-mask = <0x0122003f>; - sleep = <&pmc 0x03000000>; }; ipic: pic@700 { @@ -436,6 +428,5 @@ 0xe0008300 0x8>; /* config space access registers */ compatible = "fsl,mpc8349-pci"; device_type = "pci"; - sleep = <&pmc 0x00010000>; }; }; diff --git a/trunk/arch/powerpc/boot/dts/mpc832x_rdb.dts b/trunk/arch/powerpc/boot/dts/mpc832x_rdb.dts index f4fadb23ad6f..9a0952f74b81 100644 --- a/trunk/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/trunk/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -62,13 +62,6 @@ reg = <0x200 0x100>; }; - pmc: power@b00 { - compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 0x8>; - interrupt-parent = <&ipic>; - }; - i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -148,7 +141,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x4c>; fsl,descriptor-types-mask = <0x0122003f>; - sleep = <&pmc 0x03000000>; }; ipic:pic@700 { @@ -368,6 +360,5 @@ 0xe0008300 0x8>; /* config space access registers */ compatible = "fsl,mpc8349-pci"; device_type = "pci"; - sleep = <&pmc 0x00010000>; }; }; diff --git a/trunk/arch/powerpc/boot/dts/mpc836x_mds.dts b/trunk/arch/powerpc/boot/dts/mpc836x_mds.dts index 45cfa1c50a2a..39ff4c829caf 100644 --- a/trunk/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -99,13 +99,6 @@ reg = <0x200 0x100>; }; - pmc: power@b00 { - compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 0x8>; - interrupt-parent = <&ipic>; - }; - i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -201,7 +194,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x7e>; fsl,descriptor-types-mask = <0x01010ebf>; - sleep = <&pmc 0x03000000>; }; ipic: pic@700 { @@ -478,6 +470,5 @@ 0xe0008300 0x8>; /* config space access registers */ compatible = "fsl,mpc8349-pci"; device_type = "pci"; - sleep = <&pmc 0x00010000>; }; }; diff --git a/trunk/arch/powerpc/boot/dts/mpc836x_rdk.dts b/trunk/arch/powerpc/boot/dts/mpc836x_rdk.dts index bdf4459677b1..6315d6fcc58a 100644 --- a/trunk/arch/powerpc/boot/dts/mpc836x_rdk.dts +++ b/trunk/arch/powerpc/boot/dts/mpc836x_rdk.dts @@ -71,13 +71,6 @@ reg = <0x200 0x100>; }; - pmc: power@b00 { - compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 0x8>; - interrupt-parent = <&ipic>; - }; - i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -168,7 +161,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x7e>; fsl,descriptor-types-mask = <0x01010ebf>; - sleep = <&pmc 0x03000000>; }; ipic: interrupt-controller@700 { @@ -463,7 +455,6 @@ 0xa800 0 0 2 &ipic 20 8 0xa800 0 0 3 &ipic 21 8 0xa800 0 0 4 &ipic 18 8>; - sleep = <&pmc 0x00010000>; /* filled by u-boot */ bus-range = <0 0>; clock-frequency = <0>; diff --git a/trunk/arch/powerpc/boot/dts/mpc8568mds.dts b/trunk/arch/powerpc/boot/dts/mpc8568mds.dts index 6d892ba74e55..00c2bbda7013 100644 --- a/trunk/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc8568mds.dts @@ -40,8 +40,6 @@ i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K - sleep = <&pmc 0x00008000 // core - &pmc 0x00004000>; // timebase timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -96,41 +94,31 @@ interrupts = <16 2>; }; - i2c-sleep-nexus { + i2c@3000 { #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - sleep = <&pmc 0x00000004>; - ranges; - - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - interrupts = <3 1>; - interrupt-parent = <&mpic>; - }; + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; }; + }; - i2c@3100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - compatible = "fsl-i2c"; - reg = <0x3100 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; }; dma@21300 { @@ -140,8 +128,6 @@ reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; - sleep = <&pmc 0x00000400>; - dma-channel@0 { compatible = "fsl,mpc8568-dma-channel", "fsl,eloplus-dma-channel"; @@ -190,7 +176,6 @@ interrupt-parent = <&mpic>; tbi-handle = <&tbi0>; phy-handle = <&phy2>; - sleep = <&pmc 0x00000080>; mdio@520 { #address-cells = <1>; @@ -243,7 +228,6 @@ interrupt-parent = <&mpic>; tbi-handle = <&tbi1>; phy-handle = <&phy3>; - sleep = <&pmc 0x00000040>; mdio@520 { #address-cells = <1>; @@ -258,47 +242,30 @@ }; }; - duart-sleep-nexus { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - sleep = <&pmc 0x00000002>; - ranges; - - serial0: serial@4500 { - cell-index = <0>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4500 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; - - serial1: serial@4600 { - cell-index = <1>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4600 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; }; - global-utilities@e0000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts"; + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8548-guts"; reg = <0xe0000 0x1000>; - ranges = <0 0xe0000 0x1000>; fsl,has-rstcr; + }; - pmc: power@70 { - compatible = "fsl,mpc8568-pmc", - "fsl,mpc8548-pmc"; - reg = <0x70 0x20>; - }; + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; }; crypto@30000 { @@ -310,7 +277,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0xfe>; fsl,descriptor-types-mask = <0x12b0ebf>; - sleep = <&pmc 0x01000000>; }; mpic: pic@40000 { @@ -410,7 +376,6 @@ compatible = "fsl,qe"; ranges = <0x0 0xe0080000 0x40000>; reg = <0xe0080000 0x480>; - sleep = <&pmc 0x00000800>; brg-frequency = <0>; bus-frequency = <396000000>; fsl,qe-num-riscs = <2>; @@ -544,7 +509,6 @@ bus-range = <0 255>; ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>; - sleep = <&pmc 0x80000000>; clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; @@ -570,7 +534,6 @@ bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>; - sleep = <&pmc 0x20000000>; clock-frequency = <33333333>; #interrupt-cells = <1>; #size-cells = <2>; @@ -607,7 +570,5 @@ 55 2 /* msg2_tx */ 56 2 /* msg2_rx */>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00080000 /* controller */ - &pmc 0x00040000>; /* message unit */ }; }; diff --git a/trunk/arch/powerpc/boot/dts/mpc8569mds.dts b/trunk/arch/powerpc/boot/dts/mpc8569mds.dts index 795eb362fcf9..1e3ec8f059bf 100644 --- a/trunk/arch/powerpc/boot/dts/mpc8569mds.dts +++ b/trunk/arch/powerpc/boot/dts/mpc8569mds.dts @@ -41,8 +41,6 @@ i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K - sleep = <&pmc 0x00008000 // core - &pmc 0x00004000>; // timebase timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -61,7 +59,6 @@ reg = <0xe0005000 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x08000000>; ranges = <0x0 0x0 0xfe000000 0x02000000 0x1 0x0 0xf8000000 0x00008000 @@ -161,69 +158,51 @@ interrupts = <18 2>; }; - i2c-sleep-nexus { + i2c@3000 { #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - sleep = <&pmc 0x00000004>; - ranges; - - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - interrupts = <3 1>; - interrupt-parent = <&mpic>; - }; - }; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; - i2c@3100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - compatible = "fsl-i2c"; - reg = <0x3100 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; }; }; - duart-sleep-nexus { + i2c@3100 { #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - sleep = <&pmc 0x00000002>; - ranges; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; - serial0: serial@4500 { - cell-index = <0>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4500 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; - serial1: serial@4600 { - cell-index = <1>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4600 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; }; L2: l2-cache-controller@20000 { @@ -281,7 +260,6 @@ reg = <0x2e000 0x1000>; interrupts = <72 0x8>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00200000>; /* Filled in by U-Boot */ clock-frequency = <0>; status = "disabled"; @@ -298,7 +276,6 @@ fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0xbfe>; fsl,descriptor-types-mask = <0x3ab0ebf>; - sleep = <&pmc 0x01000000>; }; mpic: pic@40000 { @@ -327,18 +304,9 @@ }; global-utilities@e0000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts"; + compatible = "fsl,mpc8569-guts"; reg = <0xe0000 0x1000>; - ranges = <0 0xe0000 0x1000>; fsl,has-rstcr; - - pmc: power@70 { - compatible = "fsl,mpc8569-pmc", - "fsl,mpc8548-pmc"; - reg = <0x70 0x20>; - }; }; par_io@e0100 { @@ -454,7 +422,6 @@ compatible = "fsl,qe"; ranges = <0x0 0xe0080000 0x40000>; reg = <0xe0080000 0x480>; - sleep = <&pmc 0x00000800>; brg-frequency = <0>; bus-frequency = <0>; fsl,qe-num-riscs = <4>; @@ -717,7 +684,6 @@ bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; - sleep = <&pmc 0x20000000>; clock-frequency = <33333333>; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; @@ -748,6 +714,5 @@ 55 2 /* msg2_tx */ 56 2 /* msg2_rx */>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00080000>; }; }; diff --git a/trunk/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/trunk/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 9535ce68caae..f468d215f716 100644 --- a/trunk/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/trunk/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -35,8 +35,6 @@ i-cache-line-size = <32>; d-cache-size = <32768>; // L1 i-cache-size = <32768>; // L1 - sleep = <&pmc 0x00008000 0 // core - &pmc 0x00004000 0>; // timebase timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot @@ -62,7 +60,6 @@ 5 0 0xe8480000 0x00008000 6 0 0xe84c0000 0x00008000 3 0 0xe8000000 0x00000020>; - sleep = <&pmc 0x08000000 0>; flash@0,0 { compatible = "cfi-flash"; @@ -108,8 +105,6 @@ compatible = "fsl,fpga-pixis"; reg = <3 0 0x20>; ranges = <0 3 0 0x20>; - interrupt-parent = <&mpic>; - interrupts = <8 8>; sdcsr_pio: gpio-controller@a { #gpio-cells = <2>; @@ -168,7 +163,6 @@ reg = <0x3100 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00000004 0>; dfsrr; }; @@ -180,7 +174,6 @@ clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00000002 0>; }; serial1: serial@4600 { @@ -191,7 +184,6 @@ clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x00000008 0>; }; spi@7000 { @@ -204,7 +196,6 @@ interrupt-parent = <&mpic>; mode = "cpu"; gpios = <&sdcsr_pio 7 0>; - sleep = <&pmc 0x00000800 0>; mmc-slot@0 { compatible = "fsl,mpc8610hpcd-mmc-slot", @@ -222,7 +213,6 @@ reg = <0x2c000 100>; interrupts = <72 2>; interrupt-parent = <&mpic>; - sleep = <&pmc 0x04000000 0>; }; mpic: interrupt-controller@40000 { @@ -251,18 +241,9 @@ }; global-utilities@e0000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "fsl,mpc8610-guts"; reg = <0xe0000 0x1000>; - ranges = <0 0xe0000 0x1000>; fsl,has-rstcr; - - pmc: power@70 { - compatible = "fsl,mpc8610-pmc", - "fsl,mpc8641d-pmc"; - reg = <0x70 0x20>; - }; }; wdt@e4000 { @@ -281,7 +262,6 @@ fsl,playback-dma = <&dma00>; fsl,capture-dma = <&dma01>; fsl,fifo-depth = <8>; - sleep = <&pmc 0 0x08000000>; }; ssi@16100 { @@ -291,7 +271,6 @@ interrupt-parent = <&mpic>; interrupts = <63 2>; fsl,fifo-depth = <8>; - sleep = <&pmc 0 0x04000000>; }; dma@21300 { @@ -301,7 +280,6 @@ cell-index = <0>; reg = <0x21300 0x4>; /* DMA general status register */ ranges = <0x0 0x21100 0x200>; - sleep = <&pmc 0x00000400 0>; dma00: dma-channel@0 { compatible = "fsl,mpc8610-dma-channel", @@ -344,7 +322,6 @@ cell-index = <1>; reg = <0xc300 0x4>; /* DMA general status register */ ranges = <0x0 0xc100 0x200>; - sleep = <&pmc 0x00000200 0>; dma-channel@0 { compatible = "fsl,mpc8610-dma-channel", @@ -392,7 +369,6 @@ bus-range = <0 0>; ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>; - sleep = <&pmc 0x80000000 0>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <24 2>; @@ -422,7 +398,6 @@ bus-range = <1 3>; ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; - sleep = <&pmc 0x40000000 0>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <26 2>; @@ -499,7 +474,6 @@ 0x0000 0 0 4 &mpic 7 1>; interrupt-parent = <&mpic>; interrupts = <25 2>; - sleep = <&pmc 0x20000000 0>; clock-frequency = <33333333>; }; }; diff --git a/trunk/arch/powerpc/boot/dts/p1020rdb.dts b/trunk/arch/powerpc/boot/dts/p1020rdb.dts deleted file mode 100644 index df5269093af8..000000000000 --- a/trunk/arch/powerpc/boot/dts/p1020rdb.dts +++ /dev/null @@ -1,477 +0,0 @@ -/* - * P1020 RDB Device Tree Source - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/dts-v1/; -/ { - model = "fsl,P1020"; - compatible = "fsl,P1020RDB"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - pci0 = &pci0; - pci1 = &pci1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,P1020@0 { - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - - PowerPC,P1020@1 { - device_type = "cpu"; - reg = <0x1>; - next-level-cache = <&L2>; - }; - }; - - memory { - device_type = "memory"; - }; - - localbus@ffe05000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; - reg = <0 0xffe05000 0 0x1000>; - interrupts = <19 2>; - interrupt-parent = <&mpic>; - - /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ - ranges = <0x0 0x0 0x0 0xef000000 0x01000000 - 0x1 0x0 0x0 0xffa00000 0x00040000 - 0x2 0x0 0x0 0xffb00000 0x00020000>; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - device-width = <1>; - - partition@0 { - /* This location must not be altered */ - /* 256KB for Vitesse 7385 Switch firmware */ - reg = <0x0 0x00040000>; - label = "NOR (RO) Vitesse-7385 Firmware"; - read-only; - }; - - partition@40000 { - /* 256KB for DTB Image */ - reg = <0x00040000 0x00040000>; - label = "NOR (RO) DTB Image"; - read-only; - }; - - partition@80000 { - /* 3.5 MB for Linux Kernel Image */ - reg = <0x00080000 0x00380000>; - label = "NOR (RO) Linux Kernel Image"; - read-only; - }; - - partition@400000 { - /* 11MB for JFFS2 based Root file System */ - reg = <0x00400000 0x00b00000>; - label = "NOR (RW) JFFS2 Root File System"; - }; - - partition@f00000 { - /* This location must not be altered */ - /* 512KB for u-boot Bootloader Image */ - /* 512KB for u-boot Environment Variables */ - reg = <0x00f00000 0x00100000>; - label = "NOR (RO) U-Boot Image"; - read-only; - }; - }; - - nand@1,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p1020-fcm-nand", - "fsl,elbc-fcm-nand"; - reg = <0x1 0x0 0x40000>; - - partition@0 { - /* This location must not be altered */ - /* 1MB for u-boot Bootloader Image */ - reg = <0x0 0x00100000>; - label = "NAND (RO) U-Boot Image"; - read-only; - }; - - partition@100000 { - /* 1MB for DTB Image */ - reg = <0x00100000 0x00100000>; - label = "NAND (RO) DTB Image"; - read-only; - }; - - partition@200000 { - /* 4MB for Linux Kernel Image */ - reg = <0x00200000 0x00400000>; - label = "NAND (RO) Linux Kernel Image"; - read-only; - }; - - partition@600000 { - /* 4MB for Compressed Root file System Image */ - reg = <0x00600000 0x00400000>; - label = "NAND (RO) Compressed RFS Image"; - read-only; - }; - - partition@a00000 { - /* 7MB for JFFS2 based Root file System */ - reg = <0x00a00000 0x00700000>; - label = "NAND (RW) JFFS2 Root File System"; - }; - - partition@1100000 { - /* 15MB for JFFS2 based Root file System */ - reg = <0x01100000 0x00f00000>; - label = "NAND (RW) Writable User area"; - }; - }; - - L2switch@2,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "vitesse-7385"; - reg = <0x2 0x0 0x20000>; - }; - - }; - - soc@ffe00000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "fsl,p1020-immr", "simple-bus"; - ranges = <0x0 0x0 0xffe00000 0x100000>; - bus-frequency = <0>; // Filled out by uboot. - - ecm-law@0 { - compatible = "fsl,ecm-law"; - reg = <0x0 0x1000>; - fsl,num-laws = <12>; - }; - - ecm@1000 { - compatible = "fsl,p1020-ecm", "fsl,ecm"; - reg = <0x1000 0x1000>; - interrupts = <16 2>; - interrupt-parent = <&mpic>; - }; - - memory-controller@2000 { - compatible = "fsl,p1020-memory-controller"; - reg = <0x2000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - }; - - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - }; - - i2c@3100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - compatible = "fsl-i2c"; - reg = <0x3100 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - serial0: serial@4500 { - cell-index = <0>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4500 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; - - serial1: serial@4600 { - cell-index = <1>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4600 0x100>; - clock-frequency = <0>; - interrupts = <42 2>; - interrupt-parent = <&mpic>; - }; - - spi@7000 { - cell-index = <0>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,espi"; - reg = <0x7000 0x1000>; - interrupts = <59 0x2>; - interrupt-parent = <&mpic>; - mode = "cpu"; - - fsl_m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,espi-flash"; - reg = <0>; - linux,modalias = "fsl_m25p80"; - modal = "s25sl128b"; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - /* 512KB for u-boot Bootloader Image */ - reg = <0x0 0x00080000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@80000 { - /* 512KB for DTB Image */ - reg = <0x00080000 0x00080000>; - label = "SPI (RO) DTB Image"; - read-only; - }; - - partition@100000 { - /* 4MB for Linux Kernel Image */ - reg = <0x00100000 0x00400000>; - label = "SPI (RO) Linux Kernel Image"; - read-only; - }; - - partition@500000 { - /* 4MB for Compressed RFS Image */ - reg = <0x00500000 0x00400000>; - label = "SPI (RO) Compressed RFS Image"; - read-only; - }; - - partition@900000 { - /* 7MB for JFFS2 based RFS */ - reg = <0x00900000 0x00700000>; - label = "SPI (RW) JFFS2 RFS"; - }; - }; - }; - - gpio: gpio-controller@f000 { - #gpio-cells = <2>; - compatible = "fsl,mpc8572-gpio"; - reg = <0xf000 0x100>; - interrupts = <47 0x2>; - interrupt-parent = <&mpic>; - gpio-controller; - }; - - L2: l2-cache-controller@20000 { - compatible = "fsl,p1020-l2-cache-controller"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x40000>; // L2,256K - interrupt-parent = <&mpic>; - interrupts = <16 2>; - }; - - dma@21300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eloplus-dma"; - reg = <0x21300 0x4>; - ranges = <0x0 0x21100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <20 2>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <21 2>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <22 2>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <23 2>; - }; - }; - - usb@22000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <28 0x2>; - phy_type = "ulpi"; - }; - - usb@23000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl-usb2-dr"; - reg = <0x23000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <46 0x2>; - phy_type = "ulpi"; - }; - - sdhci@2e000 { - compatible = "fsl,p1020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2>; - interrupt-parent = <&mpic>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - }; - - crypto@30000 { - compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", - "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <45 2 58 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xbfe>; - fsl,descriptor-types-mask = <0x3ab0ebf>; - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x40000 0x40000>; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - }; - - msi@41600 { - compatible = "fsl,p1020-msi", "fsl,mpic-msi"; - reg = <0x41600 0x80>; - msi-available-ranges = <0 0x100>; - interrupts = < - 0xe0 0 - 0xe1 0 - 0xe2 0 - 0xe3 0 - 0xe4 0 - 0xe5 0 - 0xe6 0 - 0xe7 0>; - interrupt-parent = <&mpic>; - }; - - global-utilities@e0000 { //global utilities block - compatible = "fsl,p1020-guts"; - reg = <0xe0000 0x1000>; - fsl,has-rstcr; - }; - }; - - pci0: pcie@ffe09000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0 0xffe09000 0 0x1000>; - bus-range = <0 255>; - ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; - clock-frequency = <33333333>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - pcie@0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x2000000 0x0 0xa0000000 - 0x2000000 0x0 0xa0000000 - 0x0 0x20000000 - - 0x1000000 0x0 0x0 - 0x1000000 0x0 0x0 - 0x0 0x100000>; - }; - }; - - pci1: pcie@ffe0a000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0 0xffe0a000 0 0x1000>; - bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; - clock-frequency = <33333333>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - pcie@0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 - 0x0 0x20000000 - - 0x1000000 0x0 0x0 - 0x1000000 0x0 0x0 - 0x0 0x100000>; - }; - }; -}; diff --git a/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts deleted file mode 100644 index 0fe93d0c8b2e..000000000000 --- a/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts +++ /dev/null @@ -1,363 +0,0 @@ -/* - * P2020 RDB Core0 Device Tree Source in CAMP mode. - * - * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache - * can be shared, all the other devices must be assigned to one core only. - * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, - * eth1, eth2, sdhc, crypto, global-util, pci0. - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/dts-v1/; -/ { - model = "fsl,P2020"; - compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet1 = &enet1; - ethernet2 = &enet2; - serial0 = &serial0; - pci0 = &pci0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,P2020@0 { - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - }; - - memory { - device_type = "memory"; - }; - - soc@ffe00000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "fsl,p2020-immr", "simple-bus"; - ranges = <0x0 0x0 0xffe00000 0x100000>; - bus-frequency = <0>; // Filled out by uboot. - - ecm-law@0 { - compatible = "fsl,ecm-law"; - reg = <0x0 0x1000>; - fsl,num-laws = <12>; - }; - - ecm@1000 { - compatible = "fsl,p2020-ecm", "fsl,ecm"; - reg = <0x1000 0x1000>; - interrupts = <17 2>; - interrupt-parent = <&mpic>; - }; - - memory-controller@2000 { - compatible = "fsl,p2020-memory-controller"; - reg = <0x2000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - }; - - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - }; - - i2c@3100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - compatible = "fsl-i2c"; - reg = <0x3100 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - serial0: serial@4500 { - cell-index = <0>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4500 0x100>; - clock-frequency = <0>; - }; - - spi@7000 { - cell-index = <0>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,espi"; - reg = <0x7000 0x1000>; - interrupts = <59 0x2>; - interrupt-parent = <&mpic>; - mode = "cpu"; - - fsl_m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,espi-flash"; - reg = <0>; - linux,modalias = "fsl_m25p80"; - modal = "s25sl128b"; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - /* 512KB for u-boot Bootloader Image */ - reg = <0x0 0x00080000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@80000 { - /* 512KB for DTB Image */ - reg = <0x00080000 0x00080000>; - label = "SPI (RO) DTB Image"; - read-only; - }; - - partition@100000 { - /* 4MB for Linux Kernel Image */ - reg = <0x00100000 0x00400000>; - label = "SPI (RO) Linux Kernel Image"; - read-only; - }; - - partition@500000 { - /* 4MB for Compressed RFS Image */ - reg = <0x00500000 0x00400000>; - label = "SPI (RO) Compressed RFS Image"; - read-only; - }; - - partition@900000 { - /* 7MB for JFFS2 based RFS */ - reg = <0x00900000 0x00700000>; - label = "SPI (RW) JFFS2 RFS"; - }; - }; - }; - - gpio: gpio-controller@f000 { - #gpio-cells = <2>; - compatible = "fsl,mpc8572-gpio"; - reg = <0xf000 0x100>; - interrupts = <47 0x2>; - interrupt-parent = <&mpic>; - gpio-controller; - }; - - L2: l2-cache-controller@20000 { - compatible = "fsl,p2020-l2-cache-controller"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x80000>; // L2,512K - interrupt-parent = <&mpic>; - interrupts = <16 2>; - }; - - dma@21300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eloplus-dma"; - reg = <0x21300 0x4>; - ranges = <0x0 0x21100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <20 2>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <21 2>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <22 2>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <23 2>; - }; - }; - - usb@22000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <28 0x2>; - phy_type = "ulpi"; - }; - - mdio@24520 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,gianfar-mdio"; - reg = <0x24520 0x20>; - - phy0: ethernet-phy@0 { - interrupt-parent = <&mpic>; - interrupts = <3 1>; - reg = <0x0>; - }; - phy1: ethernet-phy@1 { - interrupt-parent = <&mpic>; - interrupts = <3 1>; - reg = <0x1>; - }; - }; - - mdio@25520 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,gianfar-tbi"; - reg = <0x26520 0x20>; - - tbi0: tbi-phy@11 { - reg = <0x11>; - device_type = "tbi-phy"; - }; - }; - - enet1: ethernet@25000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <1>; - device_type = "network"; - model = "eTSEC"; - compatible = "gianfar"; - reg = <0x25000 0x1000>; - ranges = <0x0 0x25000 0x1000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <35 2 36 2 40 2>; - interrupt-parent = <&mpic>; - tbi-handle = <&tbi0>; - phy-handle = <&phy0>; - phy-connection-type = "sgmii"; - - }; - - enet2: ethernet@26000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <2>; - device_type = "network"; - model = "eTSEC"; - compatible = "gianfar"; - reg = <0x26000 0x1000>; - ranges = <0x0 0x26000 0x1000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <31 2 32 2 33 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy1>; - phy-connection-type = "rgmii-id"; - }; - - sdhci@2e000 { - compatible = "fsl,p2020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2>; - interrupt-parent = <&mpic>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - }; - - crypto@30000 { - compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", - "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <45 2 58 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xbfe>; - fsl,descriptor-types-mask = <0x3ab0ebf>; - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x40000 0x40000>; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - protected-sources = < - 42 76 77 78 79 /* serial1 , dma2 */ - 29 30 34 26 /* enet0, pci1 */ - 0xe0 0xe1 0xe2 0xe3 /* msi */ - 0xe4 0xe5 0xe6 0xe7 - >; - }; - - global-utilities@e0000 { - compatible = "fsl,p2020-guts"; - reg = <0xe0000 0x1000>; - fsl,has-rstcr; - }; - }; - - pci0: pcie@ffe09000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0 0xffe09000 0 0x1000>; - bus-range = <0 255>; - ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; - clock-frequency = <33333333>; - interrupt-parent = <&mpic>; - interrupts = <25 2>; - pcie@0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x2000000 0x0 0xa0000000 - 0x2000000 0x0 0xa0000000 - 0x0 0x20000000 - - 0x1000000 0x0 0x0 - 0x1000000 0x0 0x0 - 0x0 0x100000>; - }; - }; -}; diff --git a/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts deleted file mode 100644 index e95a51285328..000000000000 --- a/trunk/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * P2020 RDB Core1 Device Tree Source in CAMP mode. - * - * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache - * can be shared, all the other devices must be assigned to one core only. - * This dts allows core1 to have l2, dma2, eth0, pci1, msi. - * - * Please note to add "-b 1" for core1's dts compiling. - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/dts-v1/; -/ { - model = "fsl,P2020"; - compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &enet0; - serial0 = &serial0; - pci1 = &pci1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,P2020@1 { - device_type = "cpu"; - reg = <0x1>; - next-level-cache = <&L2>; - }; - }; - - memory { - device_type = "memory"; - }; - - soc@ffe00000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "fsl,p2020-immr", "simple-bus"; - ranges = <0x0 0x0 0xffe00000 0x100000>; - bus-frequency = <0>; // Filled out by uboot. - - serial0: serial@4600 { - cell-index = <1>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x4600 0x100>; - clock-frequency = <0>; - }; - - dma@c300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,eloplus-dma"; - reg = <0xc300 0x4>; - ranges = <0x0 0xc100 0x200>; - cell-index = <1>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <76 2>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <77 2>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <78 2>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <79 2>; - }; - }; - - L2: l2-cache-controller@20000 { - compatible = "fsl,p2020-l2-cache-controller"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x80000>; // L2,512K - interrupt-parent = <&mpic>; - }; - - - enet0: ethernet@24000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <0>; - device_type = "network"; - model = "eTSEC"; - compatible = "gianfar"; - reg = <0x24000 0x1000>; - ranges = <0x0 0x24000 0x1000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <29 2 30 2 34 2>; - interrupt-parent = <&mpic>; - fixed-link = <1 1 1000 0 0>; - phy-connection-type = "rgmii-id"; - - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x40000 0x40000>; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - protected-sources = < - 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */ - 16 20 21 22 23 28 /* L2, dma1, USB */ - 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */ - 72 45 58 25 /* sdhci, crypto , pci */ - >; - }; - - msi@41600 { - compatible = "fsl,p2020-msi", "fsl,mpic-msi"; - reg = <0x41600 0x80>; - msi-available-ranges = <0 0x100>; - interrupts = < - 0xe0 0 - 0xe1 0 - 0xe2 0 - 0xe3 0 - 0xe4 0 - 0xe5 0 - 0xe6 0 - 0xe7 0>; - interrupt-parent = <&mpic>; - }; - }; - - pci1: pcie@ffe0a000 { - compatible = "fsl,mpc8548-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0 0xffe0a000 0 0x1000>; - bus-range = <0 255>; - ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 - 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; - clock-frequency = <33333333>; - interrupt-parent = <&mpic>; - interrupts = <26 2>; - pcie@0 { - reg = <0x0 0x0 0x0 0x0 0x0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x2000000 0x0 0xc0000000 - 0x2000000 0x0 0xc0000000 - 0x0 0x20000000 - - 0x1000000 0x0 0x0 - 0x1000000 0x0 0x0 - 0x0 0x100000>; - }; - }; -}; diff --git a/trunk/arch/powerpc/boot/dts/p4080ds.dts b/trunk/arch/powerpc/boot/dts/p4080ds.dts deleted file mode 100644 index 6b29eab05362..000000000000 --- a/trunk/arch/powerpc/boot/dts/p4080ds.dts +++ /dev/null @@ -1,554 +0,0 @@ -/* - * P4080DS Device Tree Source - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/dts-v1/; - -/ { - model = "fsl,P4080DS"; - compatible = "fsl,P4080DS"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ccsr = &soc; - - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - pci0 = &pci0; - pci1 = &pci1; - pci2 = &pci2; - usb0 = &usb0; - usb1 = &usb1; - dma0 = &dma0; - dma1 = &dma1; - sdhc = &sdhc; - - rio0 = &rapidio0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,4080@0 { - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - }; - }; - cpu1: PowerPC,4080@1 { - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - }; - }; - cpu2: PowerPC,4080@2 { - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2_2>; - L2_2: l2-cache { - }; - }; - cpu3: PowerPC,4080@3 { - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2_3>; - L2_3: l2-cache { - }; - }; - cpu4: PowerPC,4080@4 { - device_type = "cpu"; - reg = <4>; - next-level-cache = <&L2_4>; - L2_4: l2-cache { - }; - }; - cpu5: PowerPC,4080@5 { - device_type = "cpu"; - reg = <5>; - next-level-cache = <&L2_5>; - L2_5: l2-cache { - }; - }; - cpu6: PowerPC,4080@6 { - device_type = "cpu"; - reg = <6>; - next-level-cache = <&L2_6>; - L2_6: l2-cache { - }; - }; - cpu7: PowerPC,4080@7 { - device_type = "cpu"; - reg = <7>; - next-level-cache = <&L2_7>; - L2_7: l2-cache { - }; - }; - }; - - memory { - device_type = "memory"; - }; - - soc: soc@ffe000000 { - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - - corenet-law@0 { - compatible = "fsl,corenet-law"; - reg = <0x0 0x1000>; - fsl,num-laws = <32>; - }; - - memory-controller@8000 { - compatible = "fsl,p4080-memory-controller"; - reg = <0x8000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <0x12 2>; - }; - - memory-controller@9000 { - compatible = "fsl,p4080-memory-controller"; - reg = <0x9000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <0x12 2>; - }; - - corenet-cf@18000 { - compatible = "fsl,corenet-cf"; - reg = <0x18000 0x1000>; - fsl,ccf-num-csdids = <32>; - fsl,ccf-num-snoopids = <32>; - }; - - iommu@20000 { - compatible = "fsl,p4080-pamu"; - reg = <0x20000 0x10000>; - interrupts = <24 2>; - interrupt-parent = <&mpic>; - }; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x40000 0x40000>; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - }; - - dma0: dma@100300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p4080-dma", "fsl,eloplus-dma"; - reg = <0x100300 0x4>; - ranges = <0x0 0x100100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <28 2>; - }; - dma-channel@80 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <29 2>; - }; - dma-channel@100 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <30 2>; - }; - dma-channel@180 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <31 2>; - }; - }; - - dma1: dma@101300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p4080-dma", "fsl,eloplus-dma"; - reg = <0x101300 0x4>; - ranges = <0x0 0x101100 0x200>; - cell-index = <1>; - dma-channel@0 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <32 2>; - }; - dma-channel@80 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <33 2>; - }; - dma-channel@100 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <34 2>; - }; - dma-channel@180 { - compatible = "fsl,p4080-dma-channel", - "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <35 2>; - }; - }; - - spi@110000 { - cell-index = <0>; - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,espi"; - reg = <0x110000 0x1000>; - interrupts = <53 0x2>; - interrupt-parent = <&mpic>; - espi,num-ss-bits = <4>; - mode = "cpu"; - - fsl_m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,espi-flash"; - reg = <0>; - linux,modalias = "fsl_m25p80"; - spi-max-frequency = <40000000>; /* input clock */ - partition@u-boot { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - partition@kernel { - label = "kernel"; - reg = <0x00100000 0x00500000>; - read-only; - }; - partition@dtb { - label = "dtb"; - reg = <0x00600000 0x00100000>; - read-only; - }; - partition@fs { - label = "file system"; - reg = <0x00700000 0x00900000>; - }; - }; - }; - - sdhc: sdhc@114000 { - compatible = "fsl,p4080-esdhc", "fsl,esdhc"; - reg = <0x114000 0x1000>; - interrupts = <48 2>; - interrupt-parent = <&mpic>; - }; - - i2c@118000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x118000 0x100>; - interrupts = <38 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - i2c@118100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - compatible = "fsl-i2c"; - reg = <0x118100 0x100>; - interrupts = <38 2>; - interrupt-parent = <&mpic>; - dfsrr; - eeprom@51 { - compatible = "at24,24c256"; - reg = <0x51>; - }; - eeprom@52 { - compatible = "at24,24c256"; - reg = <0x52>; - }; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - interrupts = <0 0x1>; - interrupt-parent = <&mpic>; - }; - }; - - i2c@119000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <2>; - compatible = "fsl-i2c"; - reg = <0x119000 0x100>; - interrupts = <39 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - i2c@119100 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <3>; - compatible = "fsl-i2c"; - reg = <0x119100 0x100>; - interrupts = <39 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - serial0: serial@11c500 { - cell-index = <0>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x11c500 0x100>; - clock-frequency = <0>; - interrupts = <36 2>; - interrupt-parent = <&mpic>; - }; - - serial1: serial@11c600 { - cell-index = <1>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x11c600 0x100>; - clock-frequency = <0>; - interrupts = <36 2>; - interrupt-parent = <&mpic>; - }; - - serial2: serial@11d500 { - cell-index = <2>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x11d500 0x100>; - clock-frequency = <0>; - interrupts = <37 2>; - interrupt-parent = <&mpic>; - }; - - serial3: serial@11d600 { - cell-index = <3>; - device_type = "serial"; - compatible = "ns16550"; - reg = <0x11d600 0x100>; - clock-frequency = <0>; - interrupts = <37 2>; - interrupt-parent = <&mpic>; - }; - - gpio0: gpio@130000 { - compatible = "fsl,p4080-gpio"; - reg = <0x130000 0x1000>; - interrupts = <55 2>; - interrupt-parent = <&mpic>; - #gpio-cells = <2>; - gpio-controller; - }; - - usb0: usb@210000 { - compatible = "fsl,p4080-usb2-mph", - "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&mpic>; - interrupts = <44 0x2>; - phy_type = "ulpi"; - }; - - usb1: usb@211000 { - compatible = "fsl,p4080-usb2-dr", - "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; - reg = <0x211000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&mpic>; - interrupts = <45 0x2>; - dr_mode = "host"; - phy_type = "ulpi"; - }; - }; - - rapidio0: rapidio@ffe0c0000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "fsl,rapidio-delta"; - reg = <0xf 0xfe0c0000 0 0x20000>; - ranges = <0 0 0xf 0xf5000000 0 0x01000000>; - interrupt-parent = <&mpic>; - /* err_irq bell_outb_irq bell_inb_irq - msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */ - interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>; - }; - - localbus@ffe124000 { - compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; - reg = <0xf 0xfe124000 0 0x1000>; - interrupts = <25 2>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0xf 0xe8000000 0x08000000>; - - flash@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x08000000>; - bank-width = <2>; - device-width = <2>; - }; - }; - - pci0: pcie@ffe200000 { - compatible = "fsl,p4080-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xf 0xfe200000 0 0x1000>; - bus-range = <0x0 0xff>; - ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 - 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; - clock-frequency = <0x1fca055>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 40 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 - >; - pcie@0 { - reg = <0 0 0 0 0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x02000000 0 0xe0000000 - 0x02000000 0 0xe0000000 - 0 0x20000000 - - 0x01000000 0 0x00000000 - 0x01000000 0 0x00000000 - 0 0x00010000>; - }; - }; - - pci1: pcie@ffe201000 { - compatible = "fsl,p4080-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xf 0xfe201000 0 0x1000>; - bus-range = <0 0xff>; - ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 - 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; - clock-frequency = <0x1fca055>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 41 1 - 0000 0 0 2 &mpic 5 1 - 0000 0 0 3 &mpic 6 1 - 0000 0 0 4 &mpic 7 1 - >; - pcie@0 { - reg = <0 0 0 0 0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x02000000 0 0xe0000000 - 0x02000000 0 0xe0000000 - 0 0x20000000 - - 0x01000000 0 0x00000000 - 0x01000000 0 0x00000000 - 0 0x00010000>; - }; - }; - - pci2: pcie@ffe202000 { - compatible = "fsl,p4080-pcie"; - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xf 0xfe202000 0 0x1000>; - bus-range = <0x0 0xff>; - ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 - 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; - clock-frequency = <0x1fca055>; - interrupt-parent = <&mpic>; - interrupts = <16 2>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = < - /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 42 1 - 0000 0 0 2 &mpic 9 1 - 0000 0 0 3 &mpic 10 1 - 0000 0 0 4 &mpic 11 1 - >; - pcie@0 { - reg = <0 0 0 0 0>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - ranges = <0x02000000 0 0xe0000000 - 0x02000000 0 0xe0000000 - 0 0x20000000 - - 0x01000000 0 0x00000000 - 0x01000000 0 0x00000000 - 0 0x00010000>; - }; - }; - -}; diff --git a/trunk/arch/powerpc/boot/dts/redwood.dts b/trunk/arch/powerpc/boot/dts/redwood.dts index d2af32e2bf7a..ad402c488741 100644 --- a/trunk/arch/powerpc/boot/dts/redwood.dts +++ b/trunk/arch/powerpc/boot/dts/redwood.dts @@ -226,7 +226,6 @@ max-frame-size = <9000>; rx-fifo-size = <4096>; tx-fifo-size = <2048>; - rx-fifo-size-gige = <16384>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; diff --git a/trunk/arch/powerpc/boot/dts/yosemite.dts b/trunk/arch/powerpc/boot/dts/yosemite.dts index 64923245f0e5..1fa3cb4c4ebb 100644 --- a/trunk/arch/powerpc/boot/dts/yosemite.dts +++ b/trunk/arch/powerpc/boot/dts/yosemite.dts @@ -282,10 +282,20 @@ /* Inbound 2GB range starting at 0 */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + /* Bamboo has all 4 IRQ pins tied together per slot */ interrupt-map-mask = <0xf800 0x0 0x0 0x0>; interrupt-map = < - /* IDSEL 12 */ - 0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8 + /* IDSEL 1 */ + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 + + /* IDSEL 2 */ + 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8 + + /* IDSEL 3 */ + 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8 + + /* IDSEL 4 */ + 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; }; diff --git a/trunk/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/trunk/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index 6cd2cd65c2cd..28980738776c 100644 --- a/trunk/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/trunk/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -218,7 +218,7 @@ CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set # CONFIG_PPC_I8259 is not set # CONFIG_PPC_RTAS is not set -CONFIG_MMIO_NVRAM=y +# CONFIG_MMIO_NVRAM is not set # CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set diff --git a/trunk/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/trunk/arch/powerpc/configs/86xx/gef_sbc310_defconfig index a6a3768f7304..e199d1cacbaf 100644 --- a/trunk/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/trunk/arch/powerpc/configs/86xx/gef_sbc310_defconfig @@ -218,7 +218,7 @@ CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set # CONFIG_PPC_I8259 is not set # CONFIG_PPC_RTAS is not set -CONFIG_MMIO_NVRAM=y +# CONFIG_MMIO_NVRAM is not set # CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set diff --git a/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 1975d41e0763..3b0fbfb28efd 100644 --- a/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -219,7 +219,7 @@ CONFIG_MPIC=y # CONFIG_MPIC_WEIRD is not set # CONFIG_PPC_I8259 is not set # CONFIG_PPC_RTAS is not set -CONFIG_MMIO_NVRAM=y +# CONFIG_MMIO_NVRAM is not set # CONFIG_PPC_MPC106 is not set # CONFIG_PPC_970_NAP is not set # CONFIG_PPC_INDIRECT_IO is not set @@ -1124,7 +1124,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set -CONFIG_NVRAM=y +# CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set diff --git a/trunk/arch/powerpc/include/asm/cpm.h b/trunk/arch/powerpc/include/asm/cpm.h index 0835eb977ba9..24d79e3abd8e 100644 --- a/trunk/arch/powerpc/include/asm/cpm.h +++ b/trunk/arch/powerpc/include/asm/cpm.h @@ -3,47 +3,8 @@ #include #include -#include #include -/* - * USB Controller pram common to QE and CPM. - */ -struct usb_ctlr { - u8 usb_usmod; - u8 usb_usadr; - u8 usb_uscom; - u8 res1[1]; - __be16 usb_usep[4]; - u8 res2[4]; - __be16 usb_usber; - u8 res3[2]; - __be16 usb_usbmr; - u8 res4[1]; - u8 usb_usbs; - /* Fields down below are QE-only */ - __be16 usb_ussft; - u8 res5[2]; - __be16 usb_usfrn; - u8 res6[0x22]; -} __attribute__ ((packed)); - -/* - * Function code bits, usually generic to devices. - */ -#ifdef CONFIG_CPM1 -#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */ -#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */ -#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */ -#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */ -#else -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ -#endif -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ - /* Opcodes common to CPM1 and CPM2 */ #define CPM_CR_INIT_TRX ((ushort)0x0000) @@ -132,56 +93,13 @@ typedef struct cpm_buf_desc { #define BD_I2C_START (0x0400) int cpm_muram_init(void); - -#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); void __iomem *cpm_muram_addr(unsigned long offset); unsigned long cpm_muram_offset(void __iomem *addr); dma_addr_t cpm_muram_dma(void __iomem *addr); -#else -static inline unsigned long cpm_muram_alloc(unsigned long size, - unsigned long align) -{ - return -ENOSYS; -} - -static inline int cpm_muram_free(unsigned long offset) -{ - return -ENOSYS; -} - -static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset, - unsigned long size) -{ - return -ENOSYS; -} - -static inline void __iomem *cpm_muram_addr(unsigned long offset) -{ - return NULL; -} - -static inline unsigned long cpm_muram_offset(void __iomem *addr) -{ - return -ENOSYS; -} - -static inline dma_addr_t cpm_muram_dma(void __iomem *addr) -{ - return 0; -} -#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ - -#ifdef CONFIG_CPM int cpm_command(u32 command, u8 opcode); -#else -static inline int cpm_command(u32 command, u8 opcode) -{ - return -ENOSYS; -} -#endif /* CONFIG_CPM */ int cpm2_gpiochip_add32(struct device_node *np); diff --git a/trunk/arch/powerpc/include/asm/cpm1.h b/trunk/arch/powerpc/include/asm/cpm1.h index 81b01192f440..7685ffde8821 100644 --- a/trunk/arch/powerpc/include/asm/cpm1.h +++ b/trunk/arch/powerpc/include/asm/cpm1.h @@ -478,6 +478,51 @@ typedef struct iic { char res2[2]; /* Reserved */ } iic_t; +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; + ushort spi_rpbase; /* Relocation pointer */ + ushort spi_res2; +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ +#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ +#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +/* SPIE fields */ +#define SPIE_MME 0x20 +#define SPIE_TXE 0x10 +#define SPIE_BSY 0x04 +#define SPIE_TXB 0x02 +#define SPIE_RXB 0x01 + /* * RISC Controller Configuration Register definitons */ diff --git a/trunk/arch/powerpc/include/asm/cpm2.h b/trunk/arch/powerpc/include/asm/cpm2.h index f42e9baf3a4e..990ff191da8b 100644 --- a/trunk/arch/powerpc/include/asm/cpm2.h +++ b/trunk/arch/powerpc/include/asm/cpm2.h @@ -124,6 +124,14 @@ static inline void cpm2_fastbrg(uint brg, uint rate, int div16) __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT); } +/* Function code bits, usually generic to devices. +*/ +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ + /* Parameter RAM offsets from the base. */ #define PROFF_SCC1 ((uint)0x8000) @@ -646,6 +654,45 @@ typedef struct iic { uint iic_txtmp; /* Internal */ } iic_t; +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; /* Tx temp. */ + uint spi_res1[4]; /* SDMA temp. */ +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +#define SPI_EB ((u_char)0x10) /* big endian byte order */ + /* IDMA parameter RAM */ typedef struct idma { diff --git a/trunk/arch/powerpc/include/asm/exception-64s.h b/trunk/arch/powerpc/include/asm/exception-64s.h index 57c400071995..a98653b26231 100644 --- a/trunk/arch/powerpc/include/asm/exception-64s.h +++ b/trunk/arch/powerpc/include/asm/exception-64s.h @@ -147,7 +147,6 @@ .globl label##_pSeries; \ label##_pSeries: \ HMT_MEDIUM; \ - DO_KVM n; \ mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) @@ -171,7 +170,6 @@ label##_pSeries: \ .globl label##_pSeries; \ label##_pSeries: \ HMT_MEDIUM; \ - DO_KVM n; \ mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \ std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ diff --git a/trunk/arch/powerpc/include/asm/hugetlb.h b/trunk/arch/powerpc/include/asm/hugetlb.h index 5856a66ab404..b1dafb6a9743 100644 --- a/trunk/arch/powerpc/include/asm/hugetlb.h +++ b/trunk/arch/powerpc/include/asm/hugetlb.h @@ -3,10 +3,6 @@ #include -pte_t *huge_pte_offset_and_shift(struct mm_struct *mm, - unsigned long addr, unsigned *shift); - -void flush_dcache_icache_hugepage(struct page *page); int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, unsigned long len); @@ -15,6 +11,12 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, unsigned long end, unsigned long floor, unsigned long ceiling); +void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte); + +pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, + pte_t *ptep); + /* * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs * to override the version in mm/hugetlb.c @@ -40,26 +42,9 @@ static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm) { } - -static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte) -{ - set_pte_at(mm, addr, ptep, pte); -} - -static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, - unsigned long addr, pte_t *ptep) -{ - unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1); - return __pte(old); -} - static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) { - pte_t pte; - pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep); - flush_tlb_page(vma, addr); } static inline int huge_pte_none(pte_t pte) diff --git a/trunk/arch/powerpc/include/asm/hvcall.h b/trunk/arch/powerpc/include/asm/hvcall.h index f0275818b95c..c27caac47ad1 100644 --- a/trunk/arch/powerpc/include/asm/hvcall.h +++ b/trunk/arch/powerpc/include/asm/hvcall.h @@ -212,19 +212,6 @@ #define H_QUERY_INT_STATE 0x1E4 #define H_POLL_PENDING 0x1D8 #define H_ILLAN_ATTRIBUTES 0x244 -#define H_MODIFY_HEA_QP 0x250 -#define H_QUERY_HEA_QP 0x254 -#define H_QUERY_HEA 0x258 -#define H_QUERY_HEA_PORT 0x25C -#define H_MODIFY_HEA_PORT 0x260 -#define H_REG_BCMC 0x264 -#define H_DEREG_BCMC 0x268 -#define H_REGISTER_HEA_RPAGES 0x26C -#define H_DISABLE_AND_GET_HEA 0x270 -#define H_GET_HEA_INFO 0x274 -#define H_ALLOC_HEA_RESOURCE 0x278 -#define H_ADD_CONN 0x284 -#define H_DEL_CONN 0x288 #define H_JOIN 0x298 #define H_VASI_STATE 0x2A4 #define H_ENABLE_CRQ 0x2B0 diff --git a/trunk/arch/powerpc/include/asm/hw_irq.h b/trunk/arch/powerpc/include/asm/hw_irq.h index 9f4c9d4f5803..abbc2aaaced5 100644 --- a/trunk/arch/powerpc/include/asm/hw_irq.h +++ b/trunk/arch/powerpc/include/asm/hw_irq.h @@ -64,6 +64,11 @@ extern void iseries_handle_interrupts(void); get_paca()->hard_enabled = 0; \ } while(0) +static inline int irqs_disabled_flags(unsigned long flags) +{ + return flags == 0; +} + #else #if defined(CONFIG_BOOKE) diff --git a/trunk/arch/powerpc/include/asm/immap_cpm2.h b/trunk/arch/powerpc/include/asm/immap_cpm2.h index 7c64fda5357b..d4f069bf0e57 100644 --- a/trunk/arch/powerpc/include/asm/immap_cpm2.h +++ b/trunk/arch/powerpc/include/asm/immap_cpm2.h @@ -549,7 +549,7 @@ typedef struct comm_proc { /* USB Controller. */ -typedef struct cpm_usb_ctlr { +typedef struct usb_ctlr { u8 usb_usmod; u8 usb_usadr; u8 usb_uscom; diff --git a/trunk/arch/powerpc/include/asm/immap_qe.h b/trunk/arch/powerpc/include/asm/immap_qe.h index 4e10f508570a..c346d0bcd230 100644 --- a/trunk/arch/powerpc/include/asm/immap_qe.h +++ b/trunk/arch/powerpc/include/asm/immap_qe.h @@ -210,7 +210,7 @@ struct sir { } __attribute__ ((packed)); /* USB Controller */ -struct qe_usb_ctlr { +struct usb_ctlr { u8 usb_usmod; u8 usb_usadr; u8 usb_uscom; @@ -229,7 +229,7 @@ struct qe_usb_ctlr { } __attribute__ ((packed)); /* MCC */ -struct qe_mcc { +struct mcc { __be32 mcce; /* MCC event register */ __be32 mccm; /* MCC mask register */ __be32 mccf; /* MCC configuration register */ @@ -431,9 +431,9 @@ struct qe_immap { struct qe_mux qmx; /* QE Multiplexer */ struct qe_timers qet; /* QE Timers */ struct spi spi[0x2]; /* spi */ - struct qe_mcc mcc; /* mcc */ + struct mcc mcc; /* mcc */ struct qe_brg brg; /* brg */ - struct qe_usb_ctlr usb; /* USB */ + struct usb_ctlr usb; /* USB */ struct si1 si1; /* SI */ u8 res11[0x800]; struct sir sir; /* SI Routing Tables */ diff --git a/trunk/arch/powerpc/include/asm/irq.h b/trunk/arch/powerpc/include/asm/irq.h index e054baef1845..bbcd1aaf3dfd 100644 --- a/trunk/arch/powerpc/include/asm/irq.h +++ b/trunk/arch/powerpc/include/asm/irq.h @@ -17,6 +17,8 @@ #include +#define get_irq_desc(irq) (&irq_desc[(irq)]) + /* Define a way to iterate across irqs. */ #define for_each_irq(i) \ for ((i) = 0; (i) < NR_IRQS; ++(i)) @@ -32,15 +34,12 @@ extern atomic_t ppc_n_lost_interrupts; */ #define NO_IRQ_IGNORE ((unsigned int)-1) -/* Total number of virq in the platform */ -#define NR_IRQS CONFIG_NR_IRQS +/* Total number of virq in the platform (make it a CONFIG_* option ? */ +#define NR_IRQS 512 /* Number of irqs reserved for the legacy controller */ #define NUM_ISA_INTERRUPTS 16 -/* Same thing, used by the generic IRQ code */ -#define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS - /* This type is the placeholder for a hardware interrupt number. It has to * be big enough to enclose whatever representation is used by a given * platform. @@ -100,7 +99,7 @@ struct irq_host_ops { * interrupt controller has for that line) */ int (*xlate)(struct irq_host *h, struct device_node *ctrler, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type); }; @@ -314,7 +313,7 @@ extern void irq_free_virt(unsigned int virq, unsigned int count); * of the of_irq_map_*() functions. */ extern unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize); + u32 *intspec, unsigned int intsize); /** * irq_of_parse_and_map - Parse and Map an interrupt into linux virq space diff --git a/trunk/arch/powerpc/include/asm/kvm.h b/trunk/arch/powerpc/include/asm/kvm.h index 81f3b0b5601e..bb2de6aa5ce0 100644 --- a/trunk/arch/powerpc/include/asm/kvm.h +++ b/trunk/arch/powerpc/include/asm/kvm.h @@ -46,24 +46,6 @@ struct kvm_regs { }; struct kvm_sregs { - __u32 pvr; - union { - struct { - __u64 sdr1; - struct { - struct { - __u64 slbe; - __u64 slbv; - } slb[64]; - } ppc64; - struct { - __u32 sr[16]; - __u64 ibat[8]; - __u64 dbat[8]; - } ppc32; - } s; - __u8 pad[1020]; - } u; }; struct kvm_fpu { diff --git a/trunk/arch/powerpc/include/asm/kvm_asm.h b/trunk/arch/powerpc/include/asm/kvm_asm.h index af2abe74f544..56bfae59837f 100644 --- a/trunk/arch/powerpc/include/asm/kvm_asm.h +++ b/trunk/arch/powerpc/include/asm/kvm_asm.h @@ -49,46 +49,6 @@ #define BOOKE_INTERRUPT_SPE_FP_ROUND 34 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35 -/* book3s */ - -#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 -#define BOOK3S_INTERRUPT_MACHINE_CHECK 0x200 -#define BOOK3S_INTERRUPT_DATA_STORAGE 0x300 -#define BOOK3S_INTERRUPT_DATA_SEGMENT 0x380 -#define BOOK3S_INTERRUPT_INST_STORAGE 0x400 -#define BOOK3S_INTERRUPT_INST_SEGMENT 0x480 -#define BOOK3S_INTERRUPT_EXTERNAL 0x500 -#define BOOK3S_INTERRUPT_ALIGNMENT 0x600 -#define BOOK3S_INTERRUPT_PROGRAM 0x700 -#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800 -#define BOOK3S_INTERRUPT_DECREMENTER 0x900 -#define BOOK3S_INTERRUPT_SYSCALL 0xc00 -#define BOOK3S_INTERRUPT_TRACE 0xd00 -#define BOOK3S_INTERRUPT_PERFMON 0xf00 -#define BOOK3S_INTERRUPT_ALTIVEC 0xf20 -#define BOOK3S_INTERRUPT_VSX 0xf40 - -#define BOOK3S_IRQPRIO_SYSTEM_RESET 0 -#define BOOK3S_IRQPRIO_DATA_SEGMENT 1 -#define BOOK3S_IRQPRIO_INST_SEGMENT 2 -#define BOOK3S_IRQPRIO_DATA_STORAGE 3 -#define BOOK3S_IRQPRIO_INST_STORAGE 4 -#define BOOK3S_IRQPRIO_ALIGNMENT 5 -#define BOOK3S_IRQPRIO_PROGRAM 6 -#define BOOK3S_IRQPRIO_FP_UNAVAIL 7 -#define BOOK3S_IRQPRIO_ALTIVEC 8 -#define BOOK3S_IRQPRIO_VSX 9 -#define BOOK3S_IRQPRIO_SYSCALL 10 -#define BOOK3S_IRQPRIO_MACHINE_CHECK 11 -#define BOOK3S_IRQPRIO_DEBUG 12 -#define BOOK3S_IRQPRIO_EXTERNAL 13 -#define BOOK3S_IRQPRIO_DECREMENTER 14 -#define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR 15 -#define BOOK3S_IRQPRIO_MAX 16 - -#define BOOK3S_HFLAG_DCBZ32 0x1 -#define BOOK3S_HFLAG_SLB 0x2 - #define RESUME_FLAG_NV (1<<0) /* Reload guest nonvolatile state? */ #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ diff --git a/trunk/arch/powerpc/include/asm/kvm_book3s.h b/trunk/arch/powerpc/include/asm/kvm_book3s.h deleted file mode 100644 index 74b7369770d0..000000000000 --- a/trunk/arch/powerpc/include/asm/kvm_book3s.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#ifndef __ASM_KVM_BOOK3S_H__ -#define __ASM_KVM_BOOK3S_H__ - -#include -#include -#include - -struct kvmppc_slb { - u64 esid; - u64 vsid; - u64 orige; - u64 origv; - bool valid; - bool Ks; - bool Kp; - bool nx; - bool large; - bool class; -}; - -struct kvmppc_sr { - u32 raw; - u32 vsid; - bool Ks; - bool Kp; - bool nx; -}; - -struct kvmppc_bat { - u64 raw; - u32 bepi; - u32 bepi_mask; - bool vs; - bool vp; - u32 brpn; - u8 wimg; - u8 pp; -}; - -struct kvmppc_sid_map { - u64 guest_vsid; - u64 guest_esid; - u64 host_vsid; - bool valid; -}; - -#define SID_MAP_BITS 9 -#define SID_MAP_NUM (1 << SID_MAP_BITS) -#define SID_MAP_MASK (SID_MAP_NUM - 1) - -struct kvmppc_vcpu_book3s { - struct kvm_vcpu vcpu; - struct kvmppc_sid_map sid_map[SID_MAP_NUM]; - struct kvmppc_slb slb[64]; - struct { - u64 esid; - u64 vsid; - } slb_shadow[64]; - u8 slb_shadow_max; - struct kvmppc_sr sr[16]; - struct kvmppc_bat ibat[8]; - struct kvmppc_bat dbat[8]; - u64 hid[6]; - int slb_nr; - u64 sdr1; - u64 dsisr; - u64 hior; - u64 msr_mask; - u64 vsid_first; - u64 vsid_next; - u64 vsid_max; - int context_id; -}; - -#define CONTEXT_HOST 0 -#define CONTEXT_GUEST 1 -#define CONTEXT_GUEST_END 2 - -#define VSID_REAL 0xfffffffffff00000 -#define VSID_REAL_DR 0xffffffffffe00000 -#define VSID_REAL_IR 0xffffffffffd00000 -#define VSID_BAT 0xffffffffffc00000 -#define VSID_PR 0x8000000000000000 - -extern void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 ea, u64 ea_mask); -extern void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 vp, u64 vp_mask); -extern void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end); -extern void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 new_msr); -extern void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu); -extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu); -extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte); -extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr); -extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu); -extern struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data); -extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr, bool data); -extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr); -extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec); -extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, - bool upper, u32 val); - -extern u32 kvmppc_trampoline_lowmem; -extern u32 kvmppc_trampoline_enter; - -static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu) -{ - return container_of(vcpu, struct kvmppc_vcpu_book3s, vcpu); -} - -static inline ulong dsisr(void) -{ - ulong r; - asm ( "mfdsisr %0 " : "=r" (r) ); - return r; -} - -extern void kvm_return_point(void); - -#define INS_DCBZ 0x7c0007ec - -#endif /* __ASM_KVM_BOOK3S_H__ */ diff --git a/trunk/arch/powerpc/include/asm/kvm_book3s_64_asm.h b/trunk/arch/powerpc/include/asm/kvm_book3s_64_asm.h deleted file mode 100644 index 2e06ee8184ef..000000000000 --- a/trunk/arch/powerpc/include/asm/kvm_book3s_64_asm.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#ifndef __ASM_KVM_BOOK3S_ASM_H__ -#define __ASM_KVM_BOOK3S_ASM_H__ - -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER - -#include - -.macro DO_KVM intno - .if (\intno == BOOK3S_INTERRUPT_SYSTEM_RESET) || \ - (\intno == BOOK3S_INTERRUPT_MACHINE_CHECK) || \ - (\intno == BOOK3S_INTERRUPT_DATA_STORAGE) || \ - (\intno == BOOK3S_INTERRUPT_INST_STORAGE) || \ - (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \ - (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \ - (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \ - (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \ - (\intno == BOOK3S_INTERRUPT_PROGRAM) || \ - (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \ - (\intno == BOOK3S_INTERRUPT_DECREMENTER) || \ - (\intno == BOOK3S_INTERRUPT_SYSCALL) || \ - (\intno == BOOK3S_INTERRUPT_TRACE) || \ - (\intno == BOOK3S_INTERRUPT_PERFMON) || \ - (\intno == BOOK3S_INTERRUPT_ALTIVEC) || \ - (\intno == BOOK3S_INTERRUPT_VSX) - - b kvmppc_trampoline_\intno -kvmppc_resume_\intno: - - .endif -.endm - -#else - -.macro DO_KVM intno -.endm - -#endif /* CONFIG_KVM_BOOK3S_64_HANDLER */ - -#endif /* __ASM_KVM_BOOK3S_ASM_H__ */ diff --git a/trunk/arch/powerpc/include/asm/kvm_host.h b/trunk/arch/powerpc/include/asm/kvm_host.h index 1201f62d0d73..c9c930ed11d7 100644 --- a/trunk/arch/powerpc/include/asm/kvm_host.h +++ b/trunk/arch/powerpc/include/asm/kvm_host.h @@ -21,8 +21,7 @@ #define __POWERPC_KVM_HOST_H__ #include -#include -#include +#include #include #include #include @@ -38,8 +37,6 @@ #define KVM_NR_PAGE_SIZES 1 #define KVM_PAGES_PER_HPAGE(x) (1UL<<31) -#define HPTEG_CACHE_NUM 1024 - struct kvm; struct kvm_run; struct kvm_vcpu; @@ -66,17 +63,6 @@ struct kvm_vcpu_stat { u32 dec_exits; u32 ext_intr_exits; u32 halt_wakeup; -#ifdef CONFIG_PPC64 - u32 pf_storage; - u32 pf_instruc; - u32 sp_storage; - u32 sp_instruc; - u32 queue_intr; - u32 ld; - u32 ld_slow; - u32 st; - u32 st_slow; -#endif }; enum kvm_exit_types { @@ -123,53 +109,9 @@ struct kvmppc_exit_timing { struct kvm_arch { }; -struct kvmppc_pte { - u64 eaddr; - u64 vpage; - u64 raddr; - bool may_read; - bool may_write; - bool may_execute; -}; - -struct kvmppc_mmu { - /* book3s_64 only */ - void (*slbmte)(struct kvm_vcpu *vcpu, u64 rb, u64 rs); - u64 (*slbmfee)(struct kvm_vcpu *vcpu, u64 slb_nr); - u64 (*slbmfev)(struct kvm_vcpu *vcpu, u64 slb_nr); - void (*slbie)(struct kvm_vcpu *vcpu, u64 slb_nr); - void (*slbia)(struct kvm_vcpu *vcpu); - /* book3s */ - void (*mtsrin)(struct kvm_vcpu *vcpu, u32 srnum, ulong value); - u32 (*mfsrin)(struct kvm_vcpu *vcpu, u32 srnum); - int (*xlate)(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data); - void (*reset_msr)(struct kvm_vcpu *vcpu); - void (*tlbie)(struct kvm_vcpu *vcpu, ulong addr, bool large); - int (*esid_to_vsid)(struct kvm_vcpu *vcpu, u64 esid, u64 *vsid); - u64 (*ea_to_vp)(struct kvm_vcpu *vcpu, gva_t eaddr, bool data); - bool (*is_dcbz32)(struct kvm_vcpu *vcpu); -}; - -struct hpte_cache { - u64 host_va; - u64 pfn; - ulong slot; - struct kvmppc_pte pte; -}; - struct kvm_vcpu_arch { - ulong host_stack; + u32 host_stack; u32 host_pid; -#ifdef CONFIG_PPC64 - ulong host_msr; - ulong host_r2; - void *host_retip; - ulong trampoline_lowmem; - ulong trampoline_enter; - ulong highmem_handler; - ulong host_paca_phys; - struct kvmppc_mmu mmu; -#endif u64 fpr[32]; ulong gpr[32]; @@ -181,10 +123,6 @@ struct kvm_vcpu_arch { ulong xer; ulong msr; -#ifdef CONFIG_PPC64 - ulong shadow_msr; - ulong hflags; -#endif u32 mmucr; ulong sprg0; ulong sprg1; @@ -211,7 +149,6 @@ struct kvm_vcpu_arch { u32 ivor[64]; ulong ivpr; u32 pir; - u32 pvr; u32 shadow_pid; u32 pid; @@ -237,9 +174,6 @@ struct kvm_vcpu_arch { #endif u32 last_inst; -#ifdef CONFIG_PPC64 - ulong fault_dsisr; -#endif ulong fault_dear; ulong fault_esr; gpa_t paddr_accessed; @@ -251,15 +185,8 @@ struct kvm_vcpu_arch { u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */ - struct hrtimer dec_timer; - struct tasklet_struct tasklet; - u64 dec_jiffies; + struct timer_list dec_timer; unsigned long pending_exceptions; - -#ifdef CONFIG_PPC64 - struct hpte_cache hpte_cache[HPTEG_CACHE_NUM]; - int hpte_cache_offset; -#endif }; #endif /* __POWERPC_KVM_HOST_H__ */ diff --git a/trunk/arch/powerpc/include/asm/kvm_ppc.h b/trunk/arch/powerpc/include/asm/kvm_ppc.h index 269ee46ab028..2c6ee349df5e 100644 --- a/trunk/arch/powerpc/include/asm/kvm_ppc.h +++ b/trunk/arch/powerpc/include/asm/kvm_ppc.h @@ -39,7 +39,6 @@ enum emulation_result { extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu); extern char kvmppc_handlers_start[]; extern unsigned long kvmppc_handler_len; -extern void kvmppc_handler_highmem(void); extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu); extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, diff --git a/trunk/arch/powerpc/include/asm/lppaca.h b/trunk/arch/powerpc/include/asm/lppaca.h index 14b592dfb4e8..f78f65c38f05 100644 --- a/trunk/arch/powerpc/include/asm/lppaca.h +++ b/trunk/arch/powerpc/include/asm/lppaca.h @@ -100,14 +100,7 @@ struct lppaca { // Used to pass parms from the OS to PLIC for SetAsrAndRfid u64 saved_gpr3; // Saved GPR3 x20-x27 u64 saved_gpr4; // Saved GPR4 x28-x2F - union { - u64 saved_gpr5; /* Saved GPR5 x30-x37 */ - struct { - u8 cede_latency_hint; /* x30 */ - u8 reserved[7]; /* x31-x36 */ - } fields; - } gpr5_dword; - + u64 saved_gpr5; // Saved GPR5 x30-x37 u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 diff --git a/trunk/arch/powerpc/include/asm/machdep.h b/trunk/arch/powerpc/include/asm/machdep.h index 9f0fc9e6ce0d..9efa2be78331 100644 --- a/trunk/arch/powerpc/include/asm/machdep.h +++ b/trunk/arch/powerpc/include/asm/machdep.h @@ -266,11 +266,6 @@ struct machdep_calls { void (*suspend_disable_irqs)(void); void (*suspend_enable_irqs)(void); #endif - -#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE - ssize_t (*cpu_probe)(const char *, size_t); - ssize_t (*cpu_release)(const char *, size_t); -#endif }; extern void e500_idle(void); diff --git a/trunk/arch/powerpc/include/asm/macio.h b/trunk/arch/powerpc/include/asm/macio.h index a062c57696d0..079c06eae446 100644 --- a/trunk/arch/powerpc/include/asm/macio.h +++ b/trunk/arch/powerpc/include/asm/macio.h @@ -39,7 +39,6 @@ struct macio_dev struct macio_bus *bus; /* macio bus this device is on */ struct macio_dev *media_bay; /* Device is part of a media bay */ struct of_device ofdev; - struct device_dma_parameters dma_parms; /* ide needs that */ int n_resources; struct resource resource[MACIO_DEV_COUNT_RESOURCES]; int n_interrupts; @@ -79,8 +78,6 @@ static inline unsigned long macio_resource_len(struct macio_dev *dev, int resour return res->end - res->start + 1; } -extern int macio_enable_devres(struct macio_dev *dev); - extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name); extern void macio_release_resource(struct macio_dev *dev, int resource_no); extern int macio_request_resources(struct macio_dev *dev, const char *name); @@ -134,9 +131,6 @@ struct macio_driver int (*resume)(struct macio_dev* dev); int (*shutdown)(struct macio_dev* dev); -#ifdef CONFIG_PMAC_MEDIABAY - void (*mediabay_event)(struct macio_dev* dev, int mb_state); -#endif struct device_driver driver; }; #define to_macio_driver(drv) container_of(drv,struct macio_driver, driver) diff --git a/trunk/arch/powerpc/include/asm/mediabay.h b/trunk/arch/powerpc/include/asm/mediabay.h index 11037a4133ee..b2efb3325808 100644 --- a/trunk/arch/powerpc/include/asm/mediabay.h +++ b/trunk/arch/powerpc/include/asm/mediabay.h @@ -17,31 +17,26 @@ #define MB_POWER 6 /* media bay contains a Power device (???) */ #define MB_NO 7 /* media bay contains nothing */ -struct macio_dev; +/* Number of bays in the machine or 0 */ +extern int media_bay_count; -#ifdef CONFIG_PMAC_MEDIABAY +#ifdef CONFIG_BLK_DEV_IDE_PMAC +#include -/* Check the content type of the bay, returns MB_NO if the bay is still - * transitionning - */ -extern int check_media_bay(struct macio_dev *bay); +int check_media_bay_by_base(unsigned long base, int what); +/* called by IDE PMAC host driver to register IDE controller for media bay */ +int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base, + int irq, ide_hwif_t *hwif); -/* The ATA driver uses the calls below to temporarily hold on the - * media bay callbacks while initializing the interface - */ -extern void lock_media_bay(struct macio_dev *bay); -extern void unlock_media_bay(struct macio_dev *bay); +int check_media_bay(struct device_node *which_bay, int what); #else -static inline int check_media_bay(struct macio_dev *bay) +static inline int check_media_bay(struct device_node *which_bay, int what) { - return MB_NO; + return -ENODEV; } -static inline void lock_media_bay(struct macio_dev *bay) { } -static inline void unlock_media_bay(struct macio_dev *bay) { } - #endif #endif /* __KERNEL__ */ diff --git a/trunk/arch/powerpc/include/asm/mmu-hash64.h b/trunk/arch/powerpc/include/asm/mmu-hash64.h index 2102b214a87c..bebe31c2e907 100644 --- a/trunk/arch/powerpc/include/asm/mmu-hash64.h +++ b/trunk/arch/powerpc/include/asm/mmu-hash64.h @@ -173,6 +173,14 @@ extern unsigned long tce_alloc_start, tce_alloc_end; */ extern int mmu_ci_restrictions; +#ifdef CONFIG_HUGETLB_PAGE +/* + * The page size indexes of the huge pages for use by hugetlbfs + */ +extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT]; + +#endif /* CONFIG_HUGETLB_PAGE */ + /* * This function sets the AVPN and L fields of the HPTE appropriately * for the page size @@ -245,11 +253,10 @@ extern int __hash_page_64K(unsigned long ea, unsigned long access, unsigned long vsid, pte_t *ptep, unsigned long trap, unsigned int local, int ssize); struct mm_struct; -unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); -int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, - pte_t *ptep, unsigned long trap, int local, int ssize, - unsigned int shift, unsigned int mmu_psize); +extern int hash_huge_page(struct mm_struct *mm, unsigned long access, + unsigned long ea, unsigned long vsid, int local, + unsigned long trap); extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, unsigned long pstart, unsigned long prot, @@ -373,38 +380,6 @@ extern void slb_set_size(u16 size); #ifndef __ASSEMBLY__ -#ifdef CONFIG_PPC_SUBPAGE_PROT -/* - * For the sub-page protection option, we extend the PGD with one of - * these. Basically we have a 3-level tree, with the top level being - * the protptrs array. To optimize speed and memory consumption when - * only addresses < 4GB are being protected, pointers to the first - * four pages of sub-page protection words are stored in the low_prot - * array. - * Each page of sub-page protection words protects 1GB (4 bytes - * protects 64k). For the 3-level tree, each page of pointers then - * protects 8TB. - */ -struct subpage_prot_table { - unsigned long maxaddr; /* only addresses < this are protected */ - unsigned int **protptrs[2]; - unsigned int *low_prot[4]; -}; - -#define SBP_L1_BITS (PAGE_SHIFT - 2) -#define SBP_L2_BITS (PAGE_SHIFT - 3) -#define SBP_L1_COUNT (1 << SBP_L1_BITS) -#define SBP_L2_COUNT (1 << SBP_L2_BITS) -#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) -#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) - -extern void subpage_prot_free(struct mm_struct *mm); -extern void subpage_prot_init_new_context(struct mm_struct *mm); -#else -static inline void subpage_prot_free(struct mm_struct *mm) {} -static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } -#endif /* CONFIG_PPC_SUBPAGE_PROT */ - typedef unsigned long mm_context_id_t; typedef struct { @@ -418,9 +393,6 @@ typedef struct { u16 sllp; /* SLB page size encoding */ #endif unsigned long vdso_base; -#ifdef CONFIG_PPC_SUBPAGE_PROT - struct subpage_prot_table spt; -#endif /* CONFIG_PPC_SUBPAGE_PROT */ } mm_context_t; diff --git a/trunk/arch/powerpc/include/asm/mmu_context.h b/trunk/arch/powerpc/include/asm/mmu_context.h index 26383e0778aa..b34e94d94435 100644 --- a/trunk/arch/powerpc/include/asm/mmu_context.h +++ b/trunk/arch/powerpc/include/asm/mmu_context.h @@ -23,8 +23,6 @@ extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm); extern void set_context(unsigned long id, pgd_t *pgd); #ifdef CONFIG_PPC_BOOK3S_64 -extern int __init_new_context(void); -extern void __destroy_context(int context_id); static inline void mmu_context_init(void) { } #else extern void mmu_context_init(void); diff --git a/trunk/arch/powerpc/include/asm/mpc52xx.h b/trunk/arch/powerpc/include/asm/mpc52xx.h index b664ce79a172..1b4f697abbdd 100644 --- a/trunk/arch/powerpc/include/asm/mpc52xx.h +++ b/trunk/arch/powerpc/include/asm/mpc52xx.h @@ -276,53 +276,6 @@ extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv); extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node); extern void mpc52xx_restart(char *cmd); -/* mpc52xx_gpt.c */ -struct mpc52xx_gpt_priv; -extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq); -extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period, - int continuous); -extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt); -extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt); - -/* mpc52xx_lpbfifo.c */ -#define MPC52XX_LPBFIFO_FLAG_READ (0) -#define MPC52XX_LPBFIFO_FLAG_WRITE (1<<0) -#define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT (1<<1) -#define MPC52XX_LPBFIFO_FLAG_NO_DMA (1<<2) -#define MPC52XX_LPBFIFO_FLAG_POLL_DMA (1<<3) - -struct mpc52xx_lpbfifo_request { - struct list_head list; - - /* localplus bus address */ - unsigned int cs; - size_t offset; - - /* Memory address */ - void *data; - phys_addr_t data_phys; - - /* Details of transfer */ - size_t size; - size_t pos; /* current position of transfer */ - int flags; - - /* What to do when finished */ - void (*callback)(struct mpc52xx_lpbfifo_request *); - - void *priv; /* Driver private data */ - - /* statistics */ - int irq_count; - int irq_ticks; - u8 last_byte; - int buffer_not_done_cnt; -}; - -extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req); -extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req); -extern void mpc52xx_lpbfifo_poll(void); - /* mpc52xx_pic.c */ extern void mpc52xx_init_irq(void); extern unsigned int mpc52xx_get_irq(void); diff --git a/trunk/arch/powerpc/include/asm/nvram.h b/trunk/arch/powerpc/include/asm/nvram.h index 850b72f27445..6c587eddee59 100644 --- a/trunk/arch/powerpc/include/asm/nvram.h +++ b/trunk/arch/powerpc/include/asm/nvram.h @@ -73,6 +73,7 @@ extern int nvram_write_error_log(char * buff, int length, extern int nvram_read_error_log(char * buff, int length, unsigned int * err_type, unsigned int *err_seq); extern int nvram_clear_error_log(void); +extern struct nvram_partition *nvram_find_partition(int sig, const char *name); extern int pSeries_nvram_init(void); diff --git a/trunk/arch/powerpc/include/asm/pSeries_reconfig.h b/trunk/arch/powerpc/include/asm/pSeries_reconfig.h index d4b4bfa26fb3..e482e5352e69 100644 --- a/trunk/arch/powerpc/include/asm/pSeries_reconfig.h +++ b/trunk/arch/powerpc/include/asm/pSeries_reconfig.h @@ -17,7 +17,6 @@ #ifdef CONFIG_PPC_PSERIES extern int pSeries_reconfig_notifier_register(struct notifier_block *); extern void pSeries_reconfig_notifier_unregister(struct notifier_block *); -extern struct blocking_notifier_head pSeries_reconfig_chain; #else /* !CONFIG_PPC_PSERIES */ static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb) { diff --git a/trunk/arch/powerpc/include/asm/paca.h b/trunk/arch/powerpc/include/asm/paca.h index 5e9b4ef71415..7d8514ceceae 100644 --- a/trunk/arch/powerpc/include/asm/paca.h +++ b/trunk/arch/powerpc/include/asm/paca.h @@ -129,15 +129,6 @@ struct paca_struct { u64 system_time; /* accumulated system TB ticks */ u64 startpurr; /* PURR/TB value snapshot */ u64 startspurr; /* SPURR value snapshot */ - -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER - struct { - u64 esid; - u64 vsid; - } kvm_slb[64]; /* guest SLB */ - u8 kvm_slb_max; /* highest used guest slb entry */ - u8 kvm_in_guest; /* are we inside the guest? */ -#endif }; extern struct paca_struct paca[]; diff --git a/trunk/arch/powerpc/include/asm/page.h b/trunk/arch/powerpc/include/asm/page.h index e96d52a516ba..ff24254990e1 100644 --- a/trunk/arch/powerpc/include/asm/page.h +++ b/trunk/arch/powerpc/include/asm/page.h @@ -229,20 +229,6 @@ typedef unsigned long pgprot_t; #endif -typedef struct { signed long pd; } hugepd_t; -#define HUGEPD_SHIFT_MASK 0x3f - -#ifdef CONFIG_HUGETLB_PAGE -static inline int hugepd_ok(hugepd_t hpd) -{ - return (hpd.pd > 0); -} - -#define is_hugepd(pdep) (hugepd_ok(*((hugepd_t *)(pdep)))) -#else /* CONFIG_HUGETLB_PAGE */ -#define is_hugepd(pdep) 0 -#endif /* CONFIG_HUGETLB_PAGE */ - struct page; extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); extern void copy_user_page(void *to, void *from, unsigned long vaddr, diff --git a/trunk/arch/powerpc/include/asm/page_64.h b/trunk/arch/powerpc/include/asm/page_64.h index bfc4e027e2ad..3f17b83f55a1 100644 --- a/trunk/arch/powerpc/include/asm/page_64.h +++ b/trunk/arch/powerpc/include/asm/page_64.h @@ -90,7 +90,7 @@ extern unsigned int HPAGE_SHIFT; #define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) #define HPAGE_MASK (~(HPAGE_SIZE - 1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) -#define HUGE_MAX_HSTATE (MMU_PAGE_COUNT-1) +#define HUGE_MAX_HSTATE 3 #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/powerpc/include/asm/pgalloc-32.h b/trunk/arch/powerpc/include/asm/pgalloc-32.h index 580cf73b96e8..c9500d666a1d 100644 --- a/trunk/arch/powerpc/include/asm/pgalloc-32.h +++ b/trunk/arch/powerpc/include/asm/pgalloc-32.h @@ -3,8 +3,7 @@ #include -/* For 32-bit, all levels of page tables are just drawn from get_free_page() */ -#define MAX_PGTABLE_INDEX_SIZE 0 +#define PTE_NONCACHE_NUM 0 /* dummy for now to share code w/ppc64 */ extern void __bad_pte(pmd_t *pmd); @@ -37,10 +36,11 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); -static inline void pgtable_free(void *table, unsigned index_size) +static inline void pgtable_free(pgtable_free_t pgf) { - BUG_ON(index_size); /* 32-bit doesn't use this */ - free_page((unsigned long)table); + void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK); + + free_page((unsigned long)p); } #define check_pgt_cache() do { } while (0) diff --git a/trunk/arch/powerpc/include/asm/pgalloc-64.h b/trunk/arch/powerpc/include/asm/pgalloc-64.h index 605f5c5398d1..e6f069c4f713 100644 --- a/trunk/arch/powerpc/include/asm/pgalloc-64.h +++ b/trunk/arch/powerpc/include/asm/pgalloc-64.h @@ -11,34 +11,27 @@ #include #include -/* - * Functions that deal with pagetables that could be at any level of - * the table need to be passed an "index_size" so they know how to - * handle allocation. For PTE pages (which are linked to a struct - * page for now, and drawn from the main get_free_pages() pool), the - * allocation size will be (2^index_size * sizeof(pointer)) and - * allocations are drawn from the kmem_cache in PGT_CACHE(index_size). - * - * The maximum index size needs to be big enough to allow any - * pagetable sizes we need, but small enough to fit in the low bits of - * any page table pointer. In other words all pagetables, even tiny - * ones, must be aligned to allow at least enough low 0 bits to - * contain this value. This value is also used as a mask, so it must - * be one less than a power of two. - */ -#define MAX_PGTABLE_INDEX_SIZE 0xf +#ifndef CONFIG_PPC_SUBPAGE_PROT +static inline void subpage_prot_free(pgd_t *pgd) {} +#endif extern struct kmem_cache *pgtable_cache[]; -#define PGT_CACHE(shift) (pgtable_cache[(shift)-1]) + +#define PGD_CACHE_NUM 0 +#define PUD_CACHE_NUM 1 +#define PMD_CACHE_NUM 1 +#define HUGEPTE_CACHE_NUM 2 +#define PTE_NONCACHE_NUM 7 /* from GFP rather than kmem_cache */ static inline pgd_t *pgd_alloc(struct mm_struct *mm) { - return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE), GFP_KERNEL); + return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL); } static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) { - kmem_cache_free(PGT_CACHE(PGD_INDEX_SIZE), pgd); + subpage_prot_free(pgd); + kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd); } #ifndef CONFIG_PPC_64K_PAGES @@ -47,13 +40,13 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr) { - return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE), + return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM], GFP_KERNEL|__GFP_REPEAT); } static inline void pud_free(struct mm_struct *mm, pud_t *pud) { - kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud); + kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud); } static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) @@ -85,13 +78,13 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) { - return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE), + return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM], GFP_KERNEL|__GFP_REPEAT); } static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) { - kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd); + kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd); } static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, @@ -114,22 +107,24 @@ static inline pgtable_t pte_alloc_one(struct mm_struct *mm, return page; } -static inline void pgtable_free(void *table, unsigned index_size) +static inline void pgtable_free(pgtable_free_t pgf) { - if (!index_size) - free_page((unsigned long)table); - else { - BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE); - kmem_cache_free(PGT_CACHE(index_size), table); - } + void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK); + int cachenum = pgf.val & PGF_CACHENUM_MASK; + + if (cachenum == PTE_NONCACHE_NUM) + free_page((unsigned long)p); + else + kmem_cache_free(pgtable_cache[cachenum], p); } -#define __pmd_free_tlb(tlb, pmd, addr) \ - pgtable_free_tlb(tlb, pmd, PMD_INDEX_SIZE) +#define __pmd_free_tlb(tlb, pmd,addr) \ + pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \ + PMD_CACHE_NUM, PMD_TABLE_SIZE-1)) #ifndef CONFIG_PPC_64K_PAGES #define __pud_free_tlb(tlb, pud, addr) \ - pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE) - + pgtable_free_tlb(tlb, pgtable_free_cache(pud, \ + PUD_CACHE_NUM, PUD_TABLE_SIZE-1)) #endif /* CONFIG_PPC_64K_PAGES */ #define check_pgt_cache() do { } while (0) diff --git a/trunk/arch/powerpc/include/asm/pgalloc.h b/trunk/arch/powerpc/include/asm/pgalloc.h index abe8532bd14e..f2e812de7c3c 100644 --- a/trunk/arch/powerpc/include/asm/pgalloc.h +++ b/trunk/arch/powerpc/include/asm/pgalloc.h @@ -24,6 +24,25 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) __free_page(ptepage); } +typedef struct pgtable_free { + unsigned long val; +} pgtable_free_t; + +/* This needs to be big enough to allow for MMU_PAGE_COUNT + 2 to be stored + * and small enough to fit in the low bits of any naturally aligned page + * table cache entry. Arbitrarily set to 0x1f, that should give us some + * room to grow + */ +#define PGF_CACHENUM_MASK 0x1f + +static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum, + unsigned long mask) +{ + BUG_ON(cachenum > PGF_CACHENUM_MASK); + + return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum}; +} + #ifdef CONFIG_PPC64 #include #else @@ -31,12 +50,12 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) #endif #ifdef CONFIG_SMP -extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift); +extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf); extern void pte_free_finish(void); #else /* CONFIG_SMP */ -static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift) +static inline void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf) { - pgtable_free(table, shift); + pgtable_free(pgf); } static inline void pte_free_finish(void) { } #endif /* !CONFIG_SMP */ @@ -44,9 +63,12 @@ static inline void pte_free_finish(void) { } static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage, unsigned long address) { + pgtable_free_t pgf = pgtable_free_cache(page_address(ptepage), + PTE_NONCACHE_NUM, + PTE_TABLE_SIZE-1); tlb_flush_pgtable(tlb, address); pgtable_page_dtor(ptepage); - pgtable_free_tlb(tlb, page_address(ptepage), 0); + pgtable_free_tlb(tlb, pgf); } #endif /* __KERNEL__ */ diff --git a/trunk/arch/powerpc/include/asm/pgtable-ppc64.h b/trunk/arch/powerpc/include/asm/pgtable-ppc64.h index 49865045d56f..806abe7a3fa5 100644 --- a/trunk/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/trunk/arch/powerpc/include/asm/pgtable-ppc64.h @@ -354,7 +354,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE}) #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT) -void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); void pgtable_cache_init(void); /* @@ -379,18 +378,7 @@ void pgtable_cache_init(void); return pt; } -#ifdef CONFIG_HUGETLB_PAGE -pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, - unsigned *shift); -#else -static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, - unsigned *shift) -{ - if (shift) - *shift = 0; - return find_linux_pte(pgdir, ea); -} -#endif /* !CONFIG_HUGETLB_PAGE */ +pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address); #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/powerpc/include/asm/pgtable.h b/trunk/arch/powerpc/include/asm/pgtable.h index 21207e54825b..2a5da069714e 100644 --- a/trunk/arch/powerpc/include/asm/pgtable.h +++ b/trunk/arch/powerpc/include/asm/pgtable.h @@ -211,9 +211,6 @@ extern void paging_init(void); */ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); -extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr, - unsigned long end, int write, struct page **pages, int *nr); - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/trunk/arch/powerpc/include/asm/pte-8xx.h b/trunk/arch/powerpc/include/asm/pte-8xx.h index d44826e4ff97..dd5ea95fe61e 100644 --- a/trunk/arch/powerpc/include/asm/pte-8xx.h +++ b/trunk/arch/powerpc/include/asm/pte-8xx.h @@ -33,21 +33,21 @@ #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */ -#define _PAGE_DIRTY 0x0100 /* C: page changed */ -/* These 4 software bits must be masked out when the entry is loaded - * into the TLB, 1 SW bit left(0x0080). +/* These five software bits must be masked out when the entry is loaded + * into the TLB. */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ -#define _PAGE_ACCESSED 0x0020 /* software: page referenced */ -#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ +#define _PAGE_DIRTY 0x0020 /* software: page changed */ +#define _PAGE_RW 0x0040 /* software: user write access allowed */ +#define _PAGE_ACCESSED 0x0080 /* software: page referenced */ /* Setting any bits in the nibble with the follow two controls will * require a TLB exception handler change. It is assumed unused bits * are always zero. */ -#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */ -#define _PAGE_USER 0x0800 /* msb PP bits */ +#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ +#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ #define _PMD_PRESENT 0x0001 #define _PMD_BAD 0x0ff0 diff --git a/trunk/arch/powerpc/include/asm/pte-hash64-64k.h b/trunk/arch/powerpc/include/asm/pte-hash64-64k.h index c4490f9c67c4..82b72207c51c 100644 --- a/trunk/arch/powerpc/include/asm/pte-hash64-64k.h +++ b/trunk/arch/powerpc/include/asm/pte-hash64-64k.h @@ -76,4 +76,41 @@ remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \ __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)) + +#ifdef CONFIG_PPC_SUBPAGE_PROT +/* + * For the sub-page protection option, we extend the PGD with one of + * these. Basically we have a 3-level tree, with the top level being + * the protptrs array. To optimize speed and memory consumption when + * only addresses < 4GB are being protected, pointers to the first + * four pages of sub-page protection words are stored in the low_prot + * array. + * Each page of sub-page protection words protects 1GB (4 bytes + * protects 64k). For the 3-level tree, each page of pointers then + * protects 8TB. + */ +struct subpage_prot_table { + unsigned long maxaddr; /* only addresses < this are protected */ + unsigned int **protptrs[2]; + unsigned int *low_prot[4]; +}; + +#undef PGD_TABLE_SIZE +#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \ + sizeof(struct subpage_prot_table)) + +#define SBP_L1_BITS (PAGE_SHIFT - 2) +#define SBP_L2_BITS (PAGE_SHIFT - 3) +#define SBP_L1_COUNT (1 << SBP_L1_BITS) +#define SBP_L2_COUNT (1 << SBP_L2_BITS) +#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) +#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) + +extern void subpage_prot_free(pgd_t *pgd); + +static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd) +{ + return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD); +} +#endif /* CONFIG_PPC_SUBPAGE_PROT */ #endif /* __ASSEMBLY__ */ diff --git a/trunk/arch/powerpc/include/asm/qe.h b/trunk/arch/powerpc/include/asm/qe.h index 0947b36e534c..f388f0ab193f 100644 --- a/trunk/arch/powerpc/include/asm/qe.h +++ b/trunk/arch/powerpc/include/asm/qe.h @@ -87,7 +87,7 @@ extern spinlock_t cmxgcr_lock; /* Export QE common operations */ #ifdef CONFIG_QUICC_ENGINE -extern void qe_reset(void); +extern void __init qe_reset(void); #else static inline void qe_reset(void) {} #endif @@ -145,17 +145,8 @@ static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} #endif /* CONFIG_QE_GPIO */ -#ifdef CONFIG_QUICC_ENGINE -int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); -#else -static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, - u32 cmd_input) -{ - return -ENOSYS; -} -#endif /* CONFIG_QUICC_ENGINE */ - /* QE internal API */ +int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); enum qe_clock qe_clock_source(const char *source); unsigned int qe_get_brg_clk(void); int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); @@ -163,28 +154,7 @@ int qe_get_snum(void); void qe_put_snum(u8 snum); unsigned int qe_get_num_of_risc(void); unsigned int qe_get_num_of_snums(void); - -static inline int qe_alive_during_sleep(void) -{ - /* - * MPC8568E reference manual says: - * - * "...power down sequence waits for all I/O interfaces to become idle. - * In some applications this may happen eventually without actively - * shutting down interfaces, but most likely, software will have to - * take steps to shut down the eTSEC, QUICC Engine Block, and PCI - * interfaces before issuing the command (either the write to the core - * MSR[WE] as described above or writing to POWMGTCSR) to put the - * device into sleep state." - * - * MPC8569E reference manual has a similar paragraph. - */ -#ifdef CONFIG_PPC_85xx - return 0; -#else - return 1; -#endif -} +int qe_alive_during_sleep(void); /* we actually use cpm_muram implementation, define this for convenience */ #define qe_muram_init cpm_muram_init @@ -240,15 +210,8 @@ struct qe_firmware_info { u64 extended_modes; /* Extended modes */ }; -#ifdef CONFIG_QUICC_ENGINE /* Upload a firmware to the QE */ int qe_upload_firmware(const struct qe_firmware *firmware); -#else -static inline int qe_upload_firmware(const struct qe_firmware *firmware) -{ - return -ENOSYS; -} -#endif /* CONFIG_QUICC_ENGINE */ /* Obtain information on the uploaded firmware */ struct qe_firmware_info *qe_get_firmware_info(void); diff --git a/trunk/arch/powerpc/include/asm/systbl.h b/trunk/arch/powerpc/include/asm/systbl.h index 07d2d19ab5e9..c7d671a7d9a1 100644 --- a/trunk/arch/powerpc/include/asm/systbl.h +++ b/trunk/arch/powerpc/include/asm/systbl.h @@ -145,7 +145,7 @@ SYSCALL_SPU(setfsuid) SYSCALL_SPU(setfsgid) SYSCALL_SPU(llseek) COMPAT_SYS_SPU(getdents) -SYSX_SPU(sys_select,ppc32_select,sys_select) +SYSX_SPU(sys_select,ppc32_select,ppc_select) SYSCALL_SPU(flock) SYSCALL_SPU(msync) COMPAT_SYS_SPU(readv) diff --git a/trunk/arch/powerpc/kernel/Makefile b/trunk/arch/powerpc/kernel/Makefile index c002b0410219..b23664a0b86c 100644 --- a/trunk/arch/powerpc/kernel/Makefile +++ b/trunk/arch/powerpc/kernel/Makefile @@ -42,11 +42,10 @@ obj-$(CONFIG_ALTIVEC) += vecemu.o obj-$(CONFIG_PPC_970_NAP) += idle_power4.o obj-$(CONFIG_PPC_OF) += of_device.o of_platform.o prom_parse.o obj-$(CONFIG_PPC_CLOCK) += clock.o -procfs-y := proc_powerpc.o +procfs-$(CONFIG_PPC64) := proc_ppc64.o obj-$(CONFIG_PROC_FS) += $(procfs-y) rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o obj-$(CONFIG_PPC_RTAS) += rtas.o rtas-rtc.o $(rtaspci-y-y) -obj-$(CONFIG_PPC_RTAS_DAEMON) += rtasd.o obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o obj-$(CONFIG_RTAS_PROC) += rtas-proc.o obj-$(CONFIG_LPARCFG) += lparcfg.o diff --git a/trunk/arch/powerpc/kernel/asm-offsets.c b/trunk/arch/powerpc/kernel/asm-offsets.c index a6c2b63227b3..0812b0f414bb 100644 --- a/trunk/arch/powerpc/kernel/asm-offsets.c +++ b/trunk/arch/powerpc/kernel/asm-offsets.c @@ -190,11 +190,6 @@ int main(void) DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset)); DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER - DEFINE(PACA_KVM_IN_GUEST, offsetof(struct paca_struct, kvm_in_guest)); - DEFINE(PACA_KVM_SLB, offsetof(struct paca_struct, kvm_slb)); - DEFINE(PACA_KVM_SLB_MAX, offsetof(struct paca_struct, kvm_slb_max)); -#endif #endif /* CONFIG_PPC64 */ /* RTAS */ @@ -403,24 +398,14 @@ int main(void) DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear)); DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr)); - - /* book3s_64 */ -#ifdef CONFIG_PPC64 - DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr)); - DEFINE(VCPU_HOST_RETIP, offsetof(struct kvm_vcpu, arch.host_retip)); - DEFINE(VCPU_HOST_R2, offsetof(struct kvm_vcpu, arch.host_r2)); - DEFINE(VCPU_HOST_MSR, offsetof(struct kvm_vcpu, arch.host_msr)); - DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr)); - DEFINE(VCPU_TRAMPOLINE_LOWMEM, offsetof(struct kvm_vcpu, arch.trampoline_lowmem)); - DEFINE(VCPU_TRAMPOLINE_ENTER, offsetof(struct kvm_vcpu, arch.trampoline_enter)); - DEFINE(VCPU_HIGHMEM_HANDLER, offsetof(struct kvm_vcpu, arch.highmem_handler)); - DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags)); -#endif #endif #ifdef CONFIG_44x DEFINE(PGD_T_LOG2, PGD_T_LOG2); DEFINE(PTE_T_LOG2, PTE_T_LOG2); #endif +#ifdef CONFIG_FSL_BOOKE + DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); +#endif #ifdef CONFIG_KVM_EXIT_TIMING DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu, diff --git a/trunk/arch/powerpc/kernel/crash.c b/trunk/arch/powerpc/kernel/crash.c index 6f4613dd05ef..0a8439aafdd1 100644 --- a/trunk/arch/powerpc/kernel/crash.c +++ b/trunk/arch/powerpc/kernel/crash.c @@ -373,7 +373,7 @@ void default_machine_crash_shutdown(struct pt_regs *regs) hard_irq_disable(); for_each_irq(i) { - struct irq_desc *desc = irq_to_desc(i); + struct irq_desc *desc = irq_desc + i; if (desc->status & IRQ_INPROGRESS) desc->chip->eoi(i); diff --git a/trunk/arch/powerpc/kernel/dma-swiotlb.c b/trunk/arch/powerpc/kernel/dma-swiotlb.c index 59c928564a03..e96cbbd9b449 100644 --- a/trunk/arch/powerpc/kernel/dma-swiotlb.c +++ b/trunk/arch/powerpc/kernel/dma-swiotlb.c @@ -21,6 +21,7 @@ #include #include +int swiotlb __read_mostly; unsigned int ppc_swiotlb_enable; /* diff --git a/trunk/arch/powerpc/kernel/exceptions-64s.S b/trunk/arch/powerpc/kernel/exceptions-64s.S index e3be98ffe2a7..c7eb4e0eb86c 100644 --- a/trunk/arch/powerpc/kernel/exceptions-64s.S +++ b/trunk/arch/powerpc/kernel/exceptions-64s.S @@ -41,7 +41,6 @@ __start_interrupts: . = 0x200 _machine_check_pSeries: HMT_MEDIUM - DO_KVM 0x200 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) @@ -49,7 +48,6 @@ _machine_check_pSeries: .globl data_access_pSeries data_access_pSeries: HMT_MEDIUM - DO_KVM 0x300 mtspr SPRN_SPRG_SCRATCH0,r13 BEGIN_FTR_SECTION mfspr r13,SPRN_SPRG_PACA @@ -79,7 +77,6 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) .globl data_access_slb_pSeries data_access_slb_pSeries: HMT_MEDIUM - DO_KVM 0x380 mtspr SPRN_SPRG_SCRATCH0,r13 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */ std r3,PACA_EXSLB+EX_R3(r13) @@ -118,7 +115,6 @@ data_access_slb_pSeries: .globl instruction_access_slb_pSeries instruction_access_slb_pSeries: HMT_MEDIUM - DO_KVM 0x480 mtspr SPRN_SPRG_SCRATCH0,r13 mfspr r13,SPRN_SPRG_PACA /* get paca address into r13 */ std r3,PACA_EXSLB+EX_R3(r13) @@ -158,7 +154,6 @@ instruction_access_slb_pSeries: .globl system_call_pSeries system_call_pSeries: HMT_MEDIUM - DO_KVM 0xc00 BEGIN_FTR_SECTION cmpdi r0,0x1ebe beq- 1f @@ -192,17 +187,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) */ performance_monitor_pSeries_1: . = 0xf00 - DO_KVM 0xf00 b performance_monitor_pSeries altivec_unavailable_pSeries_1: . = 0xf20 - DO_KVM 0xf20 b altivec_unavailable_pSeries vsx_unavailable_pSeries_1: . = 0xf40 - DO_KVM 0xf40 b vsx_unavailable_pSeries #ifdef CONFIG_CBE_RAS diff --git a/trunk/arch/powerpc/kernel/head_64.S b/trunk/arch/powerpc/kernel/head_64.S index 925807488022..c38afdb45d7b 100644 --- a/trunk/arch/powerpc/kernel/head_64.S +++ b/trunk/arch/powerpc/kernel/head_64.S @@ -37,7 +37,6 @@ #include #include #include -#include /* The physical memory is layed out such that the secondary processor * spin code sits at 0x0000...0x00ff. On server, the vectors follow @@ -166,12 +165,6 @@ exception_marker: #include "exceptions-64s.S" #endif -/* KVM trampoline code needs to be close to the interrupt handlers */ - -#ifdef CONFIG_KVM_BOOK3S_64_HANDLER -#include "../kvm/book3s_64_rmhandlers.S" -#endif - _GLOBAL(generic_secondary_thread_init) mr r24,r3 diff --git a/trunk/arch/powerpc/kernel/head_8xx.S b/trunk/arch/powerpc/kernel/head_8xx.S index 678f98cd5e64..6ded19d01891 100644 --- a/trunk/arch/powerpc/kernel/head_8xx.S +++ b/trunk/arch/powerpc/kernel/head_8xx.S @@ -206,8 +206,6 @@ MachineCheck: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) - li r5,0x00f0 - mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addi r3,r1,STACK_FRAME_OVERHEAD @@ -224,8 +222,6 @@ DataAccess: stw r10,_DSISR(r11) mr r5,r10 mfspr r4,SPRN_DAR - li r10,0x00f0 - mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ EXC_XFER_EE_LITE(0x300, handle_page_fault) /* Instruction access exception. @@ -248,8 +244,6 @@ Alignment: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) - li r5,0x00f0 - mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addi r3,r1,STACK_FRAME_OVERHEAD @@ -339,20 +333,26 @@ InstructionTLBMiss: mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ lwz r10, 0(r11) /* Get the pte */ - andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT - cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT - bne- cr0, 2f - - /* Clear PP lsb, 0x400 */ - rlwinm r10, r10, 0, 22, 20 +#ifdef CONFIG_SWAP + /* do not set the _PAGE_ACCESSED bit of a non-present page */ + andi. r11, r10, _PAGE_PRESENT + beq 4f + ori r10, r10, _PAGE_ACCESSED + mfspr r11, SPRN_MD_TWC /* get the pte address again */ + stw r10, 0(r11) +4: +#else + ori r10, r10, _PAGE_ACCESSED + stw r10, 0(r11) +#endif /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 22 and 28 must be clear. + * Software indicator bits 21, 22 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ - li r11, 0x00f0 +2: li r11, 0x00f0 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x2d80, r3) mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ @@ -365,22 +365,6 @@ InstructionTLBMiss: lwz r3, 8(r0) #endif rfi -2: - mfspr r11, SPRN_SRR1 - /* clear all error bits as TLB Miss - * sets a few unconditionally - */ - rlwinm r11, r11, 0, 0xffff - mtspr SPRN_SRR1, r11 - - mfspr r10, SPRN_M_TW /* Restore registers */ - lwz r11, 0(r0) - mtcr r11 - lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - b InstructionAccess . = 0x1200 DataStoreTLBMiss: @@ -422,45 +406,29 @@ DataStoreTLBMiss: * above. */ rlwimi r11, r10, 0, 27, 27 - /* Insert the WriteThru flag into the TWC from the Linux PTE. - * It is bit 25 in the Linux PTE and bit 30 in the TWC - */ - rlwimi r11, r10, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr SPRN_MD_TWC, r11 - /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. - * We also need to know if the insn is a load/store, so: - * Clear _PAGE_PRESENT and load that which will - * trap into DTLB Error with store bit set accordinly. - */ - /* PRESENT=0x1, ACCESSED=0x20 - * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); - * r10 = (r10 & ~PRESENT) | r11; - */ - rlwinm r11, r10, 32-5, _PAGE_PRESENT - and r11, r11, r10 - rlwimi r10, r11, 0, _PAGE_PRESENT - - /* Honour kernel RO, User NA */ - /* 0x200 == Extended encoding, bit 22 */ - /* r11 = (r10 & _PAGE_USER) >> 2 */ - rlwinm r11, r10, 32-2, 0x200 - or r10, r11, r10 - /* r11 = (r10 & _PAGE_RW) >> 1 */ - rlwinm r11, r10, 32-1, 0x200 - or r10, r11, r10 - /* invert RW and 0x200 bits */ - xori r10, r10, _PAGE_RW | 0x200 +#ifdef CONFIG_SWAP + /* do not set the _PAGE_ACCESSED bit of a non-present page */ + andi. r11, r10, _PAGE_PRESENT + beq 4f + ori r10, r10, _PAGE_ACCESSED +4: + /* and update pte in table */ +#else + ori r10, r10, _PAGE_ACCESSED +#endif + mfspr r11, SPRN_MD_TWC /* get the pte address again */ + stw r10, 0(r11) /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 22 and 28 must be clear. + * Software indicator bits 21, 22 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ 2: li r11, 0x00f0 - mtspr SPRN_DAR,r11 /* Tag DAR */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ @@ -501,10 +469,97 @@ DataTLBError: stw r10, 0(r0) stw r11, 4(r0) + /* First, make sure this was a store operation. + */ + mfspr r10, SPRN_DSISR + andis. r11, r10, 0x0200 /* If set, indicates store op */ + beq 2f + + /* The EA of a data TLB miss is automatically stored in the MD_EPN + * register. The EA of a data TLB error is automatically stored in + * the DAR, but not the MD_EPN register. We must copy the 20 most + * significant bits of the EA from the DAR to MD_EPN before we + * start walking the page tables. We also need to copy the CASID + * value from the M_CASID register. + * Addendum: The EA of a data TLB error is _supposed_ to be stored + * in DAR, but it seems that this doesn't happen in some cases, such + * as when the error is due to a dcbi instruction to a page with a + * TLB that doesn't have the changed bit set. In such cases, there + * does not appear to be any way to recover the EA of the error + * since it is neither in DAR nor MD_EPN. As a workaround, the + * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs + * are initialized in mapin_ram(). This will avoid the problem, + * assuming we only use the dcbi instruction on kernel addresses. + */ mfspr r10, SPRN_DAR - cmpwi cr0, r10, 0x00f0 - beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ -DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ + rlwinm r11, r10, 0, 0, 19 + ori r11, r11, MD_EVALID + mfspr r10, SPRN_M_CASID + rlwimi r11, r10, 0, 28, 31 + DO_8xx_CPU6(0x3780, r3) + mtspr SPRN_MD_EPN, r11 + + mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andi. r11, r10, 0x0800 + beq 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + rlwimi r10, r11, 0, 2, 19 +3: + lwz r11, 0(r10) /* Get the level 1 entry */ + rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ + beq 2f /* If zero, bail */ + + /* We have a pte table, so fetch the pte from the table. + */ + ori r11, r11, 1 /* Set valid bit in physical L2 page */ + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ + mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ + lwz r10, 0(r11) /* Get the pte */ + + andi. r11, r10, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail out if not */ + + /* Update 'changed', among others. + */ +#ifdef CONFIG_SWAP + ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE + /* do not set the _PAGE_ACCESSED bit of a non-present page */ + andi. r11, r10, _PAGE_PRESENT + beq 4f + ori r10, r10, _PAGE_ACCESSED +4: +#else + ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE +#endif + mfspr r11, SPRN_MD_TWC /* Get pte address again */ + stw r10, 0(r11) /* and update pte in table */ + + /* The Linux PTE won't go exactly into the MMU TLB. + * Software indicator bits 21, 22 and 28 must be clear. + * Software indicator bits 24, 25, 26, and 27 must be + * set. All other Linux PTE bits control the behavior + * of the MMU. + */ + li r11, 0x00f0 + rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + DO_8xx_CPU6(0x3d80, r3) + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ + + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + rfi +2: mfspr r10, SPRN_M_TW /* Restore registers */ lwz r11, 0(r0) mtcr r11 @@ -533,140 +588,6 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR . = 0x2000 -/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions - * by decoding the registers used by the dcbx instruction and adding them. - * DAR is set to the calculated address and r10 also holds the EA on exit. - */ - /* define if you don't want to use self modifying code */ -#define NO_SELF_MODIFYING_CODE -FixupDAR:/* Entry point for dcbx workaround. */ - /* fetch instruction from memory. */ - mfspr r10, SPRN_SRR0 - DO_8xx_CPU6(0x3780, r3) - mtspr SPRN_MD_EPN, r10 - mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ - cmplwi cr0, r11, 0x0800 - blt- 3f /* Branch if user space */ - lis r11, (swapper_pg_dir-PAGE_OFFSET)@h - ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l - rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ -3: lwz r11, 0(r11) /* Get the level 1 entry */ - DO_8xx_CPU6(0x3b80, r3) - mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ - mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ - lwz r11, 0(r11) /* Get the pte */ - /* concat physical page address(r11) and page offset(r10) */ - rlwimi r11, r10, 0, 20, 31 - lwz r11,0(r11) -/* Check if it really is a dcbx instruction. */ -/* dcbt and dcbtst does not generate DTLB Misses/Errors, - * no need to include them here */ - srwi r10, r11, 26 /* check if major OP code is 31 */ - cmpwi cr0, r10, 31 - bne- 141f - rlwinm r10, r11, 0, 21, 30 - cmpwi cr0, r10, 2028 /* Is dcbz? */ - beq+ 142f - cmpwi cr0, r10, 940 /* Is dcbi? */ - beq+ 142f - cmpwi cr0, r10, 108 /* Is dcbst? */ - beq+ 144f /* Fix up store bit! */ - cmpwi cr0, r10, 172 /* Is dcbf? */ - beq+ 142f - cmpwi cr0, r10, 1964 /* Is icbi? */ - beq+ 142f -141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ - b DARFixed /* Nope, go back to normal TLB processing */ - -144: mfspr r10, SPRN_DSISR - rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ - mtspr SPRN_DSISR, r10 -142: /* continue, it was a dcbx, dcbi instruction. */ -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) /* restore r3 from memory */ -#endif -#ifndef NO_SELF_MODIFYING_CODE - andis. r10,r11,0x1f /* test if reg RA is r0 */ - li r10,modified_instr@l - dcbtst r0,r10 /* touch for store */ - rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ - oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ - ori r11,r11,532 - stw r11,0(r10) /* store add/and instruction */ - dcbf 0,r10 /* flush new instr. to memory. */ - icbi 0,r10 /* invalidate instr. cache line */ - lwz r11, 4(r0) /* restore r11 from memory */ - mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ - isync /* Wait until new instr is loaded from memory */ -modified_instr: - .space 4 /* this is where the add instr. is stored */ - bne+ 143f - subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ -143: mtdar r10 /* store faulting EA in DAR */ - b DARFixed /* Go back to normal TLB handling */ -#else - mfctr r10 - mtdar r10 /* save ctr reg in DAR */ - rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ - addi r10, r10, 150f@l /* add start of table */ - mtctr r10 /* load ctr with jump address */ - xor r10, r10, r10 /* sum starts at zero */ - bctr /* jump into table */ -150: - add r10, r10, r0 ;b 151f - add r10, r10, r1 ;b 151f - add r10, r10, r2 ;b 151f - add r10, r10, r3 ;b 151f - add r10, r10, r4 ;b 151f - add r10, r10, r5 ;b 151f - add r10, r10, r6 ;b 151f - add r10, r10, r7 ;b 151f - add r10, r10, r8 ;b 151f - add r10, r10, r9 ;b 151f - mtctr r11 ;b 154f /* r10 needs special handling */ - mtctr r11 ;b 153f /* r11 needs special handling */ - add r10, r10, r12 ;b 151f - add r10, r10, r13 ;b 151f - add r10, r10, r14 ;b 151f - add r10, r10, r15 ;b 151f - add r10, r10, r16 ;b 151f - add r10, r10, r17 ;b 151f - add r10, r10, r18 ;b 151f - add r10, r10, r19 ;b 151f - add r10, r10, r20 ;b 151f - add r10, r10, r21 ;b 151f - add r10, r10, r22 ;b 151f - add r10, r10, r23 ;b 151f - add r10, r10, r24 ;b 151f - add r10, r10, r25 ;b 151f - add r10, r10, r26 ;b 151f - add r10, r10, r27 ;b 151f - add r10, r10, r28 ;b 151f - add r10, r10, r29 ;b 151f - add r10, r10, r30 ;b 151f - add r10, r10, r31 -151: - rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ - beq 152f /* if reg RA is zero, don't add it */ - addi r11, r11, 150b@l /* add start of table */ - mtctr r11 /* load ctr with jump address */ - rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ - bctr /* jump into table */ -152: - mfdar r11 - mtctr r11 /* restore ctr reg from DAR */ - mtdar r10 /* save fault EA to DAR */ - b DARFixed /* Go back to normal TLB handling */ - - /* special handling for r10,r11 since these are modified already */ -153: lwz r11, 4(r0) /* load r11 from memory */ - b 155f -154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ -155: add r10, r10, r11 /* add it */ - mfctr r11 /* restore r11 */ - b 151b -#endif - .globl giveup_fpu giveup_fpu: blr diff --git a/trunk/arch/powerpc/kernel/head_fsl_booke.S b/trunk/arch/powerpc/kernel/head_fsl_booke.S index 7f4bd7f3b6af..975788ca05d2 100644 --- a/trunk/arch/powerpc/kernel/head_fsl_booke.S +++ b/trunk/arch/powerpc/kernel/head_fsl_booke.S @@ -943,6 +943,28 @@ _GLOBAL(__setup_e500mc_ivors) sync blr +/* + * extern void loadcam_entry(unsigned int index) + * + * Load TLBCAM[index] entry in to the L2 CAM MMU + */ +_GLOBAL(loadcam_entry) + lis r4,TLBCAM@ha + addi r4,r4,TLBCAM@l + mulli r5,r3,TLBCAM_SIZE + add r3,r5,r4 + lwz r4,0(r3) + mtspr SPRN_MAS0,r4 + lwz r4,4(r3) + mtspr SPRN_MAS1,r4 + lwz r4,8(r3) + mtspr SPRN_MAS2,r4 + lwz r4,12(r3) + mtspr SPRN_MAS3,r4 + tlbwe + isync + blr + /* * extern void giveup_altivec(struct task_struct *prev) * diff --git a/trunk/arch/powerpc/kernel/io.c b/trunk/arch/powerpc/kernel/io.c index 8dc7547c2377..1882bf419fa6 100644 --- a/trunk/arch/powerpc/kernel/io.c +++ b/trunk/arch/powerpc/kernel/io.c @@ -161,7 +161,7 @@ void _memcpy_fromio(void *dest, const volatile void __iomem *src, dest++; n--; } - while(n >= 4) { + while(n > 4) { *((u32 *)dest) = *((volatile u32 *)vsrc); eieio(); vsrc += 4; @@ -190,7 +190,7 @@ void _memcpy_toio(volatile void __iomem *dest, const void *src, unsigned long n) vdest++; n--; } - while(n >= 4) { + while(n > 4) { *((volatile u32 *)vdest) = *((volatile u32 *)src); src += 4; vdest += 4; diff --git a/trunk/arch/powerpc/kernel/irq.c b/trunk/arch/powerpc/kernel/irq.c index f6dca4f4b295..02a334662cc0 100644 --- a/trunk/arch/powerpc/kernel/irq.c +++ b/trunk/arch/powerpc/kernel/irq.c @@ -87,10 +87,7 @@ extern int tau_interrupts(int); #endif /* CONFIG_PPC32 */ #ifdef CONFIG_PPC64 - -#ifndef CONFIG_SPARSE_IRQ EXPORT_SYMBOL(irq_desc); -#endif int distribute_irqs = 1; @@ -192,7 +189,33 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "CPU%d ", j); seq_putc(p, '\n'); - } else if (i == nr_irqs) { + } + + if (i < NR_IRQS) { + desc = get_irq_desc(i); + spin_lock_irqsave(&desc->lock, flags); + action = desc->action; + if (!action || !action->handler) + goto skip; + seq_printf(p, "%3d: ", i); +#ifdef CONFIG_SMP + for_each_online_cpu(j) + seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); +#else + seq_printf(p, "%10u ", kstat_irqs(i)); +#endif /* CONFIG_SMP */ + if (desc->chip) + seq_printf(p, " %s ", desc->chip->typename); + else + seq_puts(p, " None "); + seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge "); + seq_printf(p, " %s", action->name); + for (action = action->next; action; action = action->next) + seq_printf(p, ", %s", action->name); + seq_putc(p, '\n'); +skip: + spin_unlock_irqrestore(&desc->lock, flags); + } else if (i == NR_IRQS) { #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT) if (tau_initialized){ seq_puts(p, "TAU: "); @@ -202,68 +225,30 @@ int show_interrupts(struct seq_file *p, void *v) } #endif /* CONFIG_PPC32 && CONFIG_TAU_INT*/ seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts); - - return 0; } - - desc = irq_to_desc(i); - if (!desc) - return 0; - - spin_lock_irqsave(&desc->lock, flags); - - action = desc->action; - if (!action || !action->handler) - goto skip; - - seq_printf(p, "%3d: ", i); -#ifdef CONFIG_SMP - for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); -#else - seq_printf(p, "%10u ", kstat_irqs(i)); -#endif /* CONFIG_SMP */ - - if (desc->chip) - seq_printf(p, " %s ", desc->chip->name); - else - seq_puts(p, " None "); - - seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge "); - seq_printf(p, " %s", action->name); - - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - seq_putc(p, '\n'); - -skip: - spin_unlock_irqrestore(&desc->lock, flags); - return 0; } #ifdef CONFIG_HOTPLUG_CPU void fixup_irqs(cpumask_t map) { - struct irq_desc *desc; unsigned int irq; static int warned; for_each_irq(irq) { cpumask_t mask; - desc = irq_to_desc(irq); - if (desc && desc->status & IRQ_PER_CPU) + if (irq_desc[irq].status & IRQ_PER_CPU) continue; - cpumask_and(&mask, desc->affinity, &map); + cpumask_and(&mask, irq_desc[irq].affinity, &map); if (any_online_cpu(mask) == NR_CPUS) { printk("Breaking affinity for irq %i\n", irq); mask = map; } - if (desc->chip->set_affinity) - desc->chip->set_affinity(irq, &mask); - else if (desc->action && !(warned++)) + if (irq_desc[irq].chip->set_affinity) + irq_desc[irq].chip->set_affinity(irq, &mask); + else if (irq_desc[irq].action && !(warned++)) printk("Cannot set affinity for irq %i\n", irq); } @@ -290,7 +275,7 @@ static inline void handle_one_irq(unsigned int irq) return; } - desc = irq_to_desc(irq); + desc = irq_desc + irq; saved_sp_limit = current->thread.ksp_limit; irqtp->task = curtp->task; @@ -556,7 +541,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node, smp_wmb(); /* Clear norequest flags */ - irq_to_desc(i)->status &= ~IRQ_NOREQUEST; + get_irq_desc(i)->status &= ~IRQ_NOREQUEST; /* Legacy flags are left to default at this point, * one can then use irq_create_mapping() to @@ -622,16 +607,8 @@ void irq_set_virq_count(unsigned int count) static int irq_setup_virq(struct irq_host *host, unsigned int virq, irq_hw_number_t hwirq) { - struct irq_desc *desc; - - desc = irq_to_desc_alloc_node(virq, 0); - if (!desc) { - pr_debug("irq: -> allocating desc failed\n"); - goto error; - } - /* Clear IRQ_NOREQUEST flag */ - desc->status &= ~IRQ_NOREQUEST; + get_irq_desc(virq)->status &= ~IRQ_NOREQUEST; /* map it */ smp_wmb(); @@ -640,14 +617,11 @@ static int irq_setup_virq(struct irq_host *host, unsigned int virq, if (host->ops->map(host, virq, hwirq)) { pr_debug("irq: -> mapping failed, freeing\n"); - goto error; + irq_free_virt(virq, 1); + return -1; } return 0; - -error: - irq_free_virt(virq, 1); - return -1; } unsigned int irq_create_direct_mapping(struct irq_host *host) @@ -731,7 +705,7 @@ unsigned int irq_create_mapping(struct irq_host *host, EXPORT_SYMBOL_GPL(irq_create_mapping); unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) + u32 *intspec, unsigned int intsize) { struct irq_host *host; irq_hw_number_t hwirq; @@ -764,7 +738,7 @@ unsigned int irq_create_of_mapping(struct device_node *controller, /* Set type if specified and different than the current one */ if (type != IRQ_TYPE_NONE && - type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) + type != (get_irq_desc(virq)->status & IRQF_TRIGGER_MASK)) set_irq_type(virq, type); return virq; } @@ -836,7 +810,7 @@ void irq_dispose_mapping(unsigned int virq) irq_map[virq].hwirq = host->inval_irq; /* Set some flags */ - irq_to_desc(virq)->status |= IRQ_NOREQUEST; + get_irq_desc(virq)->status |= IRQ_NOREQUEST; /* Free it */ irq_free_virt(virq, 1); @@ -1028,24 +1002,12 @@ void irq_free_virt(unsigned int virq, unsigned int count) spin_unlock_irqrestore(&irq_big_lock, flags); } -int arch_early_irq_init(void) +void irq_early_init(void) { - struct irq_desc *desc; - int i; - - for (i = 0; i < NR_IRQS; i++) { - desc = irq_to_desc(i); - if (desc) - desc->status |= IRQ_NOREQUEST; - } - - return 0; -} + unsigned int i; -int arch_init_chip_data(struct irq_desc *desc, int node) -{ - desc->status |= IRQ_NOREQUEST; - return 0; + for (i = 0; i < NR_IRQS; i++) + get_irq_desc(i)->status |= IRQ_NOREQUEST; } /* We need to create the radix trees late */ @@ -1107,19 +1069,16 @@ static int virq_debug_show(struct seq_file *m, void *private) seq_printf(m, "%-5s %-7s %-15s %s\n", "virq", "hwirq", "chip name", "host name"); - for (i = 1; i < nr_irqs; i++) { - desc = irq_to_desc(i); - if (!desc) - continue; - + for (i = 1; i < NR_IRQS; i++) { + desc = get_irq_desc(i); spin_lock_irqsave(&desc->lock, flags); if (desc->action && desc->action->handler) { seq_printf(m, "%5d ", i); seq_printf(m, "0x%05lx ", virq_to_hw(i)); - if (desc->chip && desc->chip->name) - p = desc->chip->name; + if (desc->chip && desc->chip->typename) + p = desc->chip->typename; else p = none; seq_printf(m, "%-15s ", p); diff --git a/trunk/arch/powerpc/kernel/lparcfg.c b/trunk/arch/powerpc/kernel/lparcfg.c index 79a00bb9c64c..ed0ac4e4b8d8 100644 --- a/trunk/arch/powerpc/kernel/lparcfg.c +++ b/trunk/arch/powerpc/kernel/lparcfg.c @@ -781,9 +781,9 @@ static int __init lparcfg_init(void) !firmware_has_feature(FW_FEATURE_ISERIES)) mode |= S_IWUSR; - ent = proc_create("powerpc/lparcfg", mode, NULL, &lparcfg_fops); + ent = proc_create("ppc64/lparcfg", mode, NULL, &lparcfg_fops); if (!ent) { - printk(KERN_ERR "Failed to create powerpc/lparcfg\n"); + printk(KERN_ERR "Failed to create ppc64/lparcfg\n"); return -EIO; } diff --git a/trunk/arch/powerpc/kernel/misc_32.S b/trunk/arch/powerpc/kernel/misc_32.S index 8649f536f8df..da9c0c4c10f3 100644 --- a/trunk/arch/powerpc/kernel/misc_32.S +++ b/trunk/arch/powerpc/kernel/misc_32.S @@ -502,7 +502,15 @@ _GLOBAL(clear_pages) li r0,PAGE_SIZE/L1_CACHE_BYTES slw r0,r0,r4 mtctr r0 +#ifdef CONFIG_8xx + li r4, 0 +1: stw r4, 0(r3) + stw r4, 4(r3) + stw r4, 8(r3) + stw r4, 12(r3) +#else 1: dcbz 0,r3 +#endif addi r3,r3,L1_CACHE_BYTES bdnz 1b blr @@ -527,6 +535,15 @@ _GLOBAL(copy_page) addi r3,r3,-4 addi r4,r4,-4 +#ifdef CONFIG_8xx + /* don't use prefetch on 8xx */ + li r0,4096/L1_CACHE_BYTES + mtctr r0 +1: COPY_16_BYTES + bdnz 1b + blr + +#else /* not 8xx, we can prefetch */ li r5,4 #if MAX_COPY_PREFETCH > 1 @@ -567,6 +584,7 @@ _GLOBAL(copy_page) li r0,MAX_COPY_PREFETCH li r11,4 b 2b +#endif /* CONFIG_8xx */ /* * void atomic_clear_mask(atomic_t mask, atomic_t *addr) diff --git a/trunk/arch/powerpc/kernel/nvram_64.c b/trunk/arch/powerpc/kernel/nvram_64.c index ad461e735aec..0ed31f220482 100644 --- a/trunk/arch/powerpc/kernel/nvram_64.c +++ b/trunk/arch/powerpc/kernel/nvram_64.c @@ -139,8 +139,8 @@ static ssize_t dev_nvram_write(struct file *file, const char __user *buf, } -static long dev_nvram_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) +static int dev_nvram_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) { switch(cmd) { #ifdef CONFIG_PPC_PMAC @@ -169,11 +169,11 @@ static long dev_nvram_ioctl(struct file *file, unsigned int cmd, } const struct file_operations nvram_fops = { - .owner = THIS_MODULE, - .llseek = dev_nvram_llseek, - .read = dev_nvram_read, - .write = dev_nvram_write, - .unlocked_ioctl = dev_nvram_ioctl, + .owner = THIS_MODULE, + .llseek = dev_nvram_llseek, + .read = dev_nvram_read, + .write = dev_nvram_write, + .ioctl = dev_nvram_ioctl, }; static struct miscdevice nvram_dev = { @@ -184,7 +184,7 @@ static struct miscdevice nvram_dev = { #ifdef DEBUG_NVRAM -static void __init nvram_print_partitions(char * label) +static void nvram_print_partitions(char * label) { struct list_head * p; struct nvram_partition * tmp_part; @@ -202,7 +202,7 @@ static void __init nvram_print_partitions(char * label) #endif -static int __init nvram_write_header(struct nvram_partition * part) +static int nvram_write_header(struct nvram_partition * part) { loff_t tmp_index; int rc; @@ -214,7 +214,7 @@ static int __init nvram_write_header(struct nvram_partition * part) } -static unsigned char __init nvram_checksum(struct nvram_header *p) +static unsigned char nvram_checksum(struct nvram_header *p) { unsigned int c_sum, c_sum2; unsigned short *sp = (unsigned short *)p->name; /* assume 6 shorts */ @@ -228,7 +228,32 @@ static unsigned char __init nvram_checksum(struct nvram_header *p) return c_sum; } -static int __init nvram_remove_os_partition(void) + +/* + * Find an nvram partition, sig can be 0 for any + * partition or name can be NULL for any name, else + * tries to match both + */ +struct nvram_partition *nvram_find_partition(int sig, const char *name) +{ + struct nvram_partition * part; + struct list_head * p; + + list_for_each(p, &nvram_part->partition) { + part = list_entry(p, struct nvram_partition, partition); + + if (sig && part->header.signature != sig) + continue; + if (name && 0 != strncmp(name, part->header.name, 12)) + continue; + return part; + } + return NULL; +} +EXPORT_SYMBOL(nvram_find_partition); + + +static int nvram_remove_os_partition(void) { struct list_head *i; struct list_head *j; @@ -294,7 +319,7 @@ static int __init nvram_remove_os_partition(void) * Will create a partition starting at the first free * space found if space has enough room. */ -static int __init nvram_create_os_partition(void) +static int nvram_create_os_partition(void) { struct nvram_partition *part; struct nvram_partition *new_part; @@ -397,7 +422,7 @@ static int __init nvram_create_os_partition(void) * 5.) If the max chunk cannot be allocated then try finding a chunk * that will satisfy the minum needed (NVRAM_MIN_REQ). */ -static int __init nvram_setup_partition(void) +static int nvram_setup_partition(void) { struct list_head * p; struct nvram_partition * part; @@ -455,7 +480,7 @@ static int __init nvram_setup_partition(void) } -static int __init nvram_scan_partitions(void) +static int nvram_scan_partitions(void) { loff_t cur_index = 0; struct nvram_header phead; @@ -681,9 +706,6 @@ int nvram_clear_error_log(void) int clear_word = ERR_FLAG_ALREADY_LOGGED; int rc; - if (nvram_error_log_index == -1) - return -1; - tmp_index = nvram_error_log_index; rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index); diff --git a/trunk/arch/powerpc/kernel/perf_callchain.c b/trunk/arch/powerpc/kernel/perf_callchain.c index 936f04dbfc6f..0a03cf70d247 100644 --- a/trunk/arch/powerpc/kernel/perf_callchain.c +++ b/trunk/arch/powerpc/kernel/perf_callchain.c @@ -119,6 +119,13 @@ static void perf_callchain_kernel(struct pt_regs *regs, } #ifdef CONFIG_PPC64 + +#ifdef CONFIG_HUGETLB_PAGE +#define is_huge_psize(pagesize) (HPAGE_SHIFT && mmu_huge_psizes[pagesize]) +#else +#define is_huge_psize(pagesize) 0 +#endif + /* * On 64-bit we don't want to invoke hash_page on user addresses from * interrupt context, so if the access faults, we read the page tables @@ -128,7 +135,7 @@ static int read_user_stack_slow(void __user *ptr, void *ret, int nb) { pgd_t *pgdir; pte_t *ptep, pte; - unsigned shift; + int pagesize; unsigned long addr = (unsigned long) ptr; unsigned long offset; unsigned long pfn; @@ -138,14 +145,17 @@ static int read_user_stack_slow(void __user *ptr, void *ret, int nb) if (!pgdir) return -EFAULT; - ptep = find_linux_pte_or_hugepte(pgdir, addr, &shift); - if (!shift) - shift = PAGE_SHIFT; + pagesize = get_slice_psize(current->mm, addr); /* align address to page boundary */ - offset = addr & ((1UL << shift) - 1); + offset = addr & ((1ul << mmu_psize_defs[pagesize].shift) - 1); addr -= offset; + if (is_huge_psize(pagesize)) + ptep = huge_pte_offset(current->mm, addr); + else + ptep = find_linux_pte(pgdir, addr); + if (ptep == NULL) return -EFAULT; pte = *ptep; diff --git a/trunk/arch/powerpc/kernel/ppc_ksyms.c b/trunk/arch/powerpc/kernel/ppc_ksyms.c index 425451453e96..c8b27bb4dbde 100644 --- a/trunk/arch/powerpc/kernel/ppc_ksyms.c +++ b/trunk/arch/powerpc/kernel/ppc_ksyms.c @@ -96,6 +96,8 @@ EXPORT_SYMBOL(copy_4K_page); EXPORT_SYMBOL(isa_io_base); EXPORT_SYMBOL(isa_mem_base); EXPORT_SYMBOL(pci_dram_offset); +EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(pci_free_consistent); #endif /* CONFIG_PCI */ EXPORT_SYMBOL(start_thread); @@ -160,6 +162,7 @@ EXPORT_SYMBOL(screen_info); #ifdef CONFIG_PPC32 EXPORT_SYMBOL(timer_interrupt); +EXPORT_SYMBOL(irq_desc); EXPORT_SYMBOL(tb_ticks_per_jiffy); EXPORT_SYMBOL(cacheable_memcpy); EXPORT_SYMBOL(cacheable_memzero); diff --git a/trunk/arch/powerpc/kernel/proc_powerpc.c b/trunk/arch/powerpc/kernel/proc_ppc64.c similarity index 87% rename from trunk/arch/powerpc/kernel/proc_powerpc.c rename to trunk/arch/powerpc/kernel/proc_ppc64.c index 1ed3b8d7981e..c647ddef40dc 100644 --- a/trunk/arch/powerpc/kernel/proc_powerpc.c +++ b/trunk/arch/powerpc/kernel/proc_ppc64.c @@ -28,7 +28,55 @@ #include #include -#ifdef CONFIG_PPC64 +static loff_t page_map_seek( struct file *file, loff_t off, int whence); +static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes, + loff_t *ppos); +static int page_map_mmap( struct file *file, struct vm_area_struct *vma ); + +static const struct file_operations page_map_fops = { + .llseek = page_map_seek, + .read = page_map_read, + .mmap = page_map_mmap +}; + +/* + * Create the ppc64 and ppc64/rtas directories early. This allows us to + * assume that they have been previously created in drivers. + */ +static int __init proc_ppc64_create(void) +{ + struct proc_dir_entry *root; + + root = proc_mkdir("ppc64", NULL); + if (!root) + return 1; + + if (!of_find_node_by_path("/rtas")) + return 0; + + if (!proc_mkdir("rtas", root)) + return 1; + + if (!proc_symlink("rtas", NULL, "ppc64/rtas")) + return 1; + + return 0; +} +core_initcall(proc_ppc64_create); + +static int __init proc_ppc64_init(void) +{ + struct proc_dir_entry *pde; + + pde = proc_create_data("ppc64/systemcfg", S_IFREG|S_IRUGO, NULL, + &page_map_fops, vdso_data); + if (!pde) + return 1; + pde->size = PAGE_SIZE; + + return 0; +} +__initcall(proc_ppc64_init); static loff_t page_map_seek( struct file *file, loff_t off, int whence) { @@ -72,55 +120,3 @@ static int page_map_mmap( struct file *file, struct vm_area_struct *vma ) return 0; } -static const struct file_operations page_map_fops = { - .llseek = page_map_seek, - .read = page_map_read, - .mmap = page_map_mmap -}; - - -static int __init proc_ppc64_init(void) -{ - struct proc_dir_entry *pde; - - pde = proc_create_data("powerpc/systemcfg", S_IFREG|S_IRUGO, NULL, - &page_map_fops, vdso_data); - if (!pde) - return 1; - pde->size = PAGE_SIZE; - - return 0; -} -__initcall(proc_ppc64_init); - -#endif /* CONFIG_PPC64 */ - -/* - * Create the ppc64 and ppc64/rtas directories early. This allows us to - * assume that they have been previously created in drivers. - */ -static int __init proc_ppc64_create(void) -{ - struct proc_dir_entry *root; - - root = proc_mkdir("powerpc", NULL); - if (!root) - return 1; - -#ifdef CONFIG_PPC64 - if (!proc_symlink("ppc64", NULL, "powerpc")) - pr_err("Failed to create link /proc/ppc64 -> /proc/powerpc\n"); -#endif - - if (!of_find_node_by_path("/rtas")) - return 0; - - if (!proc_mkdir("rtas", root)) - return 1; - - if (!proc_symlink("rtas", NULL, "powerpc/rtas")) - return 1; - - return 0; -} -core_initcall(proc_ppc64_create); diff --git a/trunk/arch/powerpc/kernel/rtas_flash.c b/trunk/arch/powerpc/kernel/rtas_flash.c index a85117d5c9a4..13011a96a977 100644 --- a/trunk/arch/powerpc/kernel/rtas_flash.c +++ b/trunk/arch/powerpc/kernel/rtas_flash.c @@ -6,7 +6,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * /proc/powerpc/rtas/firmware_flash interface + * /proc/ppc64/rtas/firmware_flash interface * * This file implements a firmware_flash interface to pump a firmware * image into the kernel. At reboot time rtas_restart() will see the @@ -740,7 +740,7 @@ static int __init rtas_flash_init(void) return 1; } - firmware_flash_pde = create_flash_pde("powerpc/rtas/" + firmware_flash_pde = create_flash_pde("ppc64/rtas/" FIRMWARE_FLASH_NAME, &rtas_flash_operations); if (firmware_flash_pde == NULL) { @@ -754,7 +754,7 @@ static int __init rtas_flash_init(void) if (rc != 0) goto cleanup; - firmware_update_pde = create_flash_pde("powerpc/rtas/" + firmware_update_pde = create_flash_pde("ppc64/rtas/" FIRMWARE_UPDATE_NAME, &rtas_flash_operations); if (firmware_update_pde == NULL) { @@ -768,7 +768,7 @@ static int __init rtas_flash_init(void) if (rc != 0) goto cleanup; - validate_pde = create_flash_pde("powerpc/rtas/" VALIDATE_FLASH_NAME, + validate_pde = create_flash_pde("ppc64/rtas/" VALIDATE_FLASH_NAME, &validate_flash_operations); if (validate_pde == NULL) { rc = -ENOMEM; @@ -781,7 +781,7 @@ static int __init rtas_flash_init(void) if (rc != 0) goto cleanup; - manage_pde = create_flash_pde("powerpc/rtas/" MANAGE_FLASH_NAME, + manage_pde = create_flash_pde("ppc64/rtas/" MANAGE_FLASH_NAME, &manage_flash_operations); if (manage_pde == NULL) { rc = -ENOMEM; diff --git a/trunk/arch/powerpc/kernel/setup_64.c b/trunk/arch/powerpc/kernel/setup_64.c index 6568406b2a30..df2c9e932b37 100644 --- a/trunk/arch/powerpc/kernel/setup_64.c +++ b/trunk/arch/powerpc/kernel/setup_64.c @@ -356,6 +356,11 @@ void __init setup_system(void) */ initialize_cache_info(); + /* + * Initialize irq remapping subsystem + */ + irq_early_init(); + #ifdef CONFIG_PPC_RTAS /* * Initialize RTAS if available diff --git a/trunk/arch/powerpc/kernel/smp.c b/trunk/arch/powerpc/kernel/smp.c index 97196eefef3e..9b86a74d2815 100644 --- a/trunk/arch/powerpc/kernel/smp.c +++ b/trunk/arch/powerpc/kernel/smp.c @@ -218,9 +218,6 @@ void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) static void stop_this_cpu(void *dummy) { - /* Remove this CPU */ - set_cpu_online(smp_processor_id(), false); - local_irq_disable(); while (1) ; diff --git a/trunk/arch/powerpc/kernel/sysfs.c b/trunk/arch/powerpc/kernel/sysfs.c index e235e52dc4fe..956ab33fd73f 100644 --- a/trunk/arch/powerpc/kernel/sysfs.c +++ b/trunk/arch/powerpc/kernel/sysfs.c @@ -461,25 +461,6 @@ static void unregister_cpu_online(unsigned int cpu) cacheinfo_cpu_offline(cpu); } - -#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE -ssize_t arch_cpu_probe(const char *buf, size_t count) -{ - if (ppc_md.cpu_probe) - return ppc_md.cpu_probe(buf, count); - - return -EINVAL; -} - -ssize_t arch_cpu_release(const char *buf, size_t count) -{ - if (ppc_md.cpu_release) - return ppc_md.cpu_release(buf, count); - - return -EINVAL; -} -#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ - #endif /* CONFIG_HOTPLUG_CPU */ static int __cpuinit sysfs_cpu_notify(struct notifier_block *self, diff --git a/trunk/arch/powerpc/kernel/time.c b/trunk/arch/powerpc/kernel/time.c index 9ba2cc88591d..674800b242d6 100644 --- a/trunk/arch/powerpc/kernel/time.c +++ b/trunk/arch/powerpc/kernel/time.c @@ -269,7 +269,6 @@ void account_system_vtime(struct task_struct *tsk) per_cpu(cputime_scaled_last_delta, smp_processor_id()) = deltascaled; local_irq_restore(flags); } -EXPORT_SYMBOL_GPL(account_system_vtime); /* * Transfer the user and system times accumulated in the paca diff --git a/trunk/arch/powerpc/kernel/traps.c b/trunk/arch/powerpc/kernel/traps.c index 804f0f30f227..9d1f9354d6ca 100644 --- a/trunk/arch/powerpc/kernel/traps.c +++ b/trunk/arch/powerpc/kernel/traps.c @@ -198,6 +198,28 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) info.si_code = code; info.si_addr = (void __user *) addr; force_sig_info(signr, &info, current); + + /* + * Init gets no signals that it doesn't have a handler for. + * That's all very well, but if it has caused a synchronous + * exception and we ignore the resulting signal, it will just + * generate the same exception over and over again and we get + * nowhere. Better to kill it and let the kernel panic. + */ + if (is_global_init(current)) { + __sighandler_t handler; + + spin_lock_irq(¤t->sighand->siglock); + handler = current->sighand->action[signr-1].sa.sa_handler; + spin_unlock_irq(¤t->sighand->siglock); + if (handler == SIG_DFL) { + /* init has generated a synchronous exception + and it doesn't have a handler for the signal */ + printk(KERN_CRIT "init has generated signal %d " + "but has no handler for it\n", signr); + do_exit(signr); + } + } } #ifdef CONFIG_PPC64 diff --git a/trunk/arch/powerpc/kernel/vector.S b/trunk/arch/powerpc/kernel/vector.S index fe460482fa68..67b6916f0e94 100644 --- a/trunk/arch/powerpc/kernel/vector.S +++ b/trunk/arch/powerpc/kernel/vector.S @@ -58,7 +58,7 @@ _GLOBAL(load_up_altivec) * all 1's */ mfspr r4,SPRN_VRSAVE - cmpwi 0,r4,0 + cmpdi 0,r4,0 bne+ 1f li r4,-1 mtspr SPRN_VRSAVE,r4 diff --git a/trunk/arch/powerpc/kvm/Kconfig b/trunk/arch/powerpc/kvm/Kconfig index 07703f72330e..c29926846613 100644 --- a/trunk/arch/powerpc/kvm/Kconfig +++ b/trunk/arch/powerpc/kvm/Kconfig @@ -21,23 +21,6 @@ config KVM select PREEMPT_NOTIFIERS select ANON_INODES -config KVM_BOOK3S_64_HANDLER - bool - -config KVM_BOOK3S_64 - tristate "KVM support for PowerPC book3s_64 processors" - depends on EXPERIMENTAL && PPC64 - select KVM - select KVM_BOOK3S_64_HANDLER - ---help--- - Support running unmodified book3s_64 and book3s_32 guest kernels - in virtual machines on book3s_64 host processors. - - This module provides access to the hardware capabilities through - a character device node named /dev/kvm. - - If unsure, say N. - config KVM_440 bool "KVM support for PowerPC 440 processors" depends on EXPERIMENTAL && 44x diff --git a/trunk/arch/powerpc/kvm/Makefile b/trunk/arch/powerpc/kvm/Makefile index 56484d652377..37655fe19f2f 100644 --- a/trunk/arch/powerpc/kvm/Makefile +++ b/trunk/arch/powerpc/kvm/Makefile @@ -12,45 +12,26 @@ CFLAGS_44x_tlb.o := -I. CFLAGS_e500_tlb.o := -I. CFLAGS_emulate.o := -I. -common-objs-y += powerpc.o emulate.o +kvm-objs := $(common-objs-y) powerpc.o emulate.o obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o -obj-$(CONFIG_KVM_BOOK3S_64_HANDLER) += book3s_64_exports.o +obj-$(CONFIG_KVM) += kvm.o AFLAGS_booke_interrupts.o := -I$(obj) kvm-440-objs := \ - $(common-objs-y) \ booke.o \ booke_emulate.o \ booke_interrupts.o \ 44x.o \ 44x_tlb.o \ 44x_emulate.o -kvm-objs-$(CONFIG_KVM_440) := $(kvm-440-objs) +obj-$(CONFIG_KVM_440) += kvm-440.o kvm-e500-objs := \ - $(common-objs-y) \ booke.o \ booke_emulate.o \ booke_interrupts.o \ e500.o \ e500_tlb.o \ e500_emulate.o -kvm-objs-$(CONFIG_KVM_E500) := $(kvm-e500-objs) - -kvm-book3s_64-objs := \ - $(common-objs-y) \ - book3s.o \ - book3s_64_emulate.o \ - book3s_64_interrupts.o \ - book3s_64_mmu_host.o \ - book3s_64_mmu.o \ - book3s_32_mmu.o -kvm-objs-$(CONFIG_KVM_BOOK3S_64) := $(kvm-book3s_64-objs) - -kvm-objs := $(kvm-objs-m) $(kvm-objs-y) - -obj-$(CONFIG_KVM_440) += kvm.o -obj-$(CONFIG_KVM_E500) += kvm.o -obj-$(CONFIG_KVM_BOOK3S_64) += kvm.o - +obj-$(CONFIG_KVM_E500) += kvm-e500.o diff --git a/trunk/arch/powerpc/kvm/book3s.c b/trunk/arch/powerpc/kvm/book3s.c deleted file mode 100644 index 3e294bd9b8c6..000000000000 --- a/trunk/arch/powerpc/kvm/book3s.c +++ /dev/null @@ -1,974 +0,0 @@ -/* - * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. - * - * Authors: - * Alexander Graf - * Kevin Wolf - * - * Description: - * This file is derived from arch/powerpc/kvm/44x.c, - * by Hollis Blanchard . - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU - -/* #define EXIT_DEBUG */ -/* #define EXIT_DEBUG_SIMPLE */ - -/* Without AGGRESSIVE_DEC we only fire off a DEC interrupt when DEC turns 0. - * When set, we retrigger a DEC interrupt after that if DEC <= 0. - * PPC32 Linux runs faster without AGGRESSIVE_DEC, PPC64 Linux requires it. */ - -/* #define AGGRESSIVE_DEC */ - -struct kvm_stats_debugfs_item debugfs_entries[] = { - { "exits", VCPU_STAT(sum_exits) }, - { "mmio", VCPU_STAT(mmio_exits) }, - { "sig", VCPU_STAT(signal_exits) }, - { "sysc", VCPU_STAT(syscall_exits) }, - { "inst_emu", VCPU_STAT(emulated_inst_exits) }, - { "dec", VCPU_STAT(dec_exits) }, - { "ext_intr", VCPU_STAT(ext_intr_exits) }, - { "queue_intr", VCPU_STAT(queue_intr) }, - { "halt_wakeup", VCPU_STAT(halt_wakeup) }, - { "pf_storage", VCPU_STAT(pf_storage) }, - { "sp_storage", VCPU_STAT(sp_storage) }, - { "pf_instruc", VCPU_STAT(pf_instruc) }, - { "sp_instruc", VCPU_STAT(sp_instruc) }, - { "ld", VCPU_STAT(ld) }, - { "ld_slow", VCPU_STAT(ld_slow) }, - { "st", VCPU_STAT(st) }, - { "st_slow", VCPU_STAT(st_slow) }, - { NULL } -}; - -void kvmppc_core_load_host_debugstate(struct kvm_vcpu *vcpu) -{ -} - -void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu) -{ -} - -void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) -{ - memcpy(get_paca()->kvm_slb, to_book3s(vcpu)->slb_shadow, sizeof(get_paca()->kvm_slb)); - get_paca()->kvm_slb_max = to_book3s(vcpu)->slb_shadow_max; -} - -void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) -{ - memcpy(to_book3s(vcpu)->slb_shadow, get_paca()->kvm_slb, sizeof(get_paca()->kvm_slb)); - to_book3s(vcpu)->slb_shadow_max = get_paca()->kvm_slb_max; -} - -#if defined(AGGRESSIVE_DEC) || defined(EXIT_DEBUG) -static u32 kvmppc_get_dec(struct kvm_vcpu *vcpu) -{ - u64 jd = mftb() - vcpu->arch.dec_jiffies; - return vcpu->arch.dec - jd; -} -#endif - -void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr) -{ - ulong old_msr = vcpu->arch.msr; - -#ifdef EXIT_DEBUG - printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); -#endif - msr &= to_book3s(vcpu)->msr_mask; - vcpu->arch.msr = msr; - vcpu->arch.shadow_msr = msr | MSR_USER32; - vcpu->arch.shadow_msr &= ( MSR_VEC | MSR_VSX | MSR_FP | MSR_FE0 | - MSR_USER64 | MSR_SE | MSR_BE | MSR_DE | - MSR_FE1); - - if (msr & (MSR_WE|MSR_POW)) { - if (!vcpu->arch.pending_exceptions) { - kvm_vcpu_block(vcpu); - vcpu->stat.halt_wakeup++; - } - } - - if (((vcpu->arch.msr & (MSR_IR|MSR_DR)) != (old_msr & (MSR_IR|MSR_DR))) || - (vcpu->arch.msr & MSR_PR) != (old_msr & MSR_PR)) { - kvmppc_mmu_flush_segments(vcpu); - kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc); - } -} - -void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags) -{ - vcpu->arch.srr0 = vcpu->arch.pc; - vcpu->arch.srr1 = vcpu->arch.msr | flags; - vcpu->arch.pc = to_book3s(vcpu)->hior + vec; - vcpu->arch.mmu.reset_msr(vcpu); -} - -void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec) -{ - unsigned int prio; - - vcpu->stat.queue_intr++; - switch (vec) { - case 0x100: prio = BOOK3S_IRQPRIO_SYSTEM_RESET; break; - case 0x200: prio = BOOK3S_IRQPRIO_MACHINE_CHECK; break; - case 0x300: prio = BOOK3S_IRQPRIO_DATA_STORAGE; break; - case 0x380: prio = BOOK3S_IRQPRIO_DATA_SEGMENT; break; - case 0x400: prio = BOOK3S_IRQPRIO_INST_STORAGE; break; - case 0x480: prio = BOOK3S_IRQPRIO_INST_SEGMENT; break; - case 0x500: prio = BOOK3S_IRQPRIO_EXTERNAL; break; - case 0x600: prio = BOOK3S_IRQPRIO_ALIGNMENT; break; - case 0x700: prio = BOOK3S_IRQPRIO_PROGRAM; break; - case 0x800: prio = BOOK3S_IRQPRIO_FP_UNAVAIL; break; - case 0x900: prio = BOOK3S_IRQPRIO_DECREMENTER; break; - case 0xc00: prio = BOOK3S_IRQPRIO_SYSCALL; break; - case 0xd00: prio = BOOK3S_IRQPRIO_DEBUG; break; - case 0xf20: prio = BOOK3S_IRQPRIO_ALTIVEC; break; - case 0xf40: prio = BOOK3S_IRQPRIO_VSX; break; - default: prio = BOOK3S_IRQPRIO_MAX; break; - } - - set_bit(prio, &vcpu->arch.pending_exceptions); -#ifdef EXIT_DEBUG - printk(KERN_INFO "Queueing interrupt %x\n", vec); -#endif -} - - -void kvmppc_core_queue_program(struct kvm_vcpu *vcpu) -{ - kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_PROGRAM); -} - -void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) -{ - kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DECREMENTER); -} - -int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) -{ - return test_bit(BOOK3S_INTERRUPT_DECREMENTER >> 7, &vcpu->arch.pending_exceptions); -} - -void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, - struct kvm_interrupt *irq) -{ - kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL); -} - -int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) -{ - int deliver = 1; - int vec = 0; - - switch (priority) { - case BOOK3S_IRQPRIO_DECREMENTER: - deliver = vcpu->arch.msr & MSR_EE; - vec = BOOK3S_INTERRUPT_DECREMENTER; - break; - case BOOK3S_IRQPRIO_EXTERNAL: - deliver = vcpu->arch.msr & MSR_EE; - vec = BOOK3S_INTERRUPT_EXTERNAL; - break; - case BOOK3S_IRQPRIO_SYSTEM_RESET: - vec = BOOK3S_INTERRUPT_SYSTEM_RESET; - break; - case BOOK3S_IRQPRIO_MACHINE_CHECK: - vec = BOOK3S_INTERRUPT_MACHINE_CHECK; - break; - case BOOK3S_IRQPRIO_DATA_STORAGE: - vec = BOOK3S_INTERRUPT_DATA_STORAGE; - break; - case BOOK3S_IRQPRIO_INST_STORAGE: - vec = BOOK3S_INTERRUPT_INST_STORAGE; - break; - case BOOK3S_IRQPRIO_DATA_SEGMENT: - vec = BOOK3S_INTERRUPT_DATA_SEGMENT; - break; - case BOOK3S_IRQPRIO_INST_SEGMENT: - vec = BOOK3S_INTERRUPT_INST_SEGMENT; - break; - case BOOK3S_IRQPRIO_ALIGNMENT: - vec = BOOK3S_INTERRUPT_ALIGNMENT; - break; - case BOOK3S_IRQPRIO_PROGRAM: - vec = BOOK3S_INTERRUPT_PROGRAM; - break; - case BOOK3S_IRQPRIO_VSX: - vec = BOOK3S_INTERRUPT_VSX; - break; - case BOOK3S_IRQPRIO_ALTIVEC: - vec = BOOK3S_INTERRUPT_ALTIVEC; - break; - case BOOK3S_IRQPRIO_FP_UNAVAIL: - vec = BOOK3S_INTERRUPT_FP_UNAVAIL; - break; - case BOOK3S_IRQPRIO_SYSCALL: - vec = BOOK3S_INTERRUPT_SYSCALL; - break; - case BOOK3S_IRQPRIO_DEBUG: - vec = BOOK3S_INTERRUPT_TRACE; - break; - case BOOK3S_IRQPRIO_PERFORMANCE_MONITOR: - vec = BOOK3S_INTERRUPT_PERFMON; - break; - default: - deliver = 0; - printk(KERN_ERR "KVM: Unknown interrupt: 0x%x\n", priority); - break; - } - -#if 0 - printk(KERN_INFO "Deliver interrupt 0x%x? %x\n", vec, deliver); -#endif - - if (deliver) - kvmppc_inject_interrupt(vcpu, vec, 0ULL); - - return deliver; -} - -void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu) -{ - unsigned long *pending = &vcpu->arch.pending_exceptions; - unsigned int priority; - - /* XXX be more clever here - no need to mftb() on every entry */ - /* Issue DEC again if it's still active */ -#ifdef AGGRESSIVE_DEC - if (vcpu->arch.msr & MSR_EE) - if (kvmppc_get_dec(vcpu) & 0x80000000) - kvmppc_core_queue_dec(vcpu); -#endif - -#ifdef EXIT_DEBUG - if (vcpu->arch.pending_exceptions) - printk(KERN_EMERG "KVM: Check pending: %lx\n", vcpu->arch.pending_exceptions); -#endif - priority = __ffs(*pending); - while (priority <= (sizeof(unsigned int) * 8)) { - if (kvmppc_book3s_irqprio_deliver(vcpu, priority)) { - clear_bit(priority, &vcpu->arch.pending_exceptions); - break; - } - - priority = find_next_bit(pending, - BITS_PER_BYTE * sizeof(*pending), - priority + 1); - } -} - -void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr) -{ - vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; - vcpu->arch.pvr = pvr; - if ((pvr >= 0x330000) && (pvr < 0x70330000)) { - kvmppc_mmu_book3s_64_init(vcpu); - to_book3s(vcpu)->hior = 0xfff00000; - to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; - } else { - kvmppc_mmu_book3s_32_init(vcpu); - to_book3s(vcpu)->hior = 0; - to_book3s(vcpu)->msr_mask = 0xffffffffULL; - } - - /* If we are in hypervisor level on 970, we can tell the CPU to - * treat DCBZ as 32 bytes store */ - vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; - if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && - !strcmp(cur_cpu_spec->platform, "ppc970")) - vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; - -} - -/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To - * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to - * emulate 32 bytes dcbz length. - * - * The Book3s_64 inventors also realized this case and implemented a special bit - * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. - * - * My approach here is to patch the dcbz instruction on executing pages. - */ -static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) -{ - bool touched = false; - hva_t hpage; - u32 *page; - int i; - - hpage = gfn_to_hva(vcpu->kvm, pte->raddr >> PAGE_SHIFT); - if (kvm_is_error_hva(hpage)) - return; - - hpage |= pte->raddr & ~PAGE_MASK; - hpage &= ~0xFFFULL; - - page = vmalloc(HW_PAGE_SIZE); - - if (copy_from_user(page, (void __user *)hpage, HW_PAGE_SIZE)) - goto out; - - for (i=0; i < HW_PAGE_SIZE / 4; i++) - if ((page[i] & 0xff0007ff) == INS_DCBZ) { - page[i] &= 0xfffffff7; // reserved instruction, so we trap - touched = true; - } - - if (touched) - copy_to_user((void __user *)hpage, page, HW_PAGE_SIZE); - -out: - vfree(page); -} - -static int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, bool data, - struct kvmppc_pte *pte) -{ - int relocated = (vcpu->arch.msr & (data ? MSR_DR : MSR_IR)); - int r; - - if (relocated) { - r = vcpu->arch.mmu.xlate(vcpu, eaddr, pte, data); - } else { - pte->eaddr = eaddr; - pte->raddr = eaddr & 0xffffffff; - pte->vpage = eaddr >> 12; - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - pte->vpage |= VSID_REAL; - case MSR_DR: - pte->vpage |= VSID_REAL_DR; - case MSR_IR: - pte->vpage |= VSID_REAL_IR; - } - pte->may_read = true; - pte->may_write = true; - pte->may_execute = true; - r = 0; - } - - return r; -} - -static hva_t kvmppc_bad_hva(void) -{ - return PAGE_OFFSET; -} - -static hva_t kvmppc_pte_to_hva(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte, - bool read) -{ - hva_t hpage; - - if (read && !pte->may_read) - goto err; - - if (!read && !pte->may_write) - goto err; - - hpage = gfn_to_hva(vcpu->kvm, pte->raddr >> PAGE_SHIFT); - if (kvm_is_error_hva(hpage)) - goto err; - - return hpage | (pte->raddr & ~PAGE_MASK); -err: - return kvmppc_bad_hva(); -} - -int kvmppc_st(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr) -{ - struct kvmppc_pte pte; - hva_t hva = eaddr; - - vcpu->stat.st++; - - if (kvmppc_xlate(vcpu, eaddr, false, &pte)) - goto err; - - hva = kvmppc_pte_to_hva(vcpu, &pte, false); - if (kvm_is_error_hva(hva)) - goto err; - - if (copy_to_user((void __user *)hva, ptr, size)) { - printk(KERN_INFO "kvmppc_st at 0x%lx failed\n", hva); - goto err; - } - - return 0; - -err: - return -ENOENT; -} - -int kvmppc_ld(struct kvm_vcpu *vcpu, ulong eaddr, int size, void *ptr, - bool data) -{ - struct kvmppc_pte pte; - hva_t hva = eaddr; - - vcpu->stat.ld++; - - if (kvmppc_xlate(vcpu, eaddr, data, &pte)) - goto err; - - hva = kvmppc_pte_to_hva(vcpu, &pte, true); - if (kvm_is_error_hva(hva)) - goto err; - - if (copy_from_user(ptr, (void __user *)hva, size)) { - printk(KERN_INFO "kvmppc_ld at 0x%lx failed\n", hva); - goto err; - } - - return 0; - -err: - return -ENOENT; -} - -static int kvmppc_visible_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) -{ - return kvm_is_visible_gfn(vcpu->kvm, gfn); -} - -int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, - ulong eaddr, int vec) -{ - bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); - int r = RESUME_GUEST; - int relocated; - int page_found = 0; - struct kvmppc_pte pte; - bool is_mmio = false; - - if ( vec == BOOK3S_INTERRUPT_DATA_STORAGE ) { - relocated = (vcpu->arch.msr & MSR_DR); - } else { - relocated = (vcpu->arch.msr & MSR_IR); - } - - /* Resolve real address if translation turned on */ - if (relocated) { - page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data); - } else { - pte.may_execute = true; - pte.may_read = true; - pte.may_write = true; - pte.raddr = eaddr & 0xffffffff; - pte.eaddr = eaddr; - pte.vpage = eaddr >> 12; - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - pte.vpage |= VSID_REAL; - case MSR_DR: - pte.vpage |= VSID_REAL_DR; - case MSR_IR: - pte.vpage |= VSID_REAL_IR; - } - } - - if (vcpu->arch.mmu.is_dcbz32(vcpu) && - (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { - /* - * If we do the dcbz hack, we have to NX on every execution, - * so we can patch the executing code. This renders our guest - * NX-less. - */ - pte.may_execute = !data; - } - - if (page_found == -ENOENT) { - /* Page not found in guest PTE entries */ - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr; - vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x00000000f8000000ULL); - kvmppc_book3s_queue_irqprio(vcpu, vec); - } else if (page_found == -EPERM) { - /* Storage protection */ - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr & ~DSISR_NOHPTE; - to_book3s(vcpu)->dsisr |= DSISR_PROTFAULT; - vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x00000000f8000000ULL); - kvmppc_book3s_queue_irqprio(vcpu, vec); - } else if (page_found == -EINVAL) { - /* Page not found in guest SLB */ - vcpu->arch.dear = vcpu->arch.fault_dear; - kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); - } else if (!is_mmio && - kvmppc_visible_gfn(vcpu, pte.raddr >> PAGE_SHIFT)) { - /* The guest's PTE is not mapped yet. Map on the host */ - kvmppc_mmu_map_page(vcpu, &pte); - if (data) - vcpu->stat.sp_storage++; - else if (vcpu->arch.mmu.is_dcbz32(vcpu) && - (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) - kvmppc_patch_dcbz(vcpu, &pte); - } else { - /* MMIO */ - vcpu->stat.mmio_exits++; - vcpu->arch.paddr_accessed = pte.raddr; - r = kvmppc_emulate_mmio(run, vcpu); - if ( r == RESUME_HOST_NV ) - r = RESUME_HOST; - if ( r == RESUME_GUEST_NV ) - r = RESUME_GUEST; - } - - return r; -} - -int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, - unsigned int exit_nr) -{ - int r = RESUME_HOST; - - vcpu->stat.sum_exits++; - - run->exit_reason = KVM_EXIT_UNKNOWN; - run->ready_for_interrupt_injection = 1; -#ifdef EXIT_DEBUG - printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | dec=0x%x | msr=0x%lx\n", - exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear, - kvmppc_get_dec(vcpu), vcpu->arch.msr); -#elif defined (EXIT_DEBUG_SIMPLE) - if ((exit_nr != 0x900) && (exit_nr != 0x500)) - printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | dar=0x%lx | msr=0x%lx\n", - exit_nr, vcpu->arch.pc, vcpu->arch.fault_dear, - vcpu->arch.msr); -#endif - kvm_resched(vcpu); - switch (exit_nr) { - case BOOK3S_INTERRUPT_INST_STORAGE: - vcpu->stat.pf_instruc++; - /* only care about PTEG not found errors, but leave NX alone */ - if (vcpu->arch.shadow_msr & 0x40000000) { - r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.pc, exit_nr); - vcpu->stat.sp_instruc++; - } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && - (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { - /* - * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, - * so we can't use the NX bit inside the guest. Let's cross our fingers, - * that no guest that needs the dcbz hack does NX. - */ - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL); - } else { - vcpu->arch.msr |= (vcpu->arch.shadow_msr & 0x58000000); - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.pc, ~0xFFFULL); - r = RESUME_GUEST; - } - break; - case BOOK3S_INTERRUPT_DATA_STORAGE: - vcpu->stat.pf_storage++; - /* The only case we need to handle is missing shadow PTEs */ - if (vcpu->arch.fault_dsisr & DSISR_NOHPTE) { - r = kvmppc_handle_pagefault(run, vcpu, vcpu->arch.fault_dear, exit_nr); - } else { - vcpu->arch.dear = vcpu->arch.fault_dear; - to_book3s(vcpu)->dsisr = vcpu->arch.fault_dsisr; - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - kvmppc_mmu_pte_flush(vcpu, vcpu->arch.dear, ~0xFFFULL); - r = RESUME_GUEST; - } - break; - case BOOK3S_INTERRUPT_DATA_SEGMENT: - if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.fault_dear) < 0) { - vcpu->arch.dear = vcpu->arch.fault_dear; - kvmppc_book3s_queue_irqprio(vcpu, - BOOK3S_INTERRUPT_DATA_SEGMENT); - } - r = RESUME_GUEST; - break; - case BOOK3S_INTERRUPT_INST_SEGMENT: - if (kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc) < 0) { - kvmppc_book3s_queue_irqprio(vcpu, - BOOK3S_INTERRUPT_INST_SEGMENT); - } - r = RESUME_GUEST; - break; - /* We're good on these - the host merely wanted to get our attention */ - case BOOK3S_INTERRUPT_DECREMENTER: - vcpu->stat.dec_exits++; - r = RESUME_GUEST; - break; - case BOOK3S_INTERRUPT_EXTERNAL: - vcpu->stat.ext_intr_exits++; - r = RESUME_GUEST; - break; - case BOOK3S_INTERRUPT_PROGRAM: - { - enum emulation_result er; - - if (vcpu->arch.msr & MSR_PR) { -#ifdef EXIT_DEBUG - printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", vcpu->arch.pc, vcpu->arch.last_inst); -#endif - if ((vcpu->arch.last_inst & 0xff0007ff) != - (INS_DCBZ & 0xfffffff7)) { - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - r = RESUME_GUEST; - break; - } - } - - vcpu->stat.emulated_inst_exits++; - er = kvmppc_emulate_instruction(run, vcpu); - switch (er) { - case EMULATE_DONE: - r = RESUME_GUEST; - break; - case EMULATE_FAIL: - printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", - __func__, vcpu->arch.pc, vcpu->arch.last_inst); - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - r = RESUME_GUEST; - break; - default: - BUG(); - } - break; - } - case BOOK3S_INTERRUPT_SYSCALL: -#ifdef EXIT_DEBUG - printk(KERN_INFO "Syscall Nr %d\n", (int)vcpu->arch.gpr[0]); -#endif - vcpu->stat.syscall_exits++; - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - r = RESUME_GUEST; - break; - case BOOK3S_INTERRUPT_MACHINE_CHECK: - case BOOK3S_INTERRUPT_FP_UNAVAIL: - case BOOK3S_INTERRUPT_TRACE: - case BOOK3S_INTERRUPT_ALTIVEC: - case BOOK3S_INTERRUPT_VSX: - kvmppc_book3s_queue_irqprio(vcpu, exit_nr); - r = RESUME_GUEST; - break; - default: - /* Ugh - bork here! What did we get? */ - printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", exit_nr, vcpu->arch.pc, vcpu->arch.shadow_msr); - r = RESUME_HOST; - BUG(); - break; - } - - - if (!(r & RESUME_HOST)) { - /* To avoid clobbering exit_reason, only check for signals if - * we aren't already exiting to userspace for some other - * reason. */ - if (signal_pending(current)) { -#ifdef EXIT_DEBUG - printk(KERN_EMERG "KVM: Going back to host\n"); -#endif - vcpu->stat.signal_exits++; - run->exit_reason = KVM_EXIT_INTR; - r = -EINTR; - } else { - /* In case an interrupt came in that was triggered - * from userspace (like DEC), we need to check what - * to inject now! */ - kvmppc_core_deliver_interrupts(vcpu); - } - } - -#ifdef EXIT_DEBUG - printk(KERN_EMERG "KVM exit: vcpu=0x%p pc=0x%lx r=0x%x\n", vcpu, vcpu->arch.pc, r); -#endif - - return r; -} - -int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) -{ - return 0; -} - -int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) -{ - int i; - - regs->pc = vcpu->arch.pc; - regs->cr = vcpu->arch.cr; - regs->ctr = vcpu->arch.ctr; - regs->lr = vcpu->arch.lr; - regs->xer = vcpu->arch.xer; - regs->msr = vcpu->arch.msr; - regs->srr0 = vcpu->arch.srr0; - regs->srr1 = vcpu->arch.srr1; - regs->pid = vcpu->arch.pid; - regs->sprg0 = vcpu->arch.sprg0; - regs->sprg1 = vcpu->arch.sprg1; - regs->sprg2 = vcpu->arch.sprg2; - regs->sprg3 = vcpu->arch.sprg3; - regs->sprg5 = vcpu->arch.sprg4; - regs->sprg6 = vcpu->arch.sprg5; - regs->sprg7 = vcpu->arch.sprg6; - - for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) - regs->gpr[i] = vcpu->arch.gpr[i]; - - return 0; -} - -int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) -{ - int i; - - vcpu->arch.pc = regs->pc; - vcpu->arch.cr = regs->cr; - vcpu->arch.ctr = regs->ctr; - vcpu->arch.lr = regs->lr; - vcpu->arch.xer = regs->xer; - kvmppc_set_msr(vcpu, regs->msr); - vcpu->arch.srr0 = regs->srr0; - vcpu->arch.srr1 = regs->srr1; - vcpu->arch.sprg0 = regs->sprg0; - vcpu->arch.sprg1 = regs->sprg1; - vcpu->arch.sprg2 = regs->sprg2; - vcpu->arch.sprg3 = regs->sprg3; - vcpu->arch.sprg5 = regs->sprg4; - vcpu->arch.sprg6 = regs->sprg5; - vcpu->arch.sprg7 = regs->sprg6; - - for (i = 0; i < ARRAY_SIZE(vcpu->arch.gpr); i++) - vcpu->arch.gpr[i] = regs->gpr[i]; - - return 0; -} - -int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, - struct kvm_sregs *sregs) -{ - struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); - int i; - - sregs->pvr = vcpu->arch.pvr; - - sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; - if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { - for (i = 0; i < 64; i++) { - sregs->u.s.ppc64.slb[i].slbe = vcpu3s->slb[i].orige | i; - sregs->u.s.ppc64.slb[i].slbv = vcpu3s->slb[i].origv; - } - } else { - for (i = 0; i < 16; i++) { - sregs->u.s.ppc32.sr[i] = vcpu3s->sr[i].raw; - sregs->u.s.ppc32.sr[i] = vcpu3s->sr[i].raw; - } - for (i = 0; i < 8; i++) { - sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; - sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; - } - } - return 0; -} - -int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, - struct kvm_sregs *sregs) -{ - struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); - int i; - - kvmppc_set_pvr(vcpu, sregs->pvr); - - vcpu3s->sdr1 = sregs->u.s.sdr1; - if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { - for (i = 0; i < 64; i++) { - vcpu->arch.mmu.slbmte(vcpu, sregs->u.s.ppc64.slb[i].slbv, - sregs->u.s.ppc64.slb[i].slbe); - } - } else { - for (i = 0; i < 16; i++) { - vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); - } - for (i = 0; i < 8; i++) { - kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, - (u32)sregs->u.s.ppc32.ibat[i]); - kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, - (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); - kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, - (u32)sregs->u.s.ppc32.dbat[i]); - kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, - (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); - } - } - - /* Flush the MMU after messing with the segments */ - kvmppc_mmu_pte_flush(vcpu, 0, 0); - return 0; -} - -int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) -{ - return -ENOTSUPP; -} - -int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) -{ - return -ENOTSUPP; -} - -int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, - struct kvm_translation *tr) -{ - return 0; -} - -/* - * Get (and clear) the dirty memory log for a memory slot. - */ -int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, - struct kvm_dirty_log *log) -{ - struct kvm_memory_slot *memslot; - struct kvm_vcpu *vcpu; - ulong ga, ga_end; - int is_dirty = 0; - int r, n; - - down_write(&kvm->slots_lock); - - r = kvm_get_dirty_log(kvm, log, &is_dirty); - if (r) - goto out; - - /* If nothing is dirty, don't bother messing with page tables. */ - if (is_dirty) { - memslot = &kvm->memslots[log->slot]; - - ga = memslot->base_gfn << PAGE_SHIFT; - ga_end = ga + (memslot->npages << PAGE_SHIFT); - - kvm_for_each_vcpu(n, vcpu, kvm) - kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); - - n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; - memset(memslot->dirty_bitmap, 0, n); - } - - r = 0; -out: - up_write(&kvm->slots_lock); - return r; -} - -int kvmppc_core_check_processor_compat(void) -{ - return 0; -} - -struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s; - struct kvm_vcpu *vcpu; - int err; - - vcpu_book3s = (struct kvmppc_vcpu_book3s *)__get_free_pages( GFP_KERNEL | __GFP_ZERO, - get_order(sizeof(struct kvmppc_vcpu_book3s))); - if (!vcpu_book3s) { - err = -ENOMEM; - goto out; - } - - vcpu = &vcpu_book3s->vcpu; - err = kvm_vcpu_init(vcpu, kvm, id); - if (err) - goto free_vcpu; - - vcpu->arch.host_retip = kvm_return_point; - vcpu->arch.host_msr = mfmsr(); - /* default to book3s_64 (970fx) */ - vcpu->arch.pvr = 0x3C0301; - kvmppc_set_pvr(vcpu, vcpu->arch.pvr); - vcpu_book3s->slb_nr = 64; - - /* remember where some real-mode handlers are */ - vcpu->arch.trampoline_lowmem = kvmppc_trampoline_lowmem; - vcpu->arch.trampoline_enter = kvmppc_trampoline_enter; - vcpu->arch.highmem_handler = (ulong)kvmppc_handler_highmem; - - vcpu->arch.shadow_msr = MSR_USER64; - - err = __init_new_context(); - if (err < 0) - goto free_vcpu; - vcpu_book3s->context_id = err; - - vcpu_book3s->vsid_max = ((vcpu_book3s->context_id + 1) << USER_ESID_BITS) - 1; - vcpu_book3s->vsid_first = vcpu_book3s->context_id << USER_ESID_BITS; - vcpu_book3s->vsid_next = vcpu_book3s->vsid_first; - - return vcpu; - -free_vcpu: - free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s))); -out: - return ERR_PTR(err); -} - -void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - - __destroy_context(vcpu_book3s->context_id); - kvm_vcpu_uninit(vcpu); - free_pages((long)vcpu_book3s, get_order(sizeof(struct kvmppc_vcpu_book3s))); -} - -extern int __kvmppc_vcpu_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu); -int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) -{ - int ret; - - /* No need to go into the guest when all we do is going out */ - if (signal_pending(current)) { - kvm_run->exit_reason = KVM_EXIT_INTR; - return -EINTR; - } - - /* XXX we get called with irq disabled - change that! */ - local_irq_enable(); - - ret = __kvmppc_vcpu_entry(kvm_run, vcpu); - - local_irq_disable(); - - return ret; -} - -static int kvmppc_book3s_init(void) -{ - return kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), THIS_MODULE); -} - -static void kvmppc_book3s_exit(void) -{ - kvm_exit(); -} - -module_init(kvmppc_book3s_init); -module_exit(kvmppc_book3s_exit); diff --git a/trunk/arch/powerpc/kvm/book3s_32_mmu.c b/trunk/arch/powerpc/kvm/book3s_32_mmu.c deleted file mode 100644 index faf99f20d993..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_32_mmu.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* #define DEBUG_MMU */ -/* #define DEBUG_MMU_PTE */ -/* #define DEBUG_MMU_PTE_IP 0xfff14c40 */ - -#ifdef DEBUG_MMU -#define dprintk(X...) printk(KERN_INFO X) -#else -#define dprintk(X...) do { } while(0) -#endif - -#ifdef DEBUG_PTE -#define dprintk_pte(X...) printk(KERN_INFO X) -#else -#define dprintk_pte(X...) do { } while(0) -#endif - -#define PTEG_FLAG_ACCESSED 0x00000100 -#define PTEG_FLAG_DIRTY 0x00000080 - -static inline bool check_debug_ip(struct kvm_vcpu *vcpu) -{ -#ifdef DEBUG_MMU_PTE_IP - return vcpu->arch.pc == DEBUG_MMU_PTE_IP; -#else - return true; -#endif -} - -static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr, - struct kvmppc_pte *pte, bool data); - -static struct kvmppc_sr *find_sr(struct kvmppc_vcpu_book3s *vcpu_book3s, gva_t eaddr) -{ - return &vcpu_book3s->sr[(eaddr >> 28) & 0xf]; -} - -static u64 kvmppc_mmu_book3s_32_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr, - bool data) -{ - struct kvmppc_sr *sre = find_sr(to_book3s(vcpu), eaddr); - struct kvmppc_pte pte; - - if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data)) - return pte.vpage; - - return (((u64)eaddr >> 12) & 0xffff) | (((u64)sre->vsid) << 16); -} - -static void kvmppc_mmu_book3s_32_reset_msr(struct kvm_vcpu *vcpu) -{ - kvmppc_set_msr(vcpu, 0); -} - -static hva_t kvmppc_mmu_book3s_32_get_pteg(struct kvmppc_vcpu_book3s *vcpu_book3s, - struct kvmppc_sr *sre, gva_t eaddr, - bool primary) -{ - u32 page, hash, pteg, htabmask; - hva_t r; - - page = (eaddr & 0x0FFFFFFF) >> 12; - htabmask = ((vcpu_book3s->sdr1 & 0x1FF) << 16) | 0xFFC0; - - hash = ((sre->vsid ^ page) << 6); - if (!primary) - hash = ~hash; - hash &= htabmask; - - pteg = (vcpu_book3s->sdr1 & 0xffff0000) | hash; - - dprintk("MMU: pc=0x%lx eaddr=0x%lx sdr1=0x%llx pteg=0x%x vsid=0x%x\n", - vcpu_book3s->vcpu.arch.pc, eaddr, vcpu_book3s->sdr1, pteg, - sre->vsid); - - r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT); - if (kvm_is_error_hva(r)) - return r; - return r | (pteg & ~PAGE_MASK); -} - -static u32 kvmppc_mmu_book3s_32_get_ptem(struct kvmppc_sr *sre, gva_t eaddr, - bool primary) -{ - return ((eaddr & 0x0fffffff) >> 22) | (sre->vsid << 7) | - (primary ? 0 : 0x40) | 0x80000000; -} - -static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr, - struct kvmppc_pte *pte, bool data) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_bat *bat; - int i; - - for (i = 0; i < 8; i++) { - if (data) - bat = &vcpu_book3s->dbat[i]; - else - bat = &vcpu_book3s->ibat[i]; - - if (vcpu->arch.msr & MSR_PR) { - if (!bat->vp) - continue; - } else { - if (!bat->vs) - continue; - } - - if (check_debug_ip(vcpu)) - { - dprintk_pte("%cBAT %02d: 0x%lx - 0x%x (0x%x)\n", - data ? 'd' : 'i', i, eaddr, bat->bepi, - bat->bepi_mask); - } - if ((eaddr & bat->bepi_mask) == bat->bepi) { - pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask); - pte->vpage = (eaddr >> 12) | VSID_BAT; - pte->may_read = bat->pp; - pte->may_write = bat->pp > 1; - pte->may_execute = true; - if (!pte->may_read) { - printk(KERN_INFO "BAT is not readable!\n"); - continue; - } - if (!pte->may_write) { - /* let's treat r/o BATs as not-readable for now */ - dprintk_pte("BAT is read-only!\n"); - continue; - } - - return 0; - } - } - - return -ENOENT; -} - -static int kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr, - struct kvmppc_pte *pte, bool data, - bool primary) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_sr *sre; - hva_t ptegp; - u32 pteg[16]; - u64 ptem = 0; - int i; - int found = 0; - - sre = find_sr(vcpu_book3s, eaddr); - - dprintk_pte("SR 0x%lx: vsid=0x%x, raw=0x%x\n", eaddr >> 28, - sre->vsid, sre->raw); - - pte->vpage = kvmppc_mmu_book3s_32_ea_to_vp(vcpu, eaddr, data); - - ptegp = kvmppc_mmu_book3s_32_get_pteg(vcpu_book3s, sre, eaddr, primary); - if (kvm_is_error_hva(ptegp)) { - printk(KERN_INFO "KVM: Invalid PTEG!\n"); - goto no_page_found; - } - - ptem = kvmppc_mmu_book3s_32_get_ptem(sre, eaddr, primary); - - if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) { - printk(KERN_ERR "KVM: Can't copy data from 0x%lx!\n", ptegp); - goto no_page_found; - } - - for (i=0; i<16; i+=2) { - if (ptem == pteg[i]) { - u8 pp; - - pte->raddr = (pteg[i+1] & ~(0xFFFULL)) | (eaddr & 0xFFF); - pp = pteg[i+1] & 3; - - if ((sre->Kp && (vcpu->arch.msr & MSR_PR)) || - (sre->Ks && !(vcpu->arch.msr & MSR_PR))) - pp |= 4; - - pte->may_write = false; - pte->may_read = false; - pte->may_execute = true; - switch (pp) { - case 0: - case 1: - case 2: - case 6: - pte->may_write = true; - case 3: - case 5: - case 7: - pte->may_read = true; - break; - } - - if ( !pte->may_read ) - continue; - - dprintk_pte("MMU: Found PTE -> %x %x - %x\n", - pteg[i], pteg[i+1], pp); - found = 1; - break; - } - } - - /* Update PTE C and A bits, so the guest's swapper knows we used the - page */ - if (found) { - u32 oldpte = pteg[i+1]; - - if (pte->may_read) - pteg[i+1] |= PTEG_FLAG_ACCESSED; - if (pte->may_write) - pteg[i+1] |= PTEG_FLAG_DIRTY; - else - dprintk_pte("KVM: Mapping read-only page!\n"); - - /* Write back into the PTEG */ - if (pteg[i+1] != oldpte) - copy_to_user((void __user *)ptegp, pteg, sizeof(pteg)); - - return 0; - } - -no_page_found: - - if (check_debug_ip(vcpu)) { - dprintk_pte("KVM MMU: No PTE found (sdr1=0x%llx ptegp=0x%lx)\n", - to_book3s(vcpu)->sdr1, ptegp); - for (i=0; i<16; i+=2) { - dprintk_pte(" %02d: 0x%x - 0x%x (0x%llx)\n", - i, pteg[i], pteg[i+1], ptem); - } - } - - return -ENOENT; -} - -static int kvmppc_mmu_book3s_32_xlate(struct kvm_vcpu *vcpu, gva_t eaddr, - struct kvmppc_pte *pte, bool data) -{ - int r; - - pte->eaddr = eaddr; - r = kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, pte, data); - if (r < 0) - r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte, data, true); - if (r < 0) - r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte, data, false); - - return r; -} - - -static u32 kvmppc_mmu_book3s_32_mfsrin(struct kvm_vcpu *vcpu, u32 srnum) -{ - return to_book3s(vcpu)->sr[srnum].raw; -} - -static void kvmppc_mmu_book3s_32_mtsrin(struct kvm_vcpu *vcpu, u32 srnum, - ulong value) -{ - struct kvmppc_sr *sre; - - sre = &to_book3s(vcpu)->sr[srnum]; - - /* Flush any left-over shadows from the previous SR */ - - /* XXX Not necessary? */ - /* kvmppc_mmu_pte_flush(vcpu, ((u64)sre->vsid) << 28, 0xf0000000ULL); */ - - /* And then put in the new SR */ - sre->raw = value; - sre->vsid = (value & 0x0fffffff); - sre->Ks = (value & 0x40000000) ? true : false; - sre->Kp = (value & 0x20000000) ? true : false; - sre->nx = (value & 0x10000000) ? true : false; - - /* Map the new segment */ - kvmppc_mmu_map_segment(vcpu, srnum << SID_SHIFT); -} - -static void kvmppc_mmu_book3s_32_tlbie(struct kvm_vcpu *vcpu, ulong ea, bool large) -{ - kvmppc_mmu_pte_flush(vcpu, ea, ~0xFFFULL); -} - -static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid, - u64 *vsid) -{ - /* In case we only have one of MSR_IR or MSR_DR set, let's put - that in the real-mode context (and hope RM doesn't access - high memory) */ - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - *vsid = (VSID_REAL >> 16) | esid; - break; - case MSR_IR: - *vsid = (VSID_REAL_IR >> 16) | esid; - break; - case MSR_DR: - *vsid = (VSID_REAL_DR >> 16) | esid; - break; - case MSR_DR|MSR_IR: - { - ulong ea; - ea = esid << SID_SHIFT; - *vsid = find_sr(to_book3s(vcpu), ea)->vsid; - break; - } - default: - BUG(); - } - - return 0; -} - -static bool kvmppc_mmu_book3s_32_is_dcbz32(struct kvm_vcpu *vcpu) -{ - return true; -} - - -void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu) -{ - struct kvmppc_mmu *mmu = &vcpu->arch.mmu; - - mmu->mtsrin = kvmppc_mmu_book3s_32_mtsrin; - mmu->mfsrin = kvmppc_mmu_book3s_32_mfsrin; - mmu->xlate = kvmppc_mmu_book3s_32_xlate; - mmu->reset_msr = kvmppc_mmu_book3s_32_reset_msr; - mmu->tlbie = kvmppc_mmu_book3s_32_tlbie; - mmu->esid_to_vsid = kvmppc_mmu_book3s_32_esid_to_vsid; - mmu->ea_to_vp = kvmppc_mmu_book3s_32_ea_to_vp; - mmu->is_dcbz32 = kvmppc_mmu_book3s_32_is_dcbz32; - - mmu->slbmte = NULL; - mmu->slbmfee = NULL; - mmu->slbmfev = NULL; - mmu->slbie = NULL; - mmu->slbia = NULL; -} diff --git a/trunk/arch/powerpc/kvm/book3s_64_emulate.c b/trunk/arch/powerpc/kvm/book3s_64_emulate.c deleted file mode 100644 index 1027eac6d474..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_emulate.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include -#include -#include - -#define OP_19_XOP_RFID 18 -#define OP_19_XOP_RFI 50 - -#define OP_31_XOP_MFMSR 83 -#define OP_31_XOP_MTMSR 146 -#define OP_31_XOP_MTMSRD 178 -#define OP_31_XOP_MTSRIN 242 -#define OP_31_XOP_TLBIEL 274 -#define OP_31_XOP_TLBIE 306 -#define OP_31_XOP_SLBMTE 402 -#define OP_31_XOP_SLBIE 434 -#define OP_31_XOP_SLBIA 498 -#define OP_31_XOP_MFSRIN 659 -#define OP_31_XOP_SLBMFEV 851 -#define OP_31_XOP_EIOIO 854 -#define OP_31_XOP_SLBMFEE 915 - -/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */ -#define OP_31_XOP_DCBZ 1010 - -int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, - unsigned int inst, int *advance) -{ - int emulated = EMULATE_DONE; - - switch (get_op(inst)) { - case 19: - switch (get_xop(inst)) { - case OP_19_XOP_RFID: - case OP_19_XOP_RFI: - vcpu->arch.pc = vcpu->arch.srr0; - kvmppc_set_msr(vcpu, vcpu->arch.srr1); - *advance = 0; - break; - - default: - emulated = EMULATE_FAIL; - break; - } - break; - case 31: - switch (get_xop(inst)) { - case OP_31_XOP_MFMSR: - vcpu->arch.gpr[get_rt(inst)] = vcpu->arch.msr; - break; - case OP_31_XOP_MTMSRD: - { - ulong rs = vcpu->arch.gpr[get_rs(inst)]; - if (inst & 0x10000) { - vcpu->arch.msr &= ~(MSR_RI | MSR_EE); - vcpu->arch.msr |= rs & (MSR_RI | MSR_EE); - } else - kvmppc_set_msr(vcpu, rs); - break; - } - case OP_31_XOP_MTMSR: - kvmppc_set_msr(vcpu, vcpu->arch.gpr[get_rs(inst)]); - break; - case OP_31_XOP_MFSRIN: - { - int srnum; - - srnum = (vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf; - if (vcpu->arch.mmu.mfsrin) { - u32 sr; - sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); - vcpu->arch.gpr[get_rt(inst)] = sr; - } - break; - } - case OP_31_XOP_MTSRIN: - vcpu->arch.mmu.mtsrin(vcpu, - (vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf, - vcpu->arch.gpr[get_rs(inst)]); - break; - case OP_31_XOP_TLBIE: - case OP_31_XOP_TLBIEL: - { - bool large = (inst & 0x00200000) ? true : false; - ulong addr = vcpu->arch.gpr[get_rb(inst)]; - vcpu->arch.mmu.tlbie(vcpu, addr, large); - break; - } - case OP_31_XOP_EIOIO: - break; - case OP_31_XOP_SLBMTE: - if (!vcpu->arch.mmu.slbmte) - return EMULATE_FAIL; - - vcpu->arch.mmu.slbmte(vcpu, vcpu->arch.gpr[get_rs(inst)], - vcpu->arch.gpr[get_rb(inst)]); - break; - case OP_31_XOP_SLBIE: - if (!vcpu->arch.mmu.slbie) - return EMULATE_FAIL; - - vcpu->arch.mmu.slbie(vcpu, vcpu->arch.gpr[get_rb(inst)]); - break; - case OP_31_XOP_SLBIA: - if (!vcpu->arch.mmu.slbia) - return EMULATE_FAIL; - - vcpu->arch.mmu.slbia(vcpu); - break; - case OP_31_XOP_SLBMFEE: - if (!vcpu->arch.mmu.slbmfee) { - emulated = EMULATE_FAIL; - } else { - ulong t, rb; - - rb = vcpu->arch.gpr[get_rb(inst)]; - t = vcpu->arch.mmu.slbmfee(vcpu, rb); - vcpu->arch.gpr[get_rt(inst)] = t; - } - break; - case OP_31_XOP_SLBMFEV: - if (!vcpu->arch.mmu.slbmfev) { - emulated = EMULATE_FAIL; - } else { - ulong t, rb; - - rb = vcpu->arch.gpr[get_rb(inst)]; - t = vcpu->arch.mmu.slbmfev(vcpu, rb); - vcpu->arch.gpr[get_rt(inst)] = t; - } - break; - case OP_31_XOP_DCBZ: - { - ulong rb = vcpu->arch.gpr[get_rb(inst)]; - ulong ra = 0; - ulong addr; - u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; - - if (get_ra(inst)) - ra = vcpu->arch.gpr[get_ra(inst)]; - - addr = (ra + rb) & ~31ULL; - if (!(vcpu->arch.msr & MSR_SF)) - addr &= 0xffffffff; - - if (kvmppc_st(vcpu, addr, 32, zeros)) { - vcpu->arch.dear = addr; - vcpu->arch.fault_dear = addr; - to_book3s(vcpu)->dsisr = DSISR_PROTFAULT | - DSISR_ISSTORE; - kvmppc_book3s_queue_irqprio(vcpu, - BOOK3S_INTERRUPT_DATA_STORAGE); - kvmppc_mmu_pte_flush(vcpu, addr, ~0xFFFULL); - } - - break; - } - default: - emulated = EMULATE_FAIL; - } - break; - default: - emulated = EMULATE_FAIL; - } - - return emulated; -} - -void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper, - u32 val) -{ - if (upper) { - /* Upper BAT */ - u32 bl = (val >> 2) & 0x7ff; - bat->bepi_mask = (~bl << 17); - bat->bepi = val & 0xfffe0000; - bat->vs = (val & 2) ? 1 : 0; - bat->vp = (val & 1) ? 1 : 0; - bat->raw = (bat->raw & 0xffffffff00000000ULL) | val; - } else { - /* Lower BAT */ - bat->brpn = val & 0xfffe0000; - bat->wimg = (val >> 3) & 0xf; - bat->pp = val & 3; - bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32); - } -} - -static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u32 val) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_bat *bat; - - switch (sprn) { - case SPRN_IBAT0U ... SPRN_IBAT3L: - bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2]; - break; - case SPRN_IBAT4U ... SPRN_IBAT7L: - bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT4U) / 2]; - break; - case SPRN_DBAT0U ... SPRN_DBAT3L: - bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2]; - break; - case SPRN_DBAT4U ... SPRN_DBAT7L: - bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT4U) / 2]; - break; - default: - BUG(); - } - - kvmppc_set_bat(vcpu, bat, !(sprn % 2), val); -} - -int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) -{ - int emulated = EMULATE_DONE; - - switch (sprn) { - case SPRN_SDR1: - to_book3s(vcpu)->sdr1 = vcpu->arch.gpr[rs]; - break; - case SPRN_DSISR: - to_book3s(vcpu)->dsisr = vcpu->arch.gpr[rs]; - break; - case SPRN_DAR: - vcpu->arch.dear = vcpu->arch.gpr[rs]; - break; - case SPRN_HIOR: - to_book3s(vcpu)->hior = vcpu->arch.gpr[rs]; - break; - case SPRN_IBAT0U ... SPRN_IBAT3L: - case SPRN_IBAT4U ... SPRN_IBAT7L: - case SPRN_DBAT0U ... SPRN_DBAT3L: - case SPRN_DBAT4U ... SPRN_DBAT7L: - kvmppc_write_bat(vcpu, sprn, (u32)vcpu->arch.gpr[rs]); - /* BAT writes happen so rarely that we're ok to flush - * everything here */ - kvmppc_mmu_pte_flush(vcpu, 0, 0); - break; - case SPRN_HID0: - to_book3s(vcpu)->hid[0] = vcpu->arch.gpr[rs]; - break; - case SPRN_HID1: - to_book3s(vcpu)->hid[1] = vcpu->arch.gpr[rs]; - break; - case SPRN_HID2: - to_book3s(vcpu)->hid[2] = vcpu->arch.gpr[rs]; - break; - case SPRN_HID4: - to_book3s(vcpu)->hid[4] = vcpu->arch.gpr[rs]; - break; - case SPRN_HID5: - to_book3s(vcpu)->hid[5] = vcpu->arch.gpr[rs]; - /* guest HID5 set can change is_dcbz32 */ - if (vcpu->arch.mmu.is_dcbz32(vcpu) && - (mfmsr() & MSR_HV)) - vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; - break; - case SPRN_ICTC: - case SPRN_THRM1: - case SPRN_THRM2: - case SPRN_THRM3: - case SPRN_CTRLF: - case SPRN_CTRLT: - break; - default: - printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn); -#ifndef DEBUG_SPR - emulated = EMULATE_FAIL; -#endif - break; - } - - return emulated; -} - -int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) -{ - int emulated = EMULATE_DONE; - - switch (sprn) { - case SPRN_SDR1: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->sdr1; - break; - case SPRN_DSISR: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->dsisr; - break; - case SPRN_DAR: - vcpu->arch.gpr[rt] = vcpu->arch.dear; - break; - case SPRN_HIOR: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hior; - break; - case SPRN_HID0: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[0]; - break; - case SPRN_HID1: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[1]; - break; - case SPRN_HID2: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[2]; - break; - case SPRN_HID4: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[4]; - break; - case SPRN_HID5: - vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[5]; - break; - case SPRN_THRM1: - case SPRN_THRM2: - case SPRN_THRM3: - case SPRN_CTRLF: - case SPRN_CTRLT: - vcpu->arch.gpr[rt] = 0; - break; - default: - printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn); -#ifndef DEBUG_SPR - emulated = EMULATE_FAIL; -#endif - break; - } - - return emulated; -} - diff --git a/trunk/arch/powerpc/kvm/book3s_64_exports.c b/trunk/arch/powerpc/kvm/book3s_64_exports.c deleted file mode 100644 index 5b2db38ed86c..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_exports.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include - -EXPORT_SYMBOL_GPL(kvmppc_trampoline_enter); -EXPORT_SYMBOL_GPL(kvmppc_trampoline_lowmem); diff --git a/trunk/arch/powerpc/kvm/book3s_64_interrupts.S b/trunk/arch/powerpc/kvm/book3s_64_interrupts.S deleted file mode 100644 index 7b55d8094c8b..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_interrupts.S +++ /dev/null @@ -1,392 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include -#include -#include -#include -#include - -#define KVMPPC_HANDLE_EXIT .kvmppc_handle_exit -#define ULONG_SIZE 8 -#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) - -.macro mfpaca tmp_reg, src_reg, offset, vcpu_reg - ld \tmp_reg, (PACA_EXMC+\offset)(r13) - std \tmp_reg, VCPU_GPR(\src_reg)(\vcpu_reg) -.endm - -.macro DISABLE_INTERRUPTS - mfmsr r0 - rldicl r0,r0,48,1 - rotldi r0,r0,16 - mtmsrd r0,1 -.endm - -/***************************************************************************** - * * - * Guest entry / exit code that is in kernel module memory (highmem) * - * * - ****************************************************************************/ - -/* Registers: - * r3: kvm_run pointer - * r4: vcpu pointer - */ -_GLOBAL(__kvmppc_vcpu_entry) - -kvm_start_entry: - /* Write correct stack frame */ - mflr r0 - std r0,16(r1) - - /* Save host state to the stack */ - stdu r1, -SWITCH_FRAME_SIZE(r1) - - /* Save r3 (kvm_run) and r4 (vcpu) */ - SAVE_2GPRS(3, r1) - - /* Save non-volatile registers (r14 - r31) */ - SAVE_NVGPRS(r1) - - /* Save LR */ - mflr r14 - std r14, _LINK(r1) - -/* XXX optimize non-volatile loading away */ -kvm_start_lightweight: - - DISABLE_INTERRUPTS - - /* Save R1/R2 in the PACA */ - std r1, PACAR1(r13) - std r2, (PACA_EXMC+EX_SRR0)(r13) - ld r3, VCPU_HIGHMEM_HANDLER(r4) - std r3, PACASAVEDMSR(r13) - - /* Load non-volatile guest state from the vcpu */ - ld r14, VCPU_GPR(r14)(r4) - ld r15, VCPU_GPR(r15)(r4) - ld r16, VCPU_GPR(r16)(r4) - ld r17, VCPU_GPR(r17)(r4) - ld r18, VCPU_GPR(r18)(r4) - ld r19, VCPU_GPR(r19)(r4) - ld r20, VCPU_GPR(r20)(r4) - ld r21, VCPU_GPR(r21)(r4) - ld r22, VCPU_GPR(r22)(r4) - ld r23, VCPU_GPR(r23)(r4) - ld r24, VCPU_GPR(r24)(r4) - ld r25, VCPU_GPR(r25)(r4) - ld r26, VCPU_GPR(r26)(r4) - ld r27, VCPU_GPR(r27)(r4) - ld r28, VCPU_GPR(r28)(r4) - ld r29, VCPU_GPR(r29)(r4) - ld r30, VCPU_GPR(r30)(r4) - ld r31, VCPU_GPR(r31)(r4) - - ld r9, VCPU_PC(r4) /* r9 = vcpu->arch.pc */ - ld r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */ - - ld r3, VCPU_TRAMPOLINE_ENTER(r4) - mtsrr0 r3 - - LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)) - mtsrr1 r3 - - /* Load guest state in the respective registers */ - lwz r3, VCPU_CR(r4) /* r3 = vcpu->arch.cr */ - stw r3, (PACA_EXMC + EX_CCR)(r13) - - ld r3, VCPU_CTR(r4) /* r3 = vcpu->arch.ctr */ - mtctr r3 /* CTR = r3 */ - - ld r3, VCPU_LR(r4) /* r3 = vcpu->arch.lr */ - mtlr r3 /* LR = r3 */ - - ld r3, VCPU_XER(r4) /* r3 = vcpu->arch.xer */ - std r3, (PACA_EXMC + EX_R3)(r13) - - /* Some guests may need to have dcbz set to 32 byte length. - * - * Usually we ensure that by patching the guest's instructions - * to trap on dcbz and emulate it in the hypervisor. - * - * If we can, we should tell the CPU to use 32 byte dcbz though, - * because that's a lot faster. - */ - - ld r3, VCPU_HFLAGS(r4) - rldicl. r3, r3, 0, 63 /* CR = ((r3 & 1) == 0) */ - beq no_dcbz32_on - - mfspr r3,SPRN_HID5 - ori r3, r3, 0x80 /* XXX HID5_dcbz32 = 0x80 */ - mtspr SPRN_HID5,r3 - -no_dcbz32_on: - /* Load guest GPRs */ - - ld r3, VCPU_GPR(r9)(r4) - std r3, (PACA_EXMC + EX_R9)(r13) - ld r3, VCPU_GPR(r10)(r4) - std r3, (PACA_EXMC + EX_R10)(r13) - ld r3, VCPU_GPR(r11)(r4) - std r3, (PACA_EXMC + EX_R11)(r13) - ld r3, VCPU_GPR(r12)(r4) - std r3, (PACA_EXMC + EX_R12)(r13) - ld r3, VCPU_GPR(r13)(r4) - std r3, (PACA_EXMC + EX_R13)(r13) - - ld r0, VCPU_GPR(r0)(r4) - ld r1, VCPU_GPR(r1)(r4) - ld r2, VCPU_GPR(r2)(r4) - ld r3, VCPU_GPR(r3)(r4) - ld r5, VCPU_GPR(r5)(r4) - ld r6, VCPU_GPR(r6)(r4) - ld r7, VCPU_GPR(r7)(r4) - ld r8, VCPU_GPR(r8)(r4) - ld r4, VCPU_GPR(r4)(r4) - - /* This sets the Magic value for the trampoline */ - - li r11, 1 - stb r11, PACA_KVM_IN_GUEST(r13) - - /* Jump to SLB patching handlder and into our guest */ - RFI - -/* - * This is the handler in module memory. It gets jumped at from the - * lowmem trampoline code, so it's basically the guest exit code. - * - */ - -.global kvmppc_handler_highmem -kvmppc_handler_highmem: - - /* - * Register usage at this point: - * - * R00 = guest R13 - * R01 = host R1 - * R02 = host R2 - * R10 = guest PC - * R11 = guest MSR - * R12 = exit handler id - * R13 = PACA - * PACA.exmc.R9 = guest R1 - * PACA.exmc.R10 = guest R10 - * PACA.exmc.R11 = guest R11 - * PACA.exmc.R12 = guest R12 - * PACA.exmc.R13 = guest R2 - * PACA.exmc.DAR = guest DAR - * PACA.exmc.DSISR = guest DSISR - * PACA.exmc.LR = guest instruction - * PACA.exmc.CCR = guest CR - * PACA.exmc.SRR0 = guest R0 - * - */ - - std r3, (PACA_EXMC+EX_R3)(r13) - - /* save the exit id in R3 */ - mr r3, r12 - - /* R12 = vcpu */ - ld r12, GPR4(r1) - - /* Now save the guest state */ - - std r0, VCPU_GPR(r13)(r12) - std r4, VCPU_GPR(r4)(r12) - std r5, VCPU_GPR(r5)(r12) - std r6, VCPU_GPR(r6)(r12) - std r7, VCPU_GPR(r7)(r12) - std r8, VCPU_GPR(r8)(r12) - std r9, VCPU_GPR(r9)(r12) - - /* get registers from PACA */ - mfpaca r5, r0, EX_SRR0, r12 - mfpaca r5, r3, EX_R3, r12 - mfpaca r5, r1, EX_R9, r12 - mfpaca r5, r10, EX_R10, r12 - mfpaca r5, r11, EX_R11, r12 - mfpaca r5, r12, EX_R12, r12 - mfpaca r5, r2, EX_R13, r12 - - lwz r5, (PACA_EXMC+EX_LR)(r13) - stw r5, VCPU_LAST_INST(r12) - - lwz r5, (PACA_EXMC+EX_CCR)(r13) - stw r5, VCPU_CR(r12) - - ld r5, VCPU_HFLAGS(r12) - rldicl. r5, r5, 0, 63 /* CR = ((r5 & 1) == 0) */ - beq no_dcbz32_off - - mfspr r5,SPRN_HID5 - rldimi r5,r5,6,56 - mtspr SPRN_HID5,r5 - -no_dcbz32_off: - - /* XXX maybe skip on lightweight? */ - std r14, VCPU_GPR(r14)(r12) - std r15, VCPU_GPR(r15)(r12) - std r16, VCPU_GPR(r16)(r12) - std r17, VCPU_GPR(r17)(r12) - std r18, VCPU_GPR(r18)(r12) - std r19, VCPU_GPR(r19)(r12) - std r20, VCPU_GPR(r20)(r12) - std r21, VCPU_GPR(r21)(r12) - std r22, VCPU_GPR(r22)(r12) - std r23, VCPU_GPR(r23)(r12) - std r24, VCPU_GPR(r24)(r12) - std r25, VCPU_GPR(r25)(r12) - std r26, VCPU_GPR(r26)(r12) - std r27, VCPU_GPR(r27)(r12) - std r28, VCPU_GPR(r28)(r12) - std r29, VCPU_GPR(r29)(r12) - std r30, VCPU_GPR(r30)(r12) - std r31, VCPU_GPR(r31)(r12) - - /* Restore non-volatile host registers (r14 - r31) */ - REST_NVGPRS(r1) - - /* Save guest PC (R10) */ - std r10, VCPU_PC(r12) - - /* Save guest msr (R11) */ - std r11, VCPU_SHADOW_MSR(r12) - - /* Save guest CTR (in R12) */ - mfctr r5 - std r5, VCPU_CTR(r12) - - /* Save guest LR */ - mflr r5 - std r5, VCPU_LR(r12) - - /* Save guest XER */ - mfxer r5 - std r5, VCPU_XER(r12) - - /* Save guest DAR */ - ld r5, (PACA_EXMC+EX_DAR)(r13) - std r5, VCPU_FAULT_DEAR(r12) - - /* Save guest DSISR */ - lwz r5, (PACA_EXMC+EX_DSISR)(r13) - std r5, VCPU_FAULT_DSISR(r12) - - /* Restore host msr -> SRR1 */ - ld r7, VCPU_HOST_MSR(r12) - mtsrr1 r7 - - /* Restore host IP -> SRR0 */ - ld r6, VCPU_HOST_RETIP(r12) - mtsrr0 r6 - - /* - * For some interrupts, we need to call the real Linux - * handler, so it can do work for us. This has to happen - * as if the interrupt arrived from the kernel though, - * so let's fake it here where most state is restored. - * - * Call Linux for hardware interrupts/decrementer - * r3 = address of interrupt handler (exit reason) - */ - - cmpwi r3, BOOK3S_INTERRUPT_EXTERNAL - beq call_linux_handler - cmpwi r3, BOOK3S_INTERRUPT_DECREMENTER - beq call_linux_handler - - /* Back to Interruptable Mode! (goto kvm_return_point) */ - RFI - -call_linux_handler: - - /* - * If we land here we need to jump back to the handler we - * came from. - * - * We have a page that we can access from real mode, so let's - * jump back to that and use it as a trampoline to get back into the - * interrupt handler! - * - * R3 still contains the exit code, - * R6 VCPU_HOST_RETIP and - * R7 VCPU_HOST_MSR - */ - - mtlr r3 - - ld r5, VCPU_TRAMPOLINE_LOWMEM(r12) - mtsrr0 r5 - LOAD_REG_IMMEDIATE(r5, MSR_KERNEL & ~(MSR_IR | MSR_DR)) - mtsrr1 r5 - - RFI - -.global kvm_return_point -kvm_return_point: - - /* Jump back to lightweight entry if we're supposed to */ - /* go back into the guest */ - mr r5, r3 - /* Restore r3 (kvm_run) and r4 (vcpu) */ - REST_2GPRS(3, r1) - bl KVMPPC_HANDLE_EXIT - -#if 0 /* XXX get lightweight exits back */ - cmpwi r3, RESUME_GUEST - bne kvm_exit_heavyweight - - /* put VCPU and KVM_RUN back into place and roll again! */ - REST_2GPRS(3, r1) - b kvm_start_lightweight - -kvm_exit_heavyweight: - /* Restore non-volatile host registers */ - ld r14, _LINK(r1) - mtlr r14 - REST_NVGPRS(r1) - - addi r1, r1, SWITCH_FRAME_SIZE -#else - ld r4, _LINK(r1) - mtlr r4 - - cmpwi r3, RESUME_GUEST - bne kvm_exit_heavyweight - - REST_2GPRS(3, r1) - - addi r1, r1, SWITCH_FRAME_SIZE - - b kvm_start_entry - -kvm_exit_heavyweight: - - addi r1, r1, SWITCH_FRAME_SIZE -#endif - - blr diff --git a/trunk/arch/powerpc/kvm/book3s_64_mmu.c b/trunk/arch/powerpc/kvm/book3s_64_mmu.c deleted file mode 100644 index 5598f88f142e..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_mmu.c +++ /dev/null @@ -1,478 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* #define DEBUG_MMU */ - -#ifdef DEBUG_MMU -#define dprintk(X...) printk(KERN_INFO X) -#else -#define dprintk(X...) do { } while(0) -#endif - -static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu) -{ - kvmppc_set_msr(vcpu, MSR_SF); -} - -static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe( - struct kvmppc_vcpu_book3s *vcpu_book3s, - gva_t eaddr) -{ - int i; - u64 esid = GET_ESID(eaddr); - u64 esid_1t = GET_ESID_1T(eaddr); - - for (i = 0; i < vcpu_book3s->slb_nr; i++) { - u64 cmp_esid = esid; - - if (!vcpu_book3s->slb[i].valid) - continue; - - if (vcpu_book3s->slb[i].large) - cmp_esid = esid_1t; - - if (vcpu_book3s->slb[i].esid == cmp_esid) - return &vcpu_book3s->slb[i]; - } - - dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n", - eaddr, esid, esid_1t); - for (i = 0; i < vcpu_book3s->slb_nr; i++) { - if (vcpu_book3s->slb[i].vsid) - dprintk(" %d: %c%c %llx %llx\n", i, - vcpu_book3s->slb[i].valid ? 'v' : ' ', - vcpu_book3s->slb[i].large ? 'l' : ' ', - vcpu_book3s->slb[i].esid, - vcpu_book3s->slb[i].vsid); - } - - return NULL; -} - -static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr, - bool data) -{ - struct kvmppc_slb *slb; - - slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), eaddr); - if (!slb) - return 0; - - if (slb->large) - return (((u64)eaddr >> 12) & 0xfffffff) | - (((u64)slb->vsid) << 28); - - return (((u64)eaddr >> 12) & 0xffff) | (((u64)slb->vsid) << 16); -} - -static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe) -{ - return slbe->large ? 24 : 12; -} - -static u32 kvmppc_mmu_book3s_64_get_page(struct kvmppc_slb *slbe, gva_t eaddr) -{ - int p = kvmppc_mmu_book3s_64_get_pagesize(slbe); - return ((eaddr & 0xfffffff) >> p); -} - -static hva_t kvmppc_mmu_book3s_64_get_pteg( - struct kvmppc_vcpu_book3s *vcpu_book3s, - struct kvmppc_slb *slbe, gva_t eaddr, - bool second) -{ - u64 hash, pteg, htabsize; - u32 page; - hva_t r; - - page = kvmppc_mmu_book3s_64_get_page(slbe, eaddr); - htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1); - - hash = slbe->vsid ^ page; - if (second) - hash = ~hash; - hash &= ((1ULL << 39ULL) - 1ULL); - hash &= htabsize; - hash <<= 7ULL; - - pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL; - pteg |= hash; - - dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n", - page, vcpu_book3s->sdr1, pteg, slbe->vsid); - - r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT); - if (kvm_is_error_hva(r)) - return r; - return r | (pteg & ~PAGE_MASK); -} - -static u64 kvmppc_mmu_book3s_64_get_avpn(struct kvmppc_slb *slbe, gva_t eaddr) -{ - int p = kvmppc_mmu_book3s_64_get_pagesize(slbe); - u64 avpn; - - avpn = kvmppc_mmu_book3s_64_get_page(slbe, eaddr); - avpn |= slbe->vsid << (28 - p); - - if (p < 24) - avpn >>= ((80 - p) - 56) - 8; - else - avpn <<= 8; - - return avpn; -} - -static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr, - struct kvmppc_pte *gpte, bool data) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_slb *slbe; - hva_t ptegp; - u64 pteg[16]; - u64 avpn = 0; - int i; - u8 key = 0; - bool found = false; - bool perm_err = false; - int second = 0; - - slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu_book3s, eaddr); - if (!slbe) - goto no_seg_found; - -do_second: - ptegp = kvmppc_mmu_book3s_64_get_pteg(vcpu_book3s, slbe, eaddr, second); - if (kvm_is_error_hva(ptegp)) - goto no_page_found; - - avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr); - - if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) { - printk(KERN_ERR "KVM can't copy data from 0x%lx!\n", ptegp); - goto no_page_found; - } - - if ((vcpu->arch.msr & MSR_PR) && slbe->Kp) - key = 4; - else if (!(vcpu->arch.msr & MSR_PR) && slbe->Ks) - key = 4; - - for (i=0; i<16; i+=2) { - u64 v = pteg[i]; - u64 r = pteg[i+1]; - - /* Valid check */ - if (!(v & HPTE_V_VALID)) - continue; - /* Hash check */ - if ((v & HPTE_V_SECONDARY) != second) - continue; - - /* AVPN compare */ - if (HPTE_V_AVPN_VAL(avpn) == HPTE_V_AVPN_VAL(v)) { - u8 pp = (r & HPTE_R_PP) | key; - int eaddr_mask = 0xFFF; - - gpte->eaddr = eaddr; - gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, - eaddr, - data); - if (slbe->large) - eaddr_mask = 0xFFFFFF; - gpte->raddr = (r & HPTE_R_RPN) | (eaddr & eaddr_mask); - gpte->may_execute = ((r & HPTE_R_N) ? false : true); - gpte->may_read = false; - gpte->may_write = false; - - switch (pp) { - case 0: - case 1: - case 2: - case 6: - gpte->may_write = true; - /* fall through */ - case 3: - case 5: - case 7: - gpte->may_read = true; - break; - } - - if (!gpte->may_read) { - perm_err = true; - continue; - } - - dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx " - "-> 0x%llx\n", - eaddr, avpn, gpte->vpage, gpte->raddr); - found = true; - break; - } - } - - /* Update PTE R and C bits, so the guest's swapper knows we used the - * page */ - if (found) { - u32 oldr = pteg[i+1]; - - if (gpte->may_read) { - /* Set the accessed flag */ - pteg[i+1] |= HPTE_R_R; - } - if (gpte->may_write) { - /* Set the dirty flag */ - pteg[i+1] |= HPTE_R_C; - } else { - dprintk("KVM: Mapping read-only page!\n"); - } - - /* Write back into the PTEG */ - if (pteg[i+1] != oldr) - copy_to_user((void __user *)ptegp, pteg, sizeof(pteg)); - - return 0; - } else { - dprintk("KVM MMU: No PTE found (ea=0x%lx sdr1=0x%llx " - "ptegp=0x%lx)\n", - eaddr, to_book3s(vcpu)->sdr1, ptegp); - for (i = 0; i < 16; i += 2) - dprintk(" %02d: 0x%llx - 0x%llx (0x%llx)\n", - i, pteg[i], pteg[i+1], avpn); - - if (!second) { - second = HPTE_V_SECONDARY; - goto do_second; - } - } - - -no_page_found: - - - if (perm_err) - return -EPERM; - - return -ENOENT; - -no_seg_found: - - dprintk("KVM MMU: Trigger segment fault\n"); - return -EINVAL; -} - -static void kvmppc_mmu_book3s_64_slbmte(struct kvm_vcpu *vcpu, u64 rs, u64 rb) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s; - u64 esid, esid_1t; - int slb_nr; - struct kvmppc_slb *slbe; - - dprintk("KVM MMU: slbmte(0x%llx, 0x%llx)\n", rs, rb); - - vcpu_book3s = to_book3s(vcpu); - - esid = GET_ESID(rb); - esid_1t = GET_ESID_1T(rb); - slb_nr = rb & 0xfff; - - if (slb_nr > vcpu_book3s->slb_nr) - return; - - slbe = &vcpu_book3s->slb[slb_nr]; - - slbe->large = (rs & SLB_VSID_L) ? 1 : 0; - slbe->esid = slbe->large ? esid_1t : esid; - slbe->vsid = rs >> 12; - slbe->valid = (rb & SLB_ESID_V) ? 1 : 0; - slbe->Ks = (rs & SLB_VSID_KS) ? 1 : 0; - slbe->Kp = (rs & SLB_VSID_KP) ? 1 : 0; - slbe->nx = (rs & SLB_VSID_N) ? 1 : 0; - slbe->class = (rs & SLB_VSID_C) ? 1 : 0; - - slbe->orige = rb & (ESID_MASK | SLB_ESID_V); - slbe->origv = rs; - - /* Map the new segment */ - kvmppc_mmu_map_segment(vcpu, esid << SID_SHIFT); -} - -static u64 kvmppc_mmu_book3s_64_slbmfee(struct kvm_vcpu *vcpu, u64 slb_nr) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_slb *slbe; - - if (slb_nr > vcpu_book3s->slb_nr) - return 0; - - slbe = &vcpu_book3s->slb[slb_nr]; - - return slbe->orige; -} - -static u64 kvmppc_mmu_book3s_64_slbmfev(struct kvm_vcpu *vcpu, u64 slb_nr) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_slb *slbe; - - if (slb_nr > vcpu_book3s->slb_nr) - return 0; - - slbe = &vcpu_book3s->slb[slb_nr]; - - return slbe->origv; -} - -static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - struct kvmppc_slb *slbe; - - dprintk("KVM MMU: slbie(0x%llx)\n", ea); - - slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu_book3s, ea); - - if (!slbe) - return; - - dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid); - - slbe->valid = false; - - kvmppc_mmu_map_segment(vcpu, ea); -} - -static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu) -{ - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - int i; - - dprintk("KVM MMU: slbia()\n"); - - for (i = 1; i < vcpu_book3s->slb_nr; i++) - vcpu_book3s->slb[i].valid = false; - - if (vcpu->arch.msr & MSR_IR) { - kvmppc_mmu_flush_segments(vcpu); - kvmppc_mmu_map_segment(vcpu, vcpu->arch.pc); - } -} - -static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum, - ulong value) -{ - u64 rb = 0, rs = 0; - - /* ESID = srnum */ - rb |= (srnum & 0xf) << 28; - /* Set the valid bit */ - rb |= 1 << 27; - /* Index = ESID */ - rb |= srnum; - - /* VSID = VSID */ - rs |= (value & 0xfffffff) << 12; - /* flags = flags */ - rs |= ((value >> 27) & 0xf) << 9; - - kvmppc_mmu_book3s_64_slbmte(vcpu, rs, rb); -} - -static void kvmppc_mmu_book3s_64_tlbie(struct kvm_vcpu *vcpu, ulong va, - bool large) -{ - u64 mask = 0xFFFFFFFFFULL; - - dprintk("KVM MMU: tlbie(0x%lx)\n", va); - - if (large) - mask = 0xFFFFFF000ULL; - kvmppc_mmu_pte_vflush(vcpu, va >> 12, mask); -} - -static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, u64 esid, - u64 *vsid) -{ - switch (vcpu->arch.msr & (MSR_DR|MSR_IR)) { - case 0: - *vsid = (VSID_REAL >> 16) | esid; - break; - case MSR_IR: - *vsid = (VSID_REAL_IR >> 16) | esid; - break; - case MSR_DR: - *vsid = (VSID_REAL_DR >> 16) | esid; - break; - case MSR_DR|MSR_IR: - { - ulong ea; - struct kvmppc_slb *slb; - ea = esid << SID_SHIFT; - slb = kvmppc_mmu_book3s_64_find_slbe(to_book3s(vcpu), ea); - if (slb) - *vsid = slb->vsid; - else - return -ENOENT; - - break; - } - default: - BUG(); - break; - } - - return 0; -} - -static bool kvmppc_mmu_book3s_64_is_dcbz32(struct kvm_vcpu *vcpu) -{ - return (to_book3s(vcpu)->hid[5] & 0x80); -} - -void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu) -{ - struct kvmppc_mmu *mmu = &vcpu->arch.mmu; - - mmu->mfsrin = NULL; - mmu->mtsrin = kvmppc_mmu_book3s_64_mtsrin; - mmu->slbmte = kvmppc_mmu_book3s_64_slbmte; - mmu->slbmfee = kvmppc_mmu_book3s_64_slbmfee; - mmu->slbmfev = kvmppc_mmu_book3s_64_slbmfev; - mmu->slbie = kvmppc_mmu_book3s_64_slbie; - mmu->slbia = kvmppc_mmu_book3s_64_slbia; - mmu->xlate = kvmppc_mmu_book3s_64_xlate; - mmu->reset_msr = kvmppc_mmu_book3s_64_reset_msr; - mmu->tlbie = kvmppc_mmu_book3s_64_tlbie; - mmu->esid_to_vsid = kvmppc_mmu_book3s_64_esid_to_vsid; - mmu->ea_to_vp = kvmppc_mmu_book3s_64_ea_to_vp; - mmu->is_dcbz32 = kvmppc_mmu_book3s_64_is_dcbz32; - - vcpu->arch.hflags |= BOOK3S_HFLAG_SLB; -} diff --git a/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c b/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c deleted file mode 100644 index f2899b297ffd..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_mmu_host.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright (C) 2009 SUSE Linux Products GmbH. All rights reserved. - * - * Authors: - * Alexander Graf - * Kevin Wolf - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include - -#include -#include -#include -#include -#include -#include - -#define PTE_SIZE 12 -#define VSID_ALL 0 - -/* #define DEBUG_MMU */ -/* #define DEBUG_SLB */ - -#ifdef DEBUG_MMU -#define dprintk_mmu(a, ...) printk(KERN_INFO a, __VA_ARGS__) -#else -#define dprintk_mmu(a, ...) do { } while(0) -#endif - -#ifdef DEBUG_SLB -#define dprintk_slb(a, ...) printk(KERN_INFO a, __VA_ARGS__) -#else -#define dprintk_slb(a, ...) do { } while(0) -#endif - -static void invalidate_pte(struct hpte_cache *pte) -{ - dprintk_mmu("KVM: Flushing SPT %d: 0x%llx (0x%llx) -> 0x%llx\n", - i, pte->pte.eaddr, pte->pte.vpage, pte->host_va); - - ppc_md.hpte_invalidate(pte->slot, pte->host_va, - MMU_PAGE_4K, MMU_SEGSIZE_256M, - false); - pte->host_va = 0; - kvm_release_pfn_dirty(pte->pfn); -} - -void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, u64 guest_ea, u64 ea_mask) -{ - int i; - - dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%llx & 0x%llx\n", - vcpu->arch.hpte_cache_offset, guest_ea, ea_mask); - BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); - - guest_ea &= ea_mask; - for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { - struct hpte_cache *pte; - - pte = &vcpu->arch.hpte_cache[i]; - if (!pte->host_va) - continue; - - if ((pte->pte.eaddr & ea_mask) == guest_ea) { - invalidate_pte(pte); - } - } - - /* Doing a complete flush -> start from scratch */ - if (!ea_mask) - vcpu->arch.hpte_cache_offset = 0; -} - -void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask) -{ - int i; - - dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n", - vcpu->arch.hpte_cache_offset, guest_vp, vp_mask); - BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); - - guest_vp &= vp_mask; - for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { - struct hpte_cache *pte; - - pte = &vcpu->arch.hpte_cache[i]; - if (!pte->host_va) - continue; - - if ((pte->pte.vpage & vp_mask) == guest_vp) { - invalidate_pte(pte); - } - } -} - -void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, u64 pa_start, u64 pa_end) -{ - int i; - - dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n", - vcpu->arch.hpte_cache_offset, guest_pa, pa_mask); - BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM); - - for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) { - struct hpte_cache *pte; - - pte = &vcpu->arch.hpte_cache[i]; - if (!pte->host_va) - continue; - - if ((pte->pte.raddr >= pa_start) && - (pte->pte.raddr < pa_end)) { - invalidate_pte(pte); - } - } -} - -struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data) -{ - int i; - u64 guest_vp; - - guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false); - for (i=0; iarch.hpte_cache_offset; i++) { - struct hpte_cache *pte; - - pte = &vcpu->arch.hpte_cache[i]; - if (!pte->host_va) - continue; - - if (pte->pte.vpage == guest_vp) - return &pte->pte; - } - - return NULL; -} - -static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu) -{ - if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM) - kvmppc_mmu_pte_flush(vcpu, 0, 0); - - return vcpu->arch.hpte_cache_offset++; -} - -/* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using - * a hash, so we don't waste cycles on looping */ -static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid) -{ - return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^ - ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK)); -} - - -static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid) -{ - struct kvmppc_sid_map *map; - u16 sid_map_mask; - - if (vcpu->arch.msr & MSR_PR) - gvsid |= VSID_PR; - - sid_map_mask = kvmppc_sid_hash(vcpu, gvsid); - map = &to_book3s(vcpu)->sid_map[sid_map_mask]; - if (map->guest_vsid == gvsid) { - dprintk_slb("SLB: Searching 0x%llx -> 0x%llx\n", - gvsid, map->host_vsid); - return map; - } - - map = &to_book3s(vcpu)->sid_map[SID_MAP_MASK - sid_map_mask]; - if (map->guest_vsid == gvsid) { - dprintk_slb("SLB: Searching 0x%llx -> 0x%llx\n", - gvsid, map->host_vsid); - return map; - } - - dprintk_slb("SLB: Searching 0x%llx -> not found\n", gvsid); - return NULL; -} - -int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte) -{ - pfn_t hpaddr; - ulong hash, hpteg, va; - u64 vsid; - int ret; - int rflags = 0x192; - int vflags = 0; - int attempt = 0; - struct kvmppc_sid_map *map; - - /* Get host physical address for gpa */ - hpaddr = gfn_to_pfn(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT); - if (kvm_is_error_hva(hpaddr)) { - printk(KERN_INFO "Couldn't get guest page for gfn %llx!\n", orig_pte->eaddr); - return -EINVAL; - } - hpaddr <<= PAGE_SHIFT; -#if PAGE_SHIFT == 12 -#elif PAGE_SHIFT == 16 - hpaddr |= orig_pte->raddr & 0xf000; -#else -#error Unknown page size -#endif - - /* and write the mapping ea -> hpa into the pt */ - vcpu->arch.mmu.esid_to_vsid(vcpu, orig_pte->eaddr >> SID_SHIFT, &vsid); - map = find_sid_vsid(vcpu, vsid); - if (!map) { - kvmppc_mmu_map_segment(vcpu, orig_pte->eaddr); - map = find_sid_vsid(vcpu, vsid); - } - BUG_ON(!map); - - vsid = map->host_vsid; - va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M); - - if (!orig_pte->may_write) - rflags |= HPTE_R_PP; - else - mark_page_dirty(vcpu->kvm, orig_pte->raddr >> PAGE_SHIFT); - - if (!orig_pte->may_execute) - rflags |= HPTE_R_N; - - hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M); - -map_again: - hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); - - /* In case we tried normal mapping already, let's nuke old entries */ - if (attempt > 1) - if (ppc_md.hpte_remove(hpteg) < 0) - return -1; - - ret = ppc_md.hpte_insert(hpteg, va, hpaddr, rflags, vflags, MMU_PAGE_4K, MMU_SEGSIZE_256M); - - if (ret < 0) { - /* If we couldn't map a primary PTE, try a secondary */ -#ifdef USE_SECONDARY - hash = ~hash; - attempt++; - if (attempt % 2) - vflags = HPTE_V_SECONDARY; - else - vflags = 0; -#else - attempt = 2; -#endif - goto map_again; - } else { - int hpte_id = kvmppc_mmu_hpte_cache_next(vcpu); - struct hpte_cache *pte = &vcpu->arch.hpte_cache[hpte_id]; - - dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%lx (0x%llx) -> %lx\n", - ((rflags & HPTE_R_PP) == 3) ? '-' : 'w', - (rflags & HPTE_R_N) ? '-' : 'x', - orig_pte->eaddr, hpteg, va, orig_pte->vpage, hpaddr); - - pte->slot = hpteg + (ret & 7); - pte->host_va = va; - pte->pte = *orig_pte; - pte->pfn = hpaddr >> PAGE_SHIFT; - } - - return 0; -} - -static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid) -{ - struct kvmppc_sid_map *map; - struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); - u16 sid_map_mask; - static int backwards_map = 0; - - if (vcpu->arch.msr & MSR_PR) - gvsid |= VSID_PR; - - /* We might get collisions that trap in preceding order, so let's - map them differently */ - - sid_map_mask = kvmppc_sid_hash(vcpu, gvsid); - if (backwards_map) - sid_map_mask = SID_MAP_MASK - sid_map_mask; - - map = &to_book3s(vcpu)->sid_map[sid_map_mask]; - - /* Make sure we're taking the other map next time */ - backwards_map = !backwards_map; - - /* Uh-oh ... out of mappings. Let's flush! */ - if (vcpu_book3s->vsid_next == vcpu_book3s->vsid_max) { - vcpu_book3s->vsid_next = vcpu_book3s->vsid_first; - memset(vcpu_book3s->sid_map, 0, - sizeof(struct kvmppc_sid_map) * SID_MAP_NUM); - kvmppc_mmu_pte_flush(vcpu, 0, 0); - kvmppc_mmu_flush_segments(vcpu); - } - map->host_vsid = vcpu_book3s->vsid_next++; - - map->guest_vsid = gvsid; - map->valid = true; - - return map; -} - -static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid) -{ - int i; - int max_slb_size = 64; - int found_inval = -1; - int r; - - if (!get_paca()->kvm_slb_max) - get_paca()->kvm_slb_max = 1; - - /* Are we overwriting? */ - for (i = 1; i < get_paca()->kvm_slb_max; i++) { - if (!(get_paca()->kvm_slb[i].esid & SLB_ESID_V)) - found_inval = i; - else if ((get_paca()->kvm_slb[i].esid & ESID_MASK) == esid) - return i; - } - - /* Found a spare entry that was invalidated before */ - if (found_inval > 0) - return found_inval; - - /* No spare invalid entry, so create one */ - - if (mmu_slb_size < 64) - max_slb_size = mmu_slb_size; - - /* Overflowing -> purge */ - if ((get_paca()->kvm_slb_max) == max_slb_size) - kvmppc_mmu_flush_segments(vcpu); - - r = get_paca()->kvm_slb_max; - get_paca()->kvm_slb_max++; - - return r; -} - -int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr) -{ - u64 esid = eaddr >> SID_SHIFT; - u64 slb_esid = (eaddr & ESID_MASK) | SLB_ESID_V; - u64 slb_vsid = SLB_VSID_USER; - u64 gvsid; - int slb_index; - struct kvmppc_sid_map *map; - - slb_index = kvmppc_mmu_next_segment(vcpu, eaddr & ESID_MASK); - - if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) { - /* Invalidate an entry */ - get_paca()->kvm_slb[slb_index].esid = 0; - return -ENOENT; - } - - map = find_sid_vsid(vcpu, gvsid); - if (!map) - map = create_sid_map(vcpu, gvsid); - - map->guest_esid = esid; - - slb_vsid |= (map->host_vsid << 12); - slb_vsid &= ~SLB_VSID_KP; - slb_esid |= slb_index; - - get_paca()->kvm_slb[slb_index].esid = slb_esid; - get_paca()->kvm_slb[slb_index].vsid = slb_vsid; - - dprintk_slb("slbmte %#llx, %#llx\n", slb_vsid, slb_esid); - - return 0; -} - -void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu) -{ - get_paca()->kvm_slb_max = 1; - get_paca()->kvm_slb[0].esid = 0; -} - -void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu) -{ - kvmppc_mmu_pte_flush(vcpu, 0, 0); -} diff --git a/trunk/arch/powerpc/kvm/book3s_64_rmhandlers.S b/trunk/arch/powerpc/kvm/book3s_64_rmhandlers.S deleted file mode 100644 index fb7dd2e9ac88..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_rmhandlers.S +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#include -#include -#include -#include -#include -#include - -/***************************************************************************** - * * - * Real Mode handlers that need to be in low physical memory * - * * - ****************************************************************************/ - - -.macro INTERRUPT_TRAMPOLINE intno - -.global kvmppc_trampoline_\intno -kvmppc_trampoline_\intno: - - mtspr SPRN_SPRG_SCRATCH0, r13 /* Save r13 */ - - /* - * First thing to do is to find out if we're coming - * from a KVM guest or a Linux process. - * - * To distinguish, we check a magic byte in the PACA - */ - mfspr r13, SPRN_SPRG_PACA /* r13 = PACA */ - std r12, (PACA_EXMC + EX_R12)(r13) - mfcr r12 - stw r12, (PACA_EXMC + EX_CCR)(r13) - lbz r12, PACA_KVM_IN_GUEST(r13) - cmpwi r12, 0 - bne ..kvmppc_handler_hasmagic_\intno - /* No KVM guest? Then jump back to the Linux handler! */ - lwz r12, (PACA_EXMC + EX_CCR)(r13) - mtcr r12 - ld r12, (PACA_EXMC + EX_R12)(r13) - mfspr r13, SPRN_SPRG_SCRATCH0 /* r13 = original r13 */ - b kvmppc_resume_\intno /* Get back original handler */ - - /* Now we know we're handling a KVM guest */ -..kvmppc_handler_hasmagic_\intno: - /* Unset guest state */ - li r12, 0 - stb r12, PACA_KVM_IN_GUEST(r13) - - std r1, (PACA_EXMC+EX_R9)(r13) - std r10, (PACA_EXMC+EX_R10)(r13) - std r11, (PACA_EXMC+EX_R11)(r13) - std r2, (PACA_EXMC+EX_R13)(r13) - - mfsrr0 r10 - mfsrr1 r11 - - /* Restore R1/R2 so we can handle faults */ - ld r1, PACAR1(r13) - ld r2, (PACA_EXMC+EX_SRR0)(r13) - - /* Let's store which interrupt we're handling */ - li r12, \intno - - /* Jump into the SLB exit code that goes to the highmem handler */ - b kvmppc_handler_trampoline_exit - -.endm - -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSTEM_RESET -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_MACHINE_CHECK -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_STORAGE -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_SEGMENT -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_STORAGE -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_SEGMENT -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_EXTERNAL -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALIGNMENT -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PROGRAM -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_FP_UNAVAIL -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DECREMENTER -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSCALL -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_TRACE -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PERFMON -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALTIVEC -INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_VSX - -/* - * This trampoline brings us back to a real mode handler - * - * Input Registers: - * - * R6 = SRR0 - * R7 = SRR1 - * LR = real-mode IP - * - */ -.global kvmppc_handler_lowmem_trampoline -kvmppc_handler_lowmem_trampoline: - - mtsrr0 r6 - mtsrr1 r7 - blr -kvmppc_handler_lowmem_trampoline_end: - -.global kvmppc_trampoline_lowmem -kvmppc_trampoline_lowmem: - .long kvmppc_handler_lowmem_trampoline - _stext - -.global kvmppc_trampoline_enter -kvmppc_trampoline_enter: - .long kvmppc_handler_trampoline_enter - _stext - -#include "book3s_64_slb.S" - diff --git a/trunk/arch/powerpc/kvm/book3s_64_slb.S b/trunk/arch/powerpc/kvm/book3s_64_slb.S deleted file mode 100644 index ecd237a03fd0..000000000000 --- a/trunk/arch/powerpc/kvm/book3s_64_slb.S +++ /dev/null @@ -1,262 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * Copyright SUSE Linux Products GmbH 2009 - * - * Authors: Alexander Graf - */ - -#define SHADOW_SLB_ESID(num) (SLBSHADOW_SAVEAREA + (num * 0x10)) -#define SHADOW_SLB_VSID(num) (SLBSHADOW_SAVEAREA + (num * 0x10) + 0x8) -#define UNBOLT_SLB_ENTRY(num) \ - ld r9, SHADOW_SLB_ESID(num)(r12); \ - /* Invalid? Skip. */; \ - rldicl. r0, r9, 37, 63; \ - beq slb_entry_skip_ ## num; \ - xoris r9, r9, SLB_ESID_V@h; \ - std r9, SHADOW_SLB_ESID(num)(r12); \ - slb_entry_skip_ ## num: - -#define REBOLT_SLB_ENTRY(num) \ - ld r10, SHADOW_SLB_ESID(num)(r11); \ - cmpdi r10, 0; \ - beq slb_exit_skip_1; \ - oris r10, r10, SLB_ESID_V@h; \ - ld r9, SHADOW_SLB_VSID(num)(r11); \ - slbmte r9, r10; \ - std r10, SHADOW_SLB_ESID(num)(r11); \ -slb_exit_skip_ ## num: - -/****************************************************************************** - * * - * Entry code * - * * - *****************************************************************************/ - -.global kvmppc_handler_trampoline_enter -kvmppc_handler_trampoline_enter: - - /* Required state: - * - * MSR = ~IR|DR - * R13 = PACA - * R9 = guest IP - * R10 = guest MSR - * R11 = free - * R12 = free - * PACA[PACA_EXMC + EX_R9] = guest R9 - * PACA[PACA_EXMC + EX_R10] = guest R10 - * PACA[PACA_EXMC + EX_R11] = guest R11 - * PACA[PACA_EXMC + EX_R12] = guest R12 - * PACA[PACA_EXMC + EX_R13] = guest R13 - * PACA[PACA_EXMC + EX_CCR] = guest CR - * PACA[PACA_EXMC + EX_R3] = guest XER - */ - - mtsrr0 r9 - mtsrr1 r10 - - mtspr SPRN_SPRG_SCRATCH0, r0 - - /* Remove LPAR shadow entries */ - -#if SLB_NUM_BOLTED == 3 - - ld r12, PACA_SLBSHADOWPTR(r13) - - /* Save off the first entry so we can slbie it later */ - ld r10, SHADOW_SLB_ESID(0)(r12) - ld r11, SHADOW_SLB_VSID(0)(r12) - - /* Remove bolted entries */ - UNBOLT_SLB_ENTRY(0) - UNBOLT_SLB_ENTRY(1) - UNBOLT_SLB_ENTRY(2) - -#else -#error unknown number of bolted entries -#endif - - /* Flush SLB */ - - slbia - - /* r0 = esid & ESID_MASK */ - rldicr r10, r10, 0, 35 - /* r0 |= CLASS_BIT(VSID) */ - rldic r12, r11, 56 - 36, 36 - or r10, r10, r12 - slbie r10 - - isync - - /* Fill SLB with our shadow */ - - lbz r12, PACA_KVM_SLB_MAX(r13) - mulli r12, r12, 16 - addi r12, r12, PACA_KVM_SLB - add r12, r12, r13 - - /* for (r11 = kvm_slb; r11 < kvm_slb + kvm_slb_size; r11+=slb_entry) */ - li r11, PACA_KVM_SLB - add r11, r11, r13 - -slb_loop_enter: - - ld r10, 0(r11) - - rldicl. r0, r10, 37, 63 - beq slb_loop_enter_skip - - ld r9, 8(r11) - slbmte r9, r10 - -slb_loop_enter_skip: - addi r11, r11, 16 - cmpd cr0, r11, r12 - blt slb_loop_enter - -slb_do_enter: - - /* Enter guest */ - - mfspr r0, SPRN_SPRG_SCRATCH0 - - ld r9, (PACA_EXMC+EX_R9)(r13) - ld r10, (PACA_EXMC+EX_R10)(r13) - ld r12, (PACA_EXMC+EX_R12)(r13) - - lwz r11, (PACA_EXMC+EX_CCR)(r13) - mtcr r11 - - ld r11, (PACA_EXMC+EX_R3)(r13) - mtxer r11 - - ld r11, (PACA_EXMC+EX_R11)(r13) - ld r13, (PACA_EXMC+EX_R13)(r13) - - RFI -kvmppc_handler_trampoline_enter_end: - - - -/****************************************************************************** - * * - * Exit code * - * * - *****************************************************************************/ - -.global kvmppc_handler_trampoline_exit -kvmppc_handler_trampoline_exit: - - /* Register usage at this point: - * - * SPRG_SCRATCH0 = guest R13 - * R01 = host R1 - * R02 = host R2 - * R10 = guest PC - * R11 = guest MSR - * R12 = exit handler id - * R13 = PACA - * PACA.exmc.CCR = guest CR - * PACA.exmc.R9 = guest R1 - * PACA.exmc.R10 = guest R10 - * PACA.exmc.R11 = guest R11 - * PACA.exmc.R12 = guest R12 - * PACA.exmc.R13 = guest R2 - * - */ - - /* Save registers */ - - std r0, (PACA_EXMC+EX_SRR0)(r13) - std r9, (PACA_EXMC+EX_R3)(r13) - std r10, (PACA_EXMC+EX_LR)(r13) - std r11, (PACA_EXMC+EX_DAR)(r13) - - /* - * In order for us to easily get the last instruction, - * we got the #vmexit at, we exploit the fact that the - * virtual layout is still the same here, so we can just - * ld from the guest's PC address - */ - - /* We only load the last instruction when it's safe */ - cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE - beq ld_last_inst - cmpwi r12, BOOK3S_INTERRUPT_PROGRAM - beq ld_last_inst - - b no_ld_last_inst - -ld_last_inst: - /* Save off the guest instruction we're at */ - /* 1) enable paging for data */ - mfmsr r9 - ori r11, r9, MSR_DR /* Enable paging for data */ - mtmsr r11 - /* 2) fetch the instruction */ - lwz r0, 0(r10) - /* 3) disable paging again */ - mtmsr r9 - -no_ld_last_inst: - - /* Restore bolted entries from the shadow and fix it along the way */ - - /* We don't store anything in entry 0, so we don't need to take care of it */ - slbia - isync - -#if SLB_NUM_BOLTED == 3 - - ld r11, PACA_SLBSHADOWPTR(r13) - - REBOLT_SLB_ENTRY(0) - REBOLT_SLB_ENTRY(1) - REBOLT_SLB_ENTRY(2) - -#else -#error unknown number of bolted entries -#endif - -slb_do_exit: - - /* Restore registers */ - - ld r11, (PACA_EXMC+EX_DAR)(r13) - ld r10, (PACA_EXMC+EX_LR)(r13) - ld r9, (PACA_EXMC+EX_R3)(r13) - - /* Save last inst */ - stw r0, (PACA_EXMC+EX_LR)(r13) - - /* Save DAR and DSISR before going to paged mode */ - mfdar r0 - std r0, (PACA_EXMC+EX_DAR)(r13) - mfdsisr r0 - stw r0, (PACA_EXMC+EX_DSISR)(r13) - - /* RFI into the highmem handler */ - mfmsr r0 - ori r0, r0, MSR_IR|MSR_DR|MSR_RI /* Enable paging */ - mtsrr1 r0 - ld r0, PACASAVEDMSR(r13) /* Highmem handler address */ - mtsrr0 r0 - - mfspr r0, SPRN_SPRG_SCRATCH0 - - RFI -kvmppc_handler_trampoline_exit_end: - diff --git a/trunk/arch/powerpc/kvm/booke.c b/trunk/arch/powerpc/kvm/booke.c index 06f5a9ecc42c..e7bf4d029484 100644 --- a/trunk/arch/powerpc/kvm/booke.c +++ b/trunk/arch/powerpc/kvm/booke.c @@ -520,11 +520,6 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, return kvmppc_core_vcpu_translate(vcpu, tr); } -int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) -{ - return -ENOTSUPP; -} - int __init kvmppc_booke_init(void) { unsigned long ivor[16]; diff --git a/trunk/arch/powerpc/kvm/emulate.c b/trunk/arch/powerpc/kvm/emulate.c index 4a9ac6640fad..7737146af3fb 100644 --- a/trunk/arch/powerpc/kvm/emulate.c +++ b/trunk/arch/powerpc/kvm/emulate.c @@ -18,7 +18,7 @@ */ #include -#include +#include #include #include #include @@ -32,7 +32,6 @@ #include "trace.h" #define OP_TRAP 3 -#define OP_TRAP_64 2 #define OP_31_XOP_LWZX 23 #define OP_31_XOP_LBZX 87 @@ -65,45 +64,19 @@ #define OP_STH 44 #define OP_STHU 45 -#ifdef CONFIG_PPC64 -static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) -{ - return 1; -} -#else -static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.tcr & TCR_DIE; -} -#endif - void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) { - unsigned long dec_nsec; - - pr_debug("mtDEC: %x\n", vcpu->arch.dec); -#ifdef CONFIG_PPC64 - /* POWER4+ triggers a dec interrupt if the value is < 0 */ - if (vcpu->arch.dec & 0x80000000) { - hrtimer_try_to_cancel(&vcpu->arch.dec_timer); - kvmppc_core_queue_dec(vcpu); - return; - } -#endif - if (kvmppc_dec_enabled(vcpu)) { + if (vcpu->arch.tcr & TCR_DIE) { /* The decrementer ticks at the same rate as the timebase, so * that's how we convert the guest DEC value to the number of * host ticks. */ + unsigned long nr_jiffies; - hrtimer_try_to_cancel(&vcpu->arch.dec_timer); - dec_nsec = vcpu->arch.dec; - dec_nsec *= 1000; - dec_nsec /= tb_ticks_per_usec; - hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec), - HRTIMER_MODE_REL); - vcpu->arch.dec_jiffies = get_tb(); + nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy; + mod_timer(&vcpu->arch.dec_timer, + get_jiffies_64() + nr_jiffies); } else { - hrtimer_try_to_cancel(&vcpu->arch.dec_timer); + del_timer(&vcpu->arch.dec_timer); } } @@ -138,15 +111,9 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) /* this default type might be overwritten by subcategories */ kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); - pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); - switch (get_op(inst)) { case OP_TRAP: -#ifdef CONFIG_PPC64 - case OP_TRAP_64: -#else vcpu->arch.esr |= ESR_PTR; -#endif kvmppc_core_queue_program(vcpu); advance = 0; break; @@ -221,19 +188,17 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) case SPRN_SRR1: vcpu->arch.gpr[rt] = vcpu->arch.srr1; break; case SPRN_PVR: - vcpu->arch.gpr[rt] = vcpu->arch.pvr; break; + vcpu->arch.gpr[rt] = mfspr(SPRN_PVR); break; case SPRN_PIR: - vcpu->arch.gpr[rt] = vcpu->vcpu_id; break; - case SPRN_MSSSR0: - vcpu->arch.gpr[rt] = 0; break; + vcpu->arch.gpr[rt] = mfspr(SPRN_PIR); break; /* Note: mftb and TBRL/TBWL are user-accessible, so * the guest can always access the real TB anyways. * In fact, we probably will never see these traps. */ case SPRN_TBWL: - vcpu->arch.gpr[rt] = get_tb() >> 32; break; + vcpu->arch.gpr[rt] = mftbl(); break; case SPRN_TBWU: - vcpu->arch.gpr[rt] = get_tb(); break; + vcpu->arch.gpr[rt] = mftbu(); break; case SPRN_SPRG0: vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break; @@ -246,13 +211,6 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) /* Note: SPRG4-7 are user-readable, so we don't get * a trap. */ - case SPRN_DEC: - { - u64 jd = get_tb() - vcpu->arch.dec_jiffies; - vcpu->arch.gpr[rt] = vcpu->arch.dec - jd; - pr_debug(KERN_INFO "mfDEC: %x - %llx = %lx\n", vcpu->arch.dec, jd, vcpu->arch.gpr[rt]); - break; - } default: emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt); if (emulated == EMULATE_FAIL) { @@ -302,8 +260,6 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) case SPRN_TBWL: break; case SPRN_TBWU: break; - case SPRN_MSSSR0: break; - case SPRN_DEC: vcpu->arch.dec = vcpu->arch.gpr[rs]; kvmppc_emulate_dec(vcpu); diff --git a/trunk/arch/powerpc/kvm/powerpc.c b/trunk/arch/powerpc/kvm/powerpc.c index f06cf93b178e..5902bbc2411e 100644 --- a/trunk/arch/powerpc/kvm/powerpc.c +++ b/trunk/arch/powerpc/kvm/powerpc.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -145,9 +144,6 @@ int kvm_dev_ioctl_check_extension(long ext) int r; switch (ext) { - case KVM_CAP_PPC_SEGSTATE: - r = 1; - break; case KVM_CAP_COALESCED_MMIO: r = KVM_COALESCED_MMIO_PAGE_OFFSET; break; @@ -213,25 +209,10 @@ static void kvmppc_decrementer_func(unsigned long data) } } -/* - * low level hrtimer wake routine. Because this runs in hardirq context - * we schedule a tasklet to do the real work. - */ -enum hrtimer_restart kvmppc_decrementer_wakeup(struct hrtimer *timer) -{ - struct kvm_vcpu *vcpu; - - vcpu = container_of(timer, struct kvm_vcpu, arch.dec_timer); - tasklet_schedule(&vcpu->arch.tasklet); - - return HRTIMER_NORESTART; -} - int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) { - hrtimer_init(&vcpu->arch.dec_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); - tasklet_init(&vcpu->arch.tasklet, kvmppc_decrementer_func, (ulong)vcpu); - vcpu->arch.dec_timer.function = kvmppc_decrementer_wakeup; + setup_timer(&vcpu->arch.dec_timer, kvmppc_decrementer_func, + (unsigned long)vcpu); return 0; } @@ -429,6 +410,11 @@ long kvm_arch_vcpu_ioctl(struct file *filp, return r; } +int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) +{ + return -ENOTSUPP; +} + long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { diff --git a/trunk/arch/powerpc/kvm/timing.c b/trunk/arch/powerpc/kvm/timing.c index 70378551c0cc..2aa371e30079 100644 --- a/trunk/arch/powerpc/kvm/timing.c +++ b/trunk/arch/powerpc/kvm/timing.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/powerpc/kvm/trace.h b/trunk/arch/powerpc/kvm/trace.h index a8e840018052..67f219de0455 100644 --- a/trunk/arch/powerpc/kvm/trace.h +++ b/trunk/arch/powerpc/kvm/trace.h @@ -12,8 +12,8 @@ * Tracepoint for guest mode entry. */ TRACE_EVENT(kvm_ppc_instr, - TP_PROTO(unsigned int inst, unsigned long _pc, unsigned int emulate), - TP_ARGS(inst, _pc, emulate), + TP_PROTO(unsigned int inst, unsigned long pc, unsigned int emulate), + TP_ARGS(inst, pc, emulate), TP_STRUCT__entry( __field( unsigned int, inst ) @@ -23,7 +23,7 @@ TRACE_EVENT(kvm_ppc_instr, TP_fast_assign( __entry->inst = inst; - __entry->pc = _pc; + __entry->pc = pc; __entry->emulate = emulate; ), diff --git a/trunk/arch/powerpc/lib/copy_32.S b/trunk/arch/powerpc/lib/copy_32.S index 74a7f4130b4c..c657de59abca 100644 --- a/trunk/arch/powerpc/lib/copy_32.S +++ b/trunk/arch/powerpc/lib/copy_32.S @@ -98,7 +98,20 @@ _GLOBAL(cacheable_memzero) bdnz 4b 3: mtctr r9 li r7,4 +#if !defined(CONFIG_8xx) 10: dcbz r7,r6 +#else +10: stw r4, 4(r6) + stw r4, 8(r6) + stw r4, 12(r6) + stw r4, 16(r6) +#if CACHE_LINE_SIZE >= 32 + stw r4, 20(r6) + stw r4, 24(r6) + stw r4, 28(r6) + stw r4, 32(r6) +#endif /* CACHE_LINE_SIZE */ +#endif addi r6,r6,CACHELINE_BYTES bdnz 10b clrlwi r5,r8,32-LG_CACHELINE_BYTES @@ -187,7 +200,9 @@ _GLOBAL(cacheable_memcpy) mtctr r0 beq 63f 53: +#if !defined(CONFIG_8xx) dcbz r11,r6 +#endif COPY_16_BYTES #if L1_CACHE_BYTES >= 32 COPY_16_BYTES @@ -341,6 +356,14 @@ _GLOBAL(__copy_tofrom_user) li r11,4 beq 63f +#ifdef CONFIG_8xx + /* Don't use prefetch on 8xx */ + mtctr r0 + li r0,0 +53: COPY_16_BYTES_WITHEX(0) + bdnz 53b + +#else /* not CONFIG_8xx */ /* Here we decide how far ahead to prefetch the source */ li r3,4 cmpwi r0,1 @@ -393,6 +416,7 @@ _GLOBAL(__copy_tofrom_user) li r3,4 li r7,0 bne 114b +#endif /* CONFIG_8xx */ 63: srwi. r0,r5,2 mtctr r0 diff --git a/trunk/arch/powerpc/mm/Makefile b/trunk/arch/powerpc/mm/Makefile index ce68708bbad5..6fb8fc8d2fea 100644 --- a/trunk/arch/powerpc/mm/Makefile +++ b/trunk/arch/powerpc/mm/Makefile @@ -28,10 +28,7 @@ obj-$(CONFIG_44x) += 44x_mmu.o obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o obj-$(CONFIG_PPC_MM_SLICES) += slice.o -ifeq ($(CONFIG_HUGETLB_PAGE),y) -obj-y += hugetlbpage.o -obj-$(CONFIG_PPC_STD_MMU_64) += hugetlbpage-hash64.o -endif +obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o obj-$(CONFIG_HIGHMEM) += highmem.o diff --git a/trunk/arch/powerpc/mm/fault.c b/trunk/arch/powerpc/mm/fault.c index 26fb6b990b0a..e7dae82c1285 100644 --- a/trunk/arch/powerpc/mm/fault.c +++ b/trunk/arch/powerpc/mm/fault.c @@ -40,7 +40,7 @@ #include #include #include -#include + #ifdef CONFIG_KPROBES static inline int notify_page_fault(struct pt_regs *regs) @@ -246,12 +246,6 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address, goto bad_area; #endif /* CONFIG_6xx */ #if defined(CONFIG_8xx) - /* 8xx sometimes need to load a invalid/non-present TLBs. - * These must be invalidated separately as linux mm don't. - */ - if (error_code & 0x40000000) /* no translation? */ - _tlbil_va(address, 0, 0, 0); - /* The MPC8xx seems to always set 0x80000000, which is * "undefined". Of those that can be set, this is the only * one which seems bad. diff --git a/trunk/arch/powerpc/mm/fsl_booke_mmu.c b/trunk/arch/powerpc/mm/fsl_booke_mmu.c index fcfcb6e976c7..dc93e95b256e 100644 --- a/trunk/arch/powerpc/mm/fsl_booke_mmu.c +++ b/trunk/arch/powerpc/mm/fsl_booke_mmu.c @@ -54,35 +54,26 @@ #include "mmu_decl.h" +extern void loadcam_entry(unsigned int index); unsigned int tlbcam_index; +static unsigned long cam[CONFIG_LOWMEM_CAM_NUM]; -#define NUM_TLBCAMS (64) +#define NUM_TLBCAMS (16) #if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS) #error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS" #endif -struct tlbcam { - u32 MAS0; - u32 MAS1; - unsigned long MAS2; - u32 MAS3; - u32 MAS7; -} TLBCAM[NUM_TLBCAMS]; +struct tlbcam TLBCAM[NUM_TLBCAMS]; struct tlbcamrange { - unsigned long start; + unsigned long start; unsigned long limit; phys_addr_t phys; } tlbcam_addrs[NUM_TLBCAMS]; extern unsigned int tlbcam_index; -unsigned long tlbcam_sz(int idx) -{ - return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1; -} - /* * Return PA for this VA if it is mapped by a CAM, or 0 */ @@ -103,36 +94,23 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa) int b; for (b = 0; b < tlbcam_index; ++b) if (pa >= tlbcam_addrs[b].phys - && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start) + && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start) +tlbcam_addrs[b].phys) return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys); return 0; } -void loadcam_entry(int idx) -{ - mtspr(SPRN_MAS0, TLBCAM[idx].MAS0); - mtspr(SPRN_MAS1, TLBCAM[idx].MAS1); - mtspr(SPRN_MAS2, TLBCAM[idx].MAS2); - mtspr(SPRN_MAS3, TLBCAM[idx].MAS3); - - if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS) - mtspr(SPRN_MAS7, TLBCAM[idx].MAS7); - - asm volatile("isync;tlbwe;isync" : : : "memory"); -} - /* * Set up one of the I/D BAT (block address translation) register pairs. * The parameters are not checked; in particular size must be a power * of 4 between 4k and 256M. */ -static void settlbcam(int index, unsigned long virt, phys_addr_t phys, - unsigned long size, unsigned long flags, unsigned int pid) +void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned int size, int flags, unsigned int pid) { unsigned int tsize, lz; - asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (size)); + asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); tsize = 21 - lz; #ifdef CONFIG_SMP @@ -150,10 +128,8 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0; TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0; - TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR; + TLBCAM[index].MAS3 = (phys & PAGE_MASK) | MAS3_SX | MAS3_SR; TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_SW : 0); - if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS) - TLBCAM[index].MAS7 = (u64)phys >> 32; #ifndef CONFIG_KGDB /* want user access for breakpoints */ if (flags & _PAGE_USER) { @@ -172,44 +148,27 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, loadcam_entry(index); } -unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx) +void invalidate_tlbcam_entry(int index) { - int i; - unsigned long virt = PAGE_OFFSET; - phys_addr_t phys = memstart_addr; - unsigned long amount_mapped = 0; - unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; - - /* Convert (4^max) kB to (2^max) bytes */ - max_cam = max_cam * 2 + 10; - - /* Calculate CAM values */ - for (i = 0; ram && i < max_cam_idx; i++) { - unsigned int camsize = __ilog2(ram) & ~1U; - unsigned int align = __ffs(virt | phys) & ~1U; - unsigned long cam_sz; - - if (camsize > align) - camsize = align; - if (camsize > max_cam) - camsize = max_cam; - - cam_sz = 1UL << camsize; - settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0); + TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index); + TLBCAM[index].MAS1 = ~MAS1_VALID; - ram -= cam_sz; - amount_mapped += cam_sz; - virt += cam_sz; - phys += cam_sz; - } - tlbcam_index = i; - - return amount_mapped; + loadcam_entry(index); } unsigned long __init mmu_mapin_ram(void) { - return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1; + unsigned long virt = PAGE_OFFSET; + phys_addr_t phys = memstart_addr; + + while (tlbcam_index < ARRAY_SIZE(cam) && cam[tlbcam_index]) { + settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], PAGE_KERNEL_X, 0); + virt += cam[tlbcam_index]; + phys += cam[tlbcam_index]; + tlbcam_index++; + } + + return virt - PAGE_OFFSET; } /* @@ -220,21 +179,46 @@ void __init MMU_init_hw(void) flush_instruction_cache(); } -void __init adjust_total_lowmem(void) +void __init +adjust_total_lowmem(void) { - unsigned long ram; + phys_addr_t ram; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + char buf[ARRAY_SIZE(cam) * 5 + 1], *p = buf; int i; + unsigned long virt = PAGE_OFFSET & 0xffffffffUL; + unsigned long phys = memstart_addr & 0xffffffffUL; + + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = max_cam * 2 + 10; /* adjust lowmem size to __max_low_memory */ ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem); - __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM); + /* Calculate CAM values */ + __max_low_memory = 0; + for (i = 0; ram && i < ARRAY_SIZE(cam); i++) { + unsigned int camsize = __ilog2(ram) & ~1U; + unsigned int align = __ffs(virt | phys) & ~1U; - pr_info("Memory CAM mapping: "); - for (i = 0; i < tlbcam_index - 1; i++) - pr_cont("%lu/", tlbcam_sz(i) >> 20); - pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20, - (unsigned int)((total_lowmem - __max_low_memory) >> 20)); + if (camsize > align) + camsize = align; + if (camsize > max_cam) + camsize = max_cam; + + cam[i] = 1UL << camsize; + ram -= cam[i]; + __max_low_memory += cam[i]; + virt += cam[i]; + phys += cam[i]; + p += sprintf(p, "%lu/", cam[i] >> 20); + } + for (; i < ARRAY_SIZE(cam); i++) + p += sprintf(p, "0/"); + p[-1] = '\0'; + + pr_info("Memory CAM mapping: %s Mb, residual: %dMb\n", buf, + (unsigned int)((total_lowmem - __max_low_memory) >> 20)); __initial_memory_limit_addr = memstart_addr + __max_low_memory; } diff --git a/trunk/arch/powerpc/mm/gup.c b/trunk/arch/powerpc/mm/gup.c index d7efdbf640c7..bc122a120bf0 100644 --- a/trunk/arch/powerpc/mm/gup.c +++ b/trunk/arch/powerpc/mm/gup.c @@ -55,6 +55,57 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr, return 1; } +#ifdef CONFIG_HUGETLB_PAGE +static noinline int gup_huge_pte(pte_t *ptep, struct hstate *hstate, + unsigned long *addr, unsigned long end, + int write, struct page **pages, int *nr) +{ + unsigned long mask; + unsigned long pte_end; + struct page *head, *page; + pte_t pte; + int refs; + + pte_end = (*addr + huge_page_size(hstate)) & huge_page_mask(hstate); + if (pte_end < end) + end = pte_end; + + pte = *ptep; + mask = _PAGE_PRESENT|_PAGE_USER; + if (write) + mask |= _PAGE_RW; + if ((pte_val(pte) & mask) != mask) + return 0; + /* hugepages are never "special" */ + VM_BUG_ON(!pfn_valid(pte_pfn(pte))); + + refs = 0; + head = pte_page(pte); + page = head + ((*addr & ~huge_page_mask(hstate)) >> PAGE_SHIFT); + do { + VM_BUG_ON(compound_head(page) != head); + pages[*nr] = page; + (*nr)++; + page++; + refs++; + } while (*addr += PAGE_SIZE, *addr != end); + + if (!page_cache_add_speculative(head, refs)) { + *nr -= refs; + return 0; + } + if (unlikely(pte_val(pte) != pte_val(*ptep))) { + /* Could be optimized better */ + while (*nr) { + put_page(page); + (*nr)--; + } + } + + return 1; +} +#endif /* CONFIG_HUGETLB_PAGE */ + static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end, int write, struct page **pages, int *nr) { @@ -68,11 +119,7 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end, next = pmd_addr_end(addr, end); if (pmd_none(pmd)) return 0; - if (is_hugepd(pmdp)) { - if (!gup_hugepd((hugepd_t *)pmdp, PMD_SHIFT, - addr, next, write, pages, nr)) - return 0; - } else if (!gup_pte_range(pmd, addr, next, write, pages, nr)) + if (!gup_pte_range(pmd, addr, next, write, pages, nr)) return 0; } while (pmdp++, addr = next, addr != end); @@ -92,11 +139,7 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end, next = pud_addr_end(addr, end); if (pud_none(pud)) return 0; - if (is_hugepd(pudp)) { - if (!gup_hugepd((hugepd_t *)pudp, PUD_SHIFT, - addr, next, write, pages, nr)) - return 0; - } else if (!gup_pmd_range(pud, addr, next, write, pages, nr)) + if (!gup_pmd_range(pud, addr, next, write, pages, nr)) return 0; } while (pudp++, addr = next, addr != end); @@ -111,6 +154,10 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, unsigned long next; pgd_t *pgdp; int nr = 0; +#ifdef CONFIG_PPC64 + unsigned int shift; + int psize; +#endif pr_devel("%s(%lx,%x,%s)\n", __func__, start, nr_pages, write ? "write" : "read"); @@ -125,6 +172,25 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, pr_devel(" aligned: %lx .. %lx\n", start, end); +#ifdef CONFIG_HUGETLB_PAGE + /* We bail out on slice boundary crossing when hugetlb is + * enabled in order to not have to deal with two different + * page table formats + */ + if (addr < SLICE_LOW_TOP) { + if (end > SLICE_LOW_TOP) + goto slow_irqon; + + if (unlikely(GET_LOW_SLICE_INDEX(addr) != + GET_LOW_SLICE_INDEX(end - 1))) + goto slow_irqon; + } else { + if (unlikely(GET_HIGH_SLICE_INDEX(addr) != + GET_HIGH_SLICE_INDEX(end - 1))) + goto slow_irqon; + } +#endif /* CONFIG_HUGETLB_PAGE */ + /* * XXX: batch / limit 'nr', to avoid large irq off latency * needs some instrumenting to determine the common sizes used by @@ -144,23 +210,54 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, */ local_irq_disable(); - pgdp = pgd_offset(mm, addr); - do { - pgd_t pgd = *pgdp; - - pr_devel(" %016lx: normal pgd %p\n", addr, - (void *)pgd_val(pgd)); - next = pgd_addr_end(addr, end); - if (pgd_none(pgd)) - goto slow; - if (is_hugepd(pgdp)) { - if (!gup_hugepd((hugepd_t *)pgdp, PGDIR_SHIFT, - addr, next, write, pages, &nr)) +#ifdef CONFIG_PPC64 + /* Those bits are related to hugetlbfs implementation and only exist + * on 64-bit for now + */ + psize = get_slice_psize(mm, addr); + shift = mmu_psize_defs[psize].shift; +#endif /* CONFIG_PPC64 */ + +#ifdef CONFIG_HUGETLB_PAGE + if (unlikely(mmu_huge_psizes[psize])) { + pte_t *ptep; + unsigned long a = addr; + unsigned long sz = ((1UL) << shift); + struct hstate *hstate = size_to_hstate(sz); + + BUG_ON(!hstate); + /* + * XXX: could be optimized to avoid hstate + * lookup entirely (just use shift) + */ + + do { + VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, a)].shift); + ptep = huge_pte_offset(mm, a); + pr_devel(" %016lx: huge ptep %p\n", a, ptep); + if (!ptep || !gup_huge_pte(ptep, hstate, &a, end, write, pages, + &nr)) goto slow; - } else if (!gup_pud_range(pgd, addr, next, write, pages, &nr)) - goto slow; - } while (pgdp++, addr = next, addr != end); - + } while (a != end); + } else +#endif /* CONFIG_HUGETLB_PAGE */ + { + pgdp = pgd_offset(mm, addr); + do { + pgd_t pgd = *pgdp; + +#ifdef CONFIG_PPC64 + VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, addr)].shift); +#endif + pr_devel(" %016lx: normal pgd %p\n", addr, + (void *)pgd_val(pgd)); + next = pgd_addr_end(addr, end); + if (pgd_none(pgd)) + goto slow; + if (!gup_pud_range(pgd, addr, next, write, pages, &nr)) + goto slow; + } while (pgdp++, addr = next, addr != end); + } local_irq_enable(); VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT); diff --git a/trunk/arch/powerpc/mm/hash_utils_64.c b/trunk/arch/powerpc/mm/hash_utils_64.c index 50f867d657df..1ade7eb6ae00 100644 --- a/trunk/arch/powerpc/mm/hash_utils_64.c +++ b/trunk/arch/powerpc/mm/hash_utils_64.c @@ -92,7 +92,6 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; struct hash_pte *htab_address; unsigned long htab_size_bytes; unsigned long htab_hash_mask; -EXPORT_SYMBOL_GPL(htab_hash_mask); int mmu_linear_psize = MMU_PAGE_4K; int mmu_virtual_psize = MMU_PAGE_4K; int mmu_vmalloc_psize = MMU_PAGE_4K; @@ -103,7 +102,6 @@ int mmu_io_psize = MMU_PAGE_4K; int mmu_kernel_ssize = MMU_SEGSIZE_256M; int mmu_highuser_ssize = MMU_SEGSIZE_256M; u16 mmu_slb_size = 64; -EXPORT_SYMBOL_GPL(mmu_slb_size); #ifdef CONFIG_HUGETLB_PAGE unsigned int HPAGE_SHIFT; #endif @@ -483,6 +481,16 @@ static void __init htab_init_page_sizes(void) #ifdef CONFIG_HUGETLB_PAGE /* Reserve 16G huge page memory sections for huge pages */ of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); + +/* Set default large page size. Currently, we pick 16M or 1M depending + * on what is available + */ + if (mmu_psize_defs[MMU_PAGE_16M].shift) + HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift; + /* With 4k/4level pagetables, we can't (for now) cope with a + * huge page size < PMD_SIZE */ + else if (mmu_psize_defs[MMU_PAGE_1M].shift) + HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift; #endif /* CONFIG_HUGETLB_PAGE */ } @@ -777,7 +785,7 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) /* page is dirty */ if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { if (trap == 0x400) { - flush_dcache_icache_page(page); + __flush_dcache_icache(page_address(page)); set_bit(PG_arch_1, &page->flags); } else pp |= HPTE_R_N; @@ -835,9 +843,9 @@ void demote_segment_4k(struct mm_struct *mm, unsigned long addr) * Result is 0: full permissions, _PAGE_RW: read-only, * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. */ -static int subpage_protection(struct mm_struct *mm, unsigned long ea) +static int subpage_protection(pgd_t *pgdir, unsigned long ea) { - struct subpage_prot_table *spt = &mm->context.spt; + struct subpage_prot_table *spt = pgd_subpage_prot(pgdir); u32 spp = 0; u32 **sbpm, *sbpp; @@ -865,7 +873,7 @@ static int subpage_protection(struct mm_struct *mm, unsigned long ea) } #else /* CONFIG_PPC_SUBPAGE_PROT */ -static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) +static inline int subpage_protection(pgd_t *pgdir, unsigned long ea) { return 0; } @@ -883,7 +891,6 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) unsigned long vsid; struct mm_struct *mm; pte_t *ptep; - unsigned hugeshift; const struct cpumask *tmp; int rc, user_region = 0, local = 0; int psize, ssize; @@ -936,31 +943,30 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) local = 1; +#ifdef CONFIG_HUGETLB_PAGE + /* Handle hugepage regions */ + if (HPAGE_SHIFT && mmu_huge_psizes[psize]) { + DBG_LOW(" -> huge page !\n"); + return hash_huge_page(mm, access, ea, vsid, local, trap); + } +#endif /* CONFIG_HUGETLB_PAGE */ + #ifndef CONFIG_PPC_64K_PAGES - /* If we use 4K pages and our psize is not 4K, then we might - * be hitting a special driver mapping, and need to align the - * address before we fetch the PTE. - * - * It could also be a hugepage mapping, in which case this is - * not necessary, but it's not harmful, either. + /* If we use 4K pages and our psize is not 4K, then we are hitting + * a special driver mapping, we need to align the address before + * we fetch the PTE */ if (psize != MMU_PAGE_4K) ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); #endif /* CONFIG_PPC_64K_PAGES */ /* Get PTE and page size from page tables */ - ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift); + ptep = find_linux_pte(pgdir, ea); if (ptep == NULL || !pte_present(*ptep)) { DBG_LOW(" no PTE !\n"); return 1; } -#ifdef CONFIG_HUGETLB_PAGE - if (hugeshift) - return __hash_page_huge(ea, access, vsid, ptep, trap, local, - ssize, hugeshift, psize); -#endif /* CONFIG_HUGETLB_PAGE */ - #ifndef CONFIG_PPC_64K_PAGES DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); #else diff --git a/trunk/arch/powerpc/mm/hugetlbpage-hash64.c b/trunk/arch/powerpc/mm/hugetlbpage-hash64.c deleted file mode 100644 index 199539882f92..000000000000 --- a/trunk/arch/powerpc/mm/hugetlbpage-hash64.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later) - * - * Copyright (C) 2003 David Gibson, IBM Corporation. - * - * Based on the IA-32 version: - * Copyright (C) 2002, Rohit Seth - */ - -#include -#include -#include -#include -#include -#include - -int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, - pte_t *ptep, unsigned long trap, int local, int ssize, - unsigned int shift, unsigned int mmu_psize) -{ - unsigned long old_pte, new_pte; - unsigned long va, rflags, pa, sz; - long slot; - int err = 1; - - BUG_ON(shift != mmu_psize_defs[mmu_psize].shift); - - /* Search the Linux page table for a match with va */ - va = hpt_va(ea, vsid, ssize); - - /* - * Check the user's access rights to the page. If access should be - * prevented then send the problem up to do_page_fault. - */ - if (unlikely(access & ~pte_val(*ptep))) - goto out; - /* - * At this point, we have a pte (old_pte) which can be used to build - * or update an HPTE. There are 2 cases: - * - * 1. There is a valid (present) pte with no associated HPTE (this is - * the most common case) - * 2. There is a valid (present) pte with an associated HPTE. The - * current values of the pp bits in the HPTE prevent access - * because we are doing software DIRTY bit management and the - * page is currently not DIRTY. - */ - - - do { - old_pte = pte_val(*ptep); - if (old_pte & _PAGE_BUSY) - goto out; - new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED; - } while(old_pte != __cmpxchg_u64((unsigned long *)ptep, - old_pte, new_pte)); - - rflags = 0x2 | (!(new_pte & _PAGE_RW)); - /* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */ - rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N); - sz = ((1UL) << shift); - if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) - /* No CPU has hugepages but lacks no execute, so we - * don't need to worry about that case */ - rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap); - - /* Check if pte already has an hpte (case 2) */ - if (unlikely(old_pte & _PAGE_HASHPTE)) { - /* There MIGHT be an HPTE for this pte */ - unsigned long hash, slot; - - hash = hpt_hash(va, shift, ssize); - if (old_pte & _PAGE_F_SECOND) - hash = ~hash; - slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; - slot += (old_pte & _PAGE_F_GIX) >> 12; - - if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize, - ssize, local) == -1) - old_pte &= ~_PAGE_HPTEFLAGS; - } - - if (likely(!(old_pte & _PAGE_HASHPTE))) { - unsigned long hash = hpt_hash(va, shift, ssize); - unsigned long hpte_group; - - pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT; - -repeat: - hpte_group = ((hash & htab_hash_mask) * - HPTES_PER_GROUP) & ~0x7UL; - - /* clear HPTE slot informations in new PTE */ -#ifdef CONFIG_PPC_64K_PAGES - new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0; -#else - new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE; -#endif - /* Add in WIMG bits */ - rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE | - _PAGE_COHERENT | _PAGE_GUARDED)); - - /* Insert into the hash table, primary slot */ - slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0, - mmu_psize, ssize); - - /* Primary is full, try the secondary */ - if (unlikely(slot == -1)) { - hpte_group = ((~hash & htab_hash_mask) * - HPTES_PER_GROUP) & ~0x7UL; - slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, - HPTE_V_SECONDARY, - mmu_psize, ssize); - if (slot == -1) { - if (mftb() & 0x1) - hpte_group = ((hash & htab_hash_mask) * - HPTES_PER_GROUP)&~0x7UL; - - ppc_md.hpte_remove(hpte_group); - goto repeat; - } - } - - if (unlikely(slot == -2)) - panic("hash_huge_page: pte_insert failed\n"); - - new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX); - } - - /* - * No need to use ldarx/stdcx here - */ - *ptep = __pte(new_pte & ~_PAGE_BUSY); - - err = 0; - - out: - return err; -} diff --git a/trunk/arch/powerpc/mm/hugetlbpage.c b/trunk/arch/powerpc/mm/hugetlbpage.c index 123f7070238a..90df6ffe3a43 100644 --- a/trunk/arch/powerpc/mm/hugetlbpage.c +++ b/trunk/arch/powerpc/mm/hugetlbpage.c @@ -7,17 +7,29 @@ * Copyright (C) 2002, Rohit Seth */ +#include +#include #include -#include #include -#include +#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include +#include #define PAGE_SHIFT_64K 16 #define PAGE_SHIFT_16M 24 #define PAGE_SHIFT_16G 34 +#define NUM_LOW_AREAS (0x100000000UL >> SID_SHIFT) +#define NUM_HIGH_AREAS (PGTABLE_RANGE >> HTLB_AREA_SHIFT) #define MAX_NUMBER_GPAGES 1024 /* Tracks the 16G pages after the device tree is scanned and before the @@ -25,17 +37,53 @@ static unsigned long gpage_freearray[MAX_NUMBER_GPAGES]; static unsigned nr_gpages; +/* Array of valid huge page sizes - non-zero value(hugepte_shift) is + * stored for the huge page sizes that are valid. + */ +unsigned int mmu_huge_psizes[MMU_PAGE_COUNT] = { }; /* initialize all to 0 */ + +#define hugepte_shift mmu_huge_psizes +#define PTRS_PER_HUGEPTE(psize) (1 << hugepte_shift[psize]) +#define HUGEPTE_TABLE_SIZE(psize) (sizeof(pte_t) << hugepte_shift[psize]) + +#define HUGEPD_SHIFT(psize) (mmu_psize_to_shift(psize) \ + + hugepte_shift[psize]) +#define HUGEPD_SIZE(psize) (1UL << HUGEPD_SHIFT(psize)) +#define HUGEPD_MASK(psize) (~(HUGEPD_SIZE(psize)-1)) + +/* Subtract one from array size because we don't need a cache for 4K since + * is not a huge page size */ +#define HUGE_PGTABLE_INDEX(psize) (HUGEPTE_CACHE_NUM + psize - 1) +#define HUGEPTE_CACHE_NAME(psize) (huge_pgtable_cache_name[psize]) + +static const char *huge_pgtable_cache_name[MMU_PAGE_COUNT] = { + [MMU_PAGE_64K] = "hugepte_cache_64K", + [MMU_PAGE_1M] = "hugepte_cache_1M", + [MMU_PAGE_16M] = "hugepte_cache_16M", + [MMU_PAGE_16G] = "hugepte_cache_16G", +}; + /* Flag to mark huge PD pointers. This means pmd_bad() and pud_bad() * will choke on pointers to hugepte tables, which is handy for * catching screwups early. */ +#define HUGEPD_OK 0x1 + +typedef struct { unsigned long pd; } hugepd_t; + +#define hugepd_none(hpd) ((hpd).pd == 0) static inline int shift_to_mmu_psize(unsigned int shift) { - int psize; - - for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) - if (mmu_psize_defs[psize].shift == shift) - return psize; + switch (shift) { +#ifndef CONFIG_PPC_64K_PAGES + case PAGE_SHIFT_64K: + return MMU_PAGE_64K; +#endif + case PAGE_SHIFT_16M: + return MMU_PAGE_16M; + case PAGE_SHIFT_16G: + return MMU_PAGE_16G; + } return -1; } @@ -46,126 +94,71 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) BUG(); } -#define hugepd_none(hpd) ((hpd).pd == 0) - static inline pte_t *hugepd_page(hugepd_t hpd) { - BUG_ON(!hugepd_ok(hpd)); - return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | 0xc000000000000000); -} - -static inline unsigned int hugepd_shift(hugepd_t hpd) -{ - return hpd.pd & HUGEPD_SHIFT_MASK; + BUG_ON(!(hpd.pd & HUGEPD_OK)); + return (pte_t *)(hpd.pd & ~HUGEPD_OK); } -static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr, unsigned pdshift) +static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr, + struct hstate *hstate) { - unsigned long idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp); + unsigned int shift = huge_page_shift(hstate); + int psize = shift_to_mmu_psize(shift); + unsigned long idx = ((addr >> shift) & (PTRS_PER_HUGEPTE(psize)-1)); pte_t *dir = hugepd_page(*hpdp); return dir + idx; } -pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift) -{ - pgd_t *pg; - pud_t *pu; - pmd_t *pm; - hugepd_t *hpdp = NULL; - unsigned pdshift = PGDIR_SHIFT; - - if (shift) - *shift = 0; - - pg = pgdir + pgd_index(ea); - if (is_hugepd(pg)) { - hpdp = (hugepd_t *)pg; - } else if (!pgd_none(*pg)) { - pdshift = PUD_SHIFT; - pu = pud_offset(pg, ea); - if (is_hugepd(pu)) - hpdp = (hugepd_t *)pu; - else if (!pud_none(*pu)) { - pdshift = PMD_SHIFT; - pm = pmd_offset(pu, ea); - if (is_hugepd(pm)) - hpdp = (hugepd_t *)pm; - else if (!pmd_none(*pm)) { - return pte_offset_map(pm, ea); - } - } - } - - if (!hpdp) - return NULL; - - if (shift) - *shift = hugepd_shift(*hpdp); - return hugepte_offset(hpdp, ea, pdshift); -} - -pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr) -{ - return find_linux_pte_or_hugepte(mm->pgd, addr, NULL); -} - static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp, - unsigned long address, unsigned pdshift, unsigned pshift) + unsigned long address, unsigned int psize) { - pte_t *new = kmem_cache_zalloc(PGT_CACHE(pdshift - pshift), - GFP_KERNEL|__GFP_REPEAT); - - BUG_ON(pshift > HUGEPD_SHIFT_MASK); - BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK); + pte_t *new = kmem_cache_zalloc(pgtable_cache[HUGE_PGTABLE_INDEX(psize)], + GFP_KERNEL|__GFP_REPEAT); if (! new) return -ENOMEM; spin_lock(&mm->page_table_lock); if (!hugepd_none(*hpdp)) - kmem_cache_free(PGT_CACHE(pdshift - pshift), new); + kmem_cache_free(pgtable_cache[HUGE_PGTABLE_INDEX(psize)], new); else - hpdp->pd = ((unsigned long)new & ~0x8000000000000000) | pshift; + hpdp->pd = (unsigned long)new | HUGEPD_OK; spin_unlock(&mm->page_table_lock); return 0; } -pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz) -{ - pgd_t *pg; - pud_t *pu; - pmd_t *pm; - hugepd_t *hpdp = NULL; - unsigned pshift = __ffs(sz); - unsigned pdshift = PGDIR_SHIFT; - - addr &= ~(sz-1); - pg = pgd_offset(mm, addr); - if (pshift >= PUD_SHIFT) { - hpdp = (hugepd_t *)pg; - } else { - pdshift = PUD_SHIFT; - pu = pud_alloc(mm, pg, addr); - if (pshift >= PMD_SHIFT) { - hpdp = (hugepd_t *)pu; - } else { - pdshift = PMD_SHIFT; - pm = pmd_alloc(mm, pu, addr); - hpdp = (hugepd_t *)pm; - } - } - - if (!hpdp) - return NULL; - - BUG_ON(!hugepd_none(*hpdp) && !hugepd_ok(*hpdp)); - - if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, pdshift, pshift)) - return NULL; - - return hugepte_offset(hpdp, addr, pdshift); +static pud_t *hpud_offset(pgd_t *pgd, unsigned long addr, struct hstate *hstate) +{ + if (huge_page_shift(hstate) < PUD_SHIFT) + return pud_offset(pgd, addr); + else + return (pud_t *) pgd; +} +static pud_t *hpud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long addr, + struct hstate *hstate) +{ + if (huge_page_shift(hstate) < PUD_SHIFT) + return pud_alloc(mm, pgd, addr); + else + return (pud_t *) pgd; +} +static pmd_t *hpmd_offset(pud_t *pud, unsigned long addr, struct hstate *hstate) +{ + if (huge_page_shift(hstate) < PMD_SHIFT) + return pmd_offset(pud, addr); + else + return (pmd_t *) pud; +} +static pmd_t *hpmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long addr, + struct hstate *hstate) +{ + if (huge_page_shift(hstate) < PMD_SHIFT) + return pmd_alloc(mm, pud, addr); + else + return (pmd_t *) pud; } /* Build list of addresses of gigantic pages. This function is used in early @@ -199,38 +192,94 @@ int alloc_bootmem_huge_page(struct hstate *hstate) return 1; } + +/* Modelled after find_linux_pte() */ +pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr) +{ + pgd_t *pg; + pud_t *pu; + pmd_t *pm; + + unsigned int psize; + unsigned int shift; + unsigned long sz; + struct hstate *hstate; + psize = get_slice_psize(mm, addr); + shift = mmu_psize_to_shift(psize); + sz = ((1UL) << shift); + hstate = size_to_hstate(sz); + + addr &= hstate->mask; + + pg = pgd_offset(mm, addr); + if (!pgd_none(*pg)) { + pu = hpud_offset(pg, addr, hstate); + if (!pud_none(*pu)) { + pm = hpmd_offset(pu, addr, hstate); + if (!pmd_none(*pm)) + return hugepte_offset((hugepd_t *)pm, addr, + hstate); + } + } + + return NULL; +} + +pte_t *huge_pte_alloc(struct mm_struct *mm, + unsigned long addr, unsigned long sz) +{ + pgd_t *pg; + pud_t *pu; + pmd_t *pm; + hugepd_t *hpdp = NULL; + struct hstate *hstate; + unsigned int psize; + hstate = size_to_hstate(sz); + + psize = get_slice_psize(mm, addr); + BUG_ON(!mmu_huge_psizes[psize]); + + addr &= hstate->mask; + + pg = pgd_offset(mm, addr); + pu = hpud_alloc(mm, pg, addr, hstate); + + if (pu) { + pm = hpmd_alloc(mm, pu, addr, hstate); + if (pm) + hpdp = (hugepd_t *)pm; + } + + if (! hpdp) + return NULL; + + if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, psize)) + return NULL; + + return hugepte_offset(hpdp, addr, hstate); +} + int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep) { return 0; } -static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshift, - unsigned long start, unsigned long end, - unsigned long floor, unsigned long ceiling) +static void free_hugepte_range(struct mmu_gather *tlb, hugepd_t *hpdp, + unsigned int psize) { pte_t *hugepte = hugepd_page(*hpdp); - unsigned shift = hugepd_shift(*hpdp); - unsigned long pdmask = ~((1UL << pdshift) - 1); - - start &= pdmask; - if (start < floor) - return; - if (ceiling) { - ceiling &= pdmask; - if (! ceiling) - return; - } - if (end - 1 > ceiling - 1) - return; hpdp->pd = 0; tlb->need_flush = 1; - pgtable_free_tlb(tlb, hugepte, pdshift - shift); + pgtable_free_tlb(tlb, pgtable_free_cache(hugepte, + HUGEPTE_CACHE_NUM+psize-1, + PGF_CACHENUM_MASK)); } static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud, unsigned long addr, unsigned long end, - unsigned long floor, unsigned long ceiling) + unsigned long floor, unsigned long ceiling, + unsigned int psize) { pmd_t *pmd; unsigned long next; @@ -242,8 +291,7 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud, next = pmd_addr_end(addr, end); if (pmd_none(*pmd)) continue; - free_hugepd_range(tlb, (hugepd_t *)pmd, PMD_SHIFT, - addr, next, floor, ceiling); + free_hugepte_range(tlb, (hugepd_t *)pmd, psize); } while (pmd++, addr = next, addr != end); start &= PUD_MASK; @@ -269,19 +317,23 @@ static void hugetlb_free_pud_range(struct mmu_gather *tlb, pgd_t *pgd, pud_t *pud; unsigned long next; unsigned long start; + unsigned int shift; + unsigned int psize = get_slice_psize(tlb->mm, addr); + shift = mmu_psize_to_shift(psize); start = addr; pud = pud_offset(pgd, addr); do { next = pud_addr_end(addr, end); - if (!is_hugepd(pud)) { + if (shift < PMD_SHIFT) { if (pud_none_or_clear_bad(pud)) continue; hugetlb_free_pmd_range(tlb, pud, addr, next, floor, - ceiling); + ceiling, psize); } else { - free_hugepd_range(tlb, (hugepd_t *)pud, PUD_SHIFT, - addr, next, floor, ceiling); + if (pud_none(*pud)) + continue; + free_hugepte_range(tlb, (hugepd_t *)pud, psize); } } while (pud++, addr = next, addr != end); @@ -312,56 +364,121 @@ void hugetlb_free_pgd_range(struct mmu_gather *tlb, { pgd_t *pgd; unsigned long next; + unsigned long start; /* - * Because there are a number of different possible pagetable - * layouts for hugepage ranges, we limit knowledge of how - * things should be laid out to the allocation path - * (huge_pte_alloc(), above). Everything else works out the - * structure as it goes from information in the hugepd - * pointers. That means that we can't here use the - * optimization used in the normal page free_pgd_range(), of - * checking whether we're actually covering a large enough - * range to have to do anything at the top level of the walk - * instead of at the bottom. + * Comments below take from the normal free_pgd_range(). They + * apply here too. The tests against HUGEPD_MASK below are + * essential, because we *don't* test for this at the bottom + * level. Without them we'll attempt to free a hugepte table + * when we unmap just part of it, even if there are other + * active mappings using it. + * + * The next few lines have given us lots of grief... + * + * Why are we testing HUGEPD* at this top level? Because + * often there will be no work to do at all, and we'd prefer + * not to go all the way down to the bottom just to discover + * that. + * + * Why all these "- 1"s? Because 0 represents both the bottom + * of the address space and the top of it (using -1 for the + * top wouldn't help much: the masks would do the wrong thing). + * The rule is that addr 0 and floor 0 refer to the bottom of + * the address space, but end 0 and ceiling 0 refer to the top + * Comparisons need to use "end - 1" and "ceiling - 1" (though + * that end 0 case should be mythical). * - * To make sense of this, you should probably go read the big - * block comment at the top of the normal free_pgd_range(), - * too. + * Wherever addr is brought up or ceiling brought down, we + * must be careful to reject "the opposite 0" before it + * confuses the subsequent tests. But what about where end is + * brought down by HUGEPD_SIZE below? no, end can't go down to + * 0 there. + * + * Whereas we round start (addr) and ceiling down, by different + * masks at different levels, in order to test whether a table + * now has no other vmas using it, so can be freed, we don't + * bother to round floor or end up - the tests don't need that. */ + unsigned int psize = get_slice_psize(tlb->mm, addr); + + addr &= HUGEPD_MASK(psize); + if (addr < floor) { + addr += HUGEPD_SIZE(psize); + if (!addr) + return; + } + if (ceiling) { + ceiling &= HUGEPD_MASK(psize); + if (!ceiling) + return; + } + if (end - 1 > ceiling - 1) + end -= HUGEPD_SIZE(psize); + if (addr > end - 1) + return; + start = addr; pgd = pgd_offset(tlb->mm, addr); do { + psize = get_slice_psize(tlb->mm, addr); + BUG_ON(!mmu_huge_psizes[psize]); next = pgd_addr_end(addr, end); - if (!is_hugepd(pgd)) { + if (mmu_psize_to_shift(psize) < PUD_SHIFT) { if (pgd_none_or_clear_bad(pgd)) continue; hugetlb_free_pud_range(tlb, pgd, addr, next, floor, ceiling); } else { - free_hugepd_range(tlb, (hugepd_t *)pgd, PGDIR_SHIFT, - addr, next, floor, ceiling); + if (pgd_none(*pgd)) + continue; + free_hugepte_range(tlb, (hugepd_t *)pgd, psize); } } while (pgd++, addr = next, addr != end); } +void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte) +{ + if (pte_present(*ptep)) { + /* We open-code pte_clear because we need to pass the right + * argument to hpte_need_flush (huge / !huge). Might not be + * necessary anymore if we make hpte_need_flush() get the + * page size from the slices + */ + unsigned int psize = get_slice_psize(mm, addr); + unsigned int shift = mmu_psize_to_shift(psize); + unsigned long sz = ((1UL) << shift); + struct hstate *hstate = size_to_hstate(sz); + pte_update(mm, addr & hstate->mask, ptep, ~0UL, 1); + } + *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); +} + +pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, + pte_t *ptep) +{ + unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1); + return __pte(old); +} + struct page * follow_huge_addr(struct mm_struct *mm, unsigned long address, int write) { pte_t *ptep; struct page *page; - unsigned shift; - unsigned long mask; - - ptep = find_linux_pte_or_hugepte(mm->pgd, address, &shift); + unsigned int mmu_psize = get_slice_psize(mm, address); /* Verify it is a huge page else bail. */ - if (!ptep || !shift) + if (!mmu_huge_psizes[mmu_psize]) return ERR_PTR(-EINVAL); - mask = (1UL << shift) - 1; + ptep = huge_pte_offset(mm, address); page = pte_page(*ptep); - if (page) - page += (address & mask) / PAGE_SIZE; + if (page) { + unsigned int shift = mmu_psize_to_shift(mmu_psize); + unsigned long sz = ((1UL) << shift); + page += (address % sz) / PAGE_SIZE; + } return page; } @@ -384,82 +501,6 @@ follow_huge_pmd(struct mm_struct *mm, unsigned long address, return NULL; } -static noinline int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr, - unsigned long end, int write, struct page **pages, int *nr) -{ - unsigned long mask; - unsigned long pte_end; - struct page *head, *page; - pte_t pte; - int refs; - - pte_end = (addr + sz) & ~(sz-1); - if (pte_end < end) - end = pte_end; - - pte = *ptep; - mask = _PAGE_PRESENT | _PAGE_USER; - if (write) - mask |= _PAGE_RW; - - if ((pte_val(pte) & mask) != mask) - return 0; - - /* hugepages are never "special" */ - VM_BUG_ON(!pfn_valid(pte_pfn(pte))); - - refs = 0; - head = pte_page(pte); - - page = head + ((addr & (sz-1)) >> PAGE_SHIFT); - do { - VM_BUG_ON(compound_head(page) != head); - pages[*nr] = page; - (*nr)++; - page++; - refs++; - } while (addr += PAGE_SIZE, addr != end); - - if (!page_cache_add_speculative(head, refs)) { - *nr -= refs; - return 0; - } - - if (unlikely(pte_val(pte) != pte_val(*ptep))) { - /* Could be optimized better */ - while (*nr) { - put_page(page); - (*nr)--; - } - } - - return 1; -} - -static unsigned long hugepte_addr_end(unsigned long addr, unsigned long end, - unsigned long sz) -{ - unsigned long __boundary = (addr + sz) & ~(sz-1); - return (__boundary - 1 < end - 1) ? __boundary : end; -} - -int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, - unsigned long addr, unsigned long end, - int write, struct page **pages, int *nr) -{ - pte_t *ptep; - unsigned long sz = 1UL << hugepd_shift(*hugepd); - unsigned long next; - - ptep = hugepte_offset(hugepd, addr, pdshift); - do { - next = hugepte_addr_end(addr, end, sz); - if (!gup_hugepte(ptep, sz, addr, end, write, pages, nr)) - return 0; - } while (ptep++, addr = next, addr != end); - - return 1; -} unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, @@ -468,6 +509,8 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, struct hstate *hstate = hstate_file(file); int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate)); + if (!mmu_huge_psizes[mmu_psize]) + return -EINVAL; return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0); } @@ -478,46 +521,229 @@ unsigned long vma_mmu_pagesize(struct vm_area_struct *vma) return 1UL << mmu_psize_to_shift(psize); } -static int __init add_huge_page_size(unsigned long long size) +/* + * Called by asm hashtable.S for doing lazy icache flush + */ +static unsigned int hash_huge_page_do_lazy_icache(unsigned long rflags, + pte_t pte, int trap, unsigned long sz) { - int shift = __ffs(size); - int mmu_psize; + struct page *page; + int i; - /* Check that it is a page size supported by the hardware and - * that it fits within pagetable and slice limits. */ - if (!is_power_of_2(size) - || (shift > SLICE_HIGH_SHIFT) || (shift <= PAGE_SHIFT)) - return -EINVAL; + if (!pfn_valid(pte_pfn(pte))) + return rflags; - if ((mmu_psize = shift_to_mmu_psize(shift)) < 0) - return -EINVAL; + page = pte_page(pte); + + /* page is dirty */ + if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { + if (trap == 0x400) { + for (i = 0; i < (sz / PAGE_SIZE); i++) + __flush_dcache_icache(page_address(page+i)); + set_bit(PG_arch_1, &page->flags); + } else { + rflags |= HPTE_R_N; + } + } + return rflags; +} + +int hash_huge_page(struct mm_struct *mm, unsigned long access, + unsigned long ea, unsigned long vsid, int local, + unsigned long trap) +{ + pte_t *ptep; + unsigned long old_pte, new_pte; + unsigned long va, rflags, pa, sz; + long slot; + int err = 1; + int ssize = user_segment_size(ea); + unsigned int mmu_psize; + int shift; + mmu_psize = get_slice_psize(mm, ea); + + if (!mmu_huge_psizes[mmu_psize]) + goto out; + ptep = huge_pte_offset(mm, ea); + + /* Search the Linux page table for a match with va */ + va = hpt_va(ea, vsid, ssize); -#ifdef CONFIG_SPU_FS_64K_LS - /* Disable support for 64K huge pages when 64K SPU local store - * support is enabled as the current implementation conflicts. + /* + * If no pte found or not present, send the problem up to + * do_page_fault */ - if (shift == PAGE_SHIFT_64K) - return -EINVAL; -#endif /* CONFIG_SPU_FS_64K_LS */ + if (unlikely(!ptep || pte_none(*ptep))) + goto out; - BUG_ON(mmu_psize_defs[mmu_psize].shift != shift); + /* + * Check the user's access rights to the page. If access should be + * prevented then send the problem up to do_page_fault. + */ + if (unlikely(access & ~pte_val(*ptep))) + goto out; + /* + * At this point, we have a pte (old_pte) which can be used to build + * or update an HPTE. There are 2 cases: + * + * 1. There is a valid (present) pte with no associated HPTE (this is + * the most common case) + * 2. There is a valid (present) pte with an associated HPTE. The + * current values of the pp bits in the HPTE prevent access + * because we are doing software DIRTY bit management and the + * page is currently not DIRTY. + */ - /* Return if huge page size has already been setup */ - if (size_to_hstate(size)) - return 0; - hugetlb_add_hstate(shift - PAGE_SHIFT); + do { + old_pte = pte_val(*ptep); + if (old_pte & _PAGE_BUSY) + goto out; + new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED; + } while(old_pte != __cmpxchg_u64((unsigned long *)ptep, + old_pte, new_pte)); + + rflags = 0x2 | (!(new_pte & _PAGE_RW)); + /* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */ + rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N); + shift = mmu_psize_to_shift(mmu_psize); + sz = ((1UL) << shift); + if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + /* No CPU has hugepages but lacks no execute, so we + * don't need to worry about that case */ + rflags = hash_huge_page_do_lazy_icache(rflags, __pte(old_pte), + trap, sz); + + /* Check if pte already has an hpte (case 2) */ + if (unlikely(old_pte & _PAGE_HASHPTE)) { + /* There MIGHT be an HPTE for this pte */ + unsigned long hash, slot; + + hash = hpt_hash(va, shift, ssize); + if (old_pte & _PAGE_F_SECOND) + hash = ~hash; + slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; + slot += (old_pte & _PAGE_F_GIX) >> 12; + + if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize, + ssize, local) == -1) + old_pte &= ~_PAGE_HPTEFLAGS; + } - return 0; + if (likely(!(old_pte & _PAGE_HASHPTE))) { + unsigned long hash = hpt_hash(va, shift, ssize); + unsigned long hpte_group; + + pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT; + +repeat: + hpte_group = ((hash & htab_hash_mask) * + HPTES_PER_GROUP) & ~0x7UL; + + /* clear HPTE slot informations in new PTE */ +#ifdef CONFIG_PPC_64K_PAGES + new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0; +#else + new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE; +#endif + /* Add in WIMG bits */ + rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE | + _PAGE_COHERENT | _PAGE_GUARDED)); + + /* Insert into the hash table, primary slot */ + slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0, + mmu_psize, ssize); + + /* Primary is full, try the secondary */ + if (unlikely(slot == -1)) { + hpte_group = ((~hash & htab_hash_mask) * + HPTES_PER_GROUP) & ~0x7UL; + slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, + HPTE_V_SECONDARY, + mmu_psize, ssize); + if (slot == -1) { + if (mftb() & 0x1) + hpte_group = ((hash & htab_hash_mask) * + HPTES_PER_GROUP)&~0x7UL; + + ppc_md.hpte_remove(hpte_group); + goto repeat; + } + } + + if (unlikely(slot == -2)) + panic("hash_huge_page: pte_insert failed\n"); + + new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX); + } + + /* + * No need to use ldarx/stdcx here + */ + *ptep = __pte(new_pte & ~_PAGE_BUSY); + + err = 0; + + out: + return err; +} + +static void __init set_huge_psize(int psize) +{ + /* Check that it is a page size supported by the hardware and + * that it fits within pagetable limits. */ + if (mmu_psize_defs[psize].shift && + mmu_psize_defs[psize].shift < SID_SHIFT_1T && + (mmu_psize_defs[psize].shift > MIN_HUGEPTE_SHIFT || + mmu_psize_defs[psize].shift == PAGE_SHIFT_64K || + mmu_psize_defs[psize].shift == PAGE_SHIFT_16G)) { + /* Return if huge page size has already been setup or is the + * same as the base page size. */ + if (mmu_huge_psizes[psize] || + mmu_psize_defs[psize].shift == PAGE_SHIFT) + return; + if (WARN_ON(HUGEPTE_CACHE_NAME(psize) == NULL)) + return; + hugetlb_add_hstate(mmu_psize_defs[psize].shift - PAGE_SHIFT); + + switch (mmu_psize_defs[psize].shift) { + case PAGE_SHIFT_64K: + /* We only allow 64k hpages with 4k base page, + * which was checked above, and always put them + * at the PMD */ + hugepte_shift[psize] = PMD_SHIFT; + break; + case PAGE_SHIFT_16M: + /* 16M pages can be at two different levels + * of pagestables based on base page size */ + if (PAGE_SHIFT == PAGE_SHIFT_64K) + hugepte_shift[psize] = PMD_SHIFT; + else /* 4k base page */ + hugepte_shift[psize] = PUD_SHIFT; + break; + case PAGE_SHIFT_16G: + /* 16G pages are always at PGD level */ + hugepte_shift[psize] = PGDIR_SHIFT; + break; + } + hugepte_shift[psize] -= mmu_psize_defs[psize].shift; + } else + hugepte_shift[psize] = 0; } static int __init hugepage_setup_sz(char *str) { unsigned long long size; + int mmu_psize; + int shift; size = memparse(str, &str); - if (add_huge_page_size(size) != 0) + shift = __ffs(size); + mmu_psize = shift_to_mmu_psize(shift); + if (mmu_psize >= 0 && mmu_psize_defs[mmu_psize].shift) + set_huge_psize(mmu_psize); + else printk(KERN_WARNING "Invalid huge page size specified(%llu)\n", size); return 1; @@ -526,55 +752,41 @@ __setup("hugepagesz=", hugepage_setup_sz); static int __init hugetlbpage_init(void) { - int psize; + unsigned int psize; if (!cpu_has_feature(CPU_FTR_16M_PAGE)) return -ENODEV; - for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { - unsigned shift; - unsigned pdshift; - - if (!mmu_psize_defs[psize].shift) - continue; - - shift = mmu_psize_to_shift(psize); + /* Add supported huge page sizes. Need to change HUGE_MAX_HSTATE + * and adjust PTE_NONCACHE_NUM if the number of supported huge page + * sizes changes. + */ + set_huge_psize(MMU_PAGE_16M); + set_huge_psize(MMU_PAGE_16G); - if (add_huge_page_size(1ULL << shift) < 0) - continue; + /* Temporarily disable support for 64K huge pages when 64K SPU local + * store support is enabled as the current implementation conflicts. + */ +#ifndef CONFIG_SPU_FS_64K_LS + set_huge_psize(MMU_PAGE_64K); +#endif - if (shift < PMD_SHIFT) - pdshift = PMD_SHIFT; - else if (shift < PUD_SHIFT) - pdshift = PUD_SHIFT; - else - pdshift = PGDIR_SHIFT; - - pgtable_cache_add(pdshift - shift, NULL); - if (!PGT_CACHE(pdshift - shift)) - panic("hugetlbpage_init(): could not create " - "pgtable cache for %d bit pagesize\n", shift); + for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { + if (mmu_huge_psizes[psize]) { + pgtable_cache[HUGE_PGTABLE_INDEX(psize)] = + kmem_cache_create( + HUGEPTE_CACHE_NAME(psize), + HUGEPTE_TABLE_SIZE(psize), + HUGEPTE_TABLE_SIZE(psize), + 0, + NULL); + if (!pgtable_cache[HUGE_PGTABLE_INDEX(psize)]) + panic("hugetlbpage_init(): could not create %s"\ + "\n", HUGEPTE_CACHE_NAME(psize)); + } } - /* Set default large page size. Currently, we pick 16M or 1M - * depending on what is available - */ - if (mmu_psize_defs[MMU_PAGE_16M].shift) - HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift; - else if (mmu_psize_defs[MMU_PAGE_1M].shift) - HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift; - return 0; } module_init(hugetlbpage_init); - -void flush_dcache_icache_hugepage(struct page *page) -{ - int i; - - BUG_ON(!PageCompound(page)); - - for (i = 0; i < (1UL << compound_order(page)); i++) - __flush_dcache_icache(page_address(page+i)); -} diff --git a/trunk/arch/powerpc/mm/init_64.c b/trunk/arch/powerpc/mm/init_64.c index 776f28d02b6b..335c578b9cc3 100644 --- a/trunk/arch/powerpc/mm/init_64.c +++ b/trunk/arch/powerpc/mm/init_64.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include @@ -120,63 +119,30 @@ static void pmd_ctor(void *addr) memset(addr, 0, PMD_TABLE_SIZE); } -struct kmem_cache *pgtable_cache[MAX_PGTABLE_INDEX_SIZE]; - -/* - * Create a kmem_cache() for pagetables. This is not used for PTE - * pages - they're linked to struct page, come from the normal free - * pages pool and have a different entry size (see real_pte_t) to - * everything else. Caches created by this function are used for all - * the higher level pagetables, and for hugepage pagetables. - */ -void pgtable_cache_add(unsigned shift, void (*ctor)(void *)) -{ - char *name; - unsigned long table_size = sizeof(void *) << shift; - unsigned long align = table_size; - - /* When batching pgtable pointers for RCU freeing, we store - * the index size in the low bits. Table alignment must be - * big enough to fit it. - * - * Likewise, hugeapge pagetable pointers contain a (different) - * shift value in the low bits. All tables must be aligned so - * as to leave enough 0 bits in the address to contain it. */ - unsigned long minalign = max(MAX_PGTABLE_INDEX_SIZE + 1, - HUGEPD_SHIFT_MASK + 1); - struct kmem_cache *new; - - /* It would be nice if this was a BUILD_BUG_ON(), but at the - * moment, gcc doesn't seem to recognize is_power_of_2 as a - * constant expression, so so much for that. */ - BUG_ON(!is_power_of_2(minalign)); - BUG_ON((shift < 1) || (shift > MAX_PGTABLE_INDEX_SIZE)); - - if (PGT_CACHE(shift)) - return; /* Already have a cache of this size */ - - align = max_t(unsigned long, align, minalign); - name = kasprintf(GFP_KERNEL, "pgtable-2^%d", shift); - new = kmem_cache_create(name, table_size, align, 0, ctor); - PGT_CACHE(shift) = new; - - pr_debug("Allocated pgtable cache for order %d\n", shift); -} - +static const unsigned int pgtable_cache_size[2] = { + PGD_TABLE_SIZE, PMD_TABLE_SIZE +}; +static const char *pgtable_cache_name[ARRAY_SIZE(pgtable_cache_size)] = { +#ifdef CONFIG_PPC_64K_PAGES + "pgd_cache", "pmd_cache", +#else + "pgd_cache", "pud_pmd_cache", +#endif /* CONFIG_PPC_64K_PAGES */ +}; + +#ifdef CONFIG_HUGETLB_PAGE +/* Hugepages need an extra cache per hugepagesize, initialized in + * hugetlbpage.c. We can't put into the tables above, because HPAGE_SHIFT + * is not compile time constant. */ +struct kmem_cache *pgtable_cache[ARRAY_SIZE(pgtable_cache_size)+MMU_PAGE_COUNT]; +#else +struct kmem_cache *pgtable_cache[ARRAY_SIZE(pgtable_cache_size)]; +#endif void pgtable_cache_init(void) { - pgtable_cache_add(PGD_INDEX_SIZE, pgd_ctor); - pgtable_cache_add(PMD_INDEX_SIZE, pmd_ctor); - if (!PGT_CACHE(PGD_INDEX_SIZE) || !PGT_CACHE(PMD_INDEX_SIZE)) - panic("Couldn't allocate pgtable caches"); - - /* In all current configs, when the PUD index exists it's the - * same size as either the pgd or pmd index. Verify that the - * initialization above has also created a PUD cache. This - * will need re-examiniation if we add new possibilities for - * the pagetable layout. */ - BUG_ON(PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE)); + pgtable_cache[0] = kmem_cache_create(pgtable_cache_name[0], PGD_TABLE_SIZE, PGD_TABLE_SIZE, SLAB_PANIC, pgd_ctor); + pgtable_cache[1] = kmem_cache_create(pgtable_cache_name[1], PMD_TABLE_SIZE, PMD_TABLE_SIZE, SLAB_PANIC, pmd_ctor); } #ifdef CONFIG_SPARSEMEM_VMEMMAP diff --git a/trunk/arch/powerpc/mm/mem.c b/trunk/arch/powerpc/mm/mem.c index b9b152558f9c..59736317bf0e 100644 --- a/trunk/arch/powerpc/mm/mem.c +++ b/trunk/arch/powerpc/mm/mem.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -418,26 +417,18 @@ EXPORT_SYMBOL(flush_dcache_page); void flush_dcache_icache_page(struct page *page) { -#ifdef CONFIG_HUGETLB_PAGE - if (PageCompound(page)) { - flush_dcache_icache_hugepage(page); - return; - } -#endif #ifdef CONFIG_BOOKE - { - void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE); - __flush_dcache_icache(start); - kunmap_atomic(start, KM_PPC_SYNC_ICACHE); - } + void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE); + __flush_dcache_icache(start); + kunmap_atomic(start, KM_PPC_SYNC_ICACHE); #elif defined(CONFIG_8xx) || defined(CONFIG_PPC64) /* On 8xx there is no need to kmap since highmem is not supported */ __flush_dcache_icache(page_address(page)); #else __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); #endif -} +} void clear_user_page(void *page, unsigned long vaddr, struct page *pg) { clear_page(page); diff --git a/trunk/arch/powerpc/mm/mmu_context_hash64.c b/trunk/arch/powerpc/mm/mmu_context_hash64.c index b910d37aea1a..dbeb86ac90cd 100644 --- a/trunk/arch/powerpc/mm/mmu_context_hash64.c +++ b/trunk/arch/powerpc/mm/mmu_context_hash64.c @@ -18,7 +18,6 @@ #include #include #include -#include #include @@ -33,7 +32,7 @@ static DEFINE_IDR(mmu_context_idr); #define NO_CONTEXT 0 #define MAX_CONTEXT ((1UL << 19) - 1) -int __init_new_context(void) +int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int index; int err; @@ -58,41 +57,22 @@ int __init_new_context(void) return -ENOMEM; } - return index; -} -EXPORT_SYMBOL_GPL(__init_new_context); - -int init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - int index; - - index = __init_new_context(); - if (index < 0) - return index; - /* The old code would re-promote on fork, we don't do that * when using slices as it could cause problem promoting slices * that have been forced down to 4K */ if (slice_mm_new_context(mm)) slice_set_user_psize(mm, mmu_virtual_psize); - subpage_prot_init_new_context(mm); mm->context.id = index; return 0; } -void __destroy_context(int context_id) +void destroy_context(struct mm_struct *mm) { spin_lock(&mmu_context_lock); - idr_remove(&mmu_context_idr, context_id); + idr_remove(&mmu_context_idr, mm->context.id); spin_unlock(&mmu_context_lock); -} -EXPORT_SYMBOL_GPL(__destroy_context); -void destroy_context(struct mm_struct *mm) -{ - __destroy_context(mm->context.id); - subpage_prot_free(mm); mm->context.id = NO_CONTEXT; } diff --git a/trunk/arch/powerpc/mm/mmu_decl.h b/trunk/arch/powerpc/mm/mmu_decl.h index e27a990af42d..d2e5321d5ea6 100644 --- a/trunk/arch/powerpc/mm/mmu_decl.h +++ b/trunk/arch/powerpc/mm/mmu_decl.h @@ -98,10 +98,21 @@ extern void _tlbia(void); #ifdef CONFIG_PPC32 +struct tlbcam { + u32 MAS0; + u32 MAS1; + u32 MAS2; + u32 MAS3; + u32 MAS7; +}; + extern void mapin_ram(void); extern int map_page(unsigned long va, phys_addr_t pa, int flags); extern void setbat(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags); +extern void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned int size, int flags, unsigned int pid); +extern void invalidate_tlbcam_entry(int index); extern int __map_without_bats; extern unsigned long ioremap_base; diff --git a/trunk/arch/powerpc/mm/pgtable.c b/trunk/arch/powerpc/mm/pgtable.c index 99df697c601a..53040931de32 100644 --- a/trunk/arch/powerpc/mm/pgtable.c +++ b/trunk/arch/powerpc/mm/pgtable.c @@ -49,12 +49,12 @@ struct pte_freelist_batch { struct rcu_head rcu; unsigned int index; - unsigned long tables[0]; + pgtable_free_t tables[0]; }; #define PTE_FREELIST_SIZE \ ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \ - / sizeof(unsigned long)) + / sizeof(pgtable_free_t)) static void pte_free_smp_sync(void *arg) { @@ -64,13 +64,13 @@ static void pte_free_smp_sync(void *arg) /* This is only called when we are critically out of memory * (and fail to get a page in pte_free_tlb). */ -static void pgtable_free_now(void *table, unsigned shift) +static void pgtable_free_now(pgtable_free_t pgf) { pte_freelist_forced_free++; smp_call_function(pte_free_smp_sync, NULL, 1); - pgtable_free(table, shift); + pgtable_free(pgf); } static void pte_free_rcu_callback(struct rcu_head *head) @@ -79,12 +79,8 @@ static void pte_free_rcu_callback(struct rcu_head *head) container_of(head, struct pte_freelist_batch, rcu); unsigned int i; - for (i = 0; i < batch->index; i++) { - void *table = (void *)(batch->tables[i] & ~MAX_PGTABLE_INDEX_SIZE); - unsigned shift = batch->tables[i] & MAX_PGTABLE_INDEX_SIZE; - - pgtable_free(table, shift); - } + for (i = 0; i < batch->index; i++) + pgtable_free(batch->tables[i]); free_page((unsigned long)batch); } @@ -95,28 +91,25 @@ static void pte_free_submit(struct pte_freelist_batch *batch) call_rcu(&batch->rcu, pte_free_rcu_callback); } -void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift) +void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf) { /* This is safe since tlb_gather_mmu has disabled preemption */ struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur); - unsigned long pgf; if (atomic_read(&tlb->mm->mm_users) < 2 || cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){ - pgtable_free(table, shift); + pgtable_free(pgf); return; } if (*batchp == NULL) { *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC); if (*batchp == NULL) { - pgtable_free_now(table, shift); + pgtable_free_now(pgf); return; } (*batchp)->index = 0; } - BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE); - pgf = (unsigned long)table | shift; (*batchp)->tables[(*batchp)->index++] = pgf; if ((*batchp)->index == PTE_FREELIST_SIZE) { pte_free_submit(*batchp); diff --git a/trunk/arch/powerpc/mm/subpage-prot.c b/trunk/arch/powerpc/mm/subpage-prot.c index a040b81e93bd..4cafc0c33d0a 100644 --- a/trunk/arch/powerpc/mm/subpage-prot.c +++ b/trunk/arch/powerpc/mm/subpage-prot.c @@ -24,9 +24,9 @@ * Also makes sure that the subpage_prot_table structure is * reinitialized for the next user. */ -void subpage_prot_free(struct mm_struct *mm) +void subpage_prot_free(pgd_t *pgd) { - struct subpage_prot_table *spt = &mm->context.spt; + struct subpage_prot_table *spt = pgd_subpage_prot(pgd); unsigned long i, j, addr; u32 **p; @@ -51,13 +51,6 @@ void subpage_prot_free(struct mm_struct *mm) spt->maxaddr = 0; } -void subpage_prot_init_new_context(struct mm_struct *mm) -{ - struct subpage_prot_table *spt = &mm->context.spt; - - memset(spt, 0, sizeof(*spt)); -} - static void hpte_flush_range(struct mm_struct *mm, unsigned long addr, int npages) { @@ -94,7 +87,7 @@ static void hpte_flush_range(struct mm_struct *mm, unsigned long addr, static void subpage_prot_clear(unsigned long addr, unsigned long len) { struct mm_struct *mm = current->mm; - struct subpage_prot_table *spt = &mm->context.spt; + struct subpage_prot_table *spt = pgd_subpage_prot(mm->pgd); u32 **spm, *spp; int i, nw; unsigned long next, limit; @@ -143,7 +136,7 @@ static void subpage_prot_clear(unsigned long addr, unsigned long len) long sys_subpage_prot(unsigned long addr, unsigned long len, u32 __user *map) { struct mm_struct *mm = current->mm; - struct subpage_prot_table *spt = &mm->context.spt; + struct subpage_prot_table *spt = pgd_subpage_prot(mm->pgd); u32 **spm, *spp; int i, nw; unsigned long next, limit; diff --git a/trunk/arch/powerpc/mm/tlb_hash64.c b/trunk/arch/powerpc/mm/tlb_hash64.c index 282d9306361f..2b2f35f6985e 100644 --- a/trunk/arch/powerpc/mm/tlb_hash64.c +++ b/trunk/arch/powerpc/mm/tlb_hash64.c @@ -53,6 +53,11 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, i = batch->index; + /* We mask the address for the base page size. Huge pages will + * have applied their own masking already + */ + addr &= PAGE_MASK; + /* Get page size (maybe move back to caller). * * NOTE: when using special 64K mappings in 4K environment like @@ -70,9 +75,6 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, } else psize = pte_pagesize_index(mm, addr, pte); - /* Mask the address for the correct page size */ - addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1); - /* Build full vaddr */ if (!is_kernel_addr(addr)) { ssize = user_segment_size(addr); diff --git a/trunk/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/trunk/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c index da9b20a63769..a6ce80566625 100644 --- a/trunk/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c +++ b/trunk/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c @@ -79,7 +79,7 @@ cpld_unmask_irq(unsigned int irq) } static struct irq_chip cpld_pic = { - .name = " CPLD PIC ", + .typename = " CPLD PIC ", .mask = cpld_mask_irq, .ack = cpld_mask_irq, .unmask = cpld_unmask_irq, @@ -132,7 +132,7 @@ static int cpld_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq); return 0; } diff --git a/trunk/arch/powerpc/platforms/52xx/Kconfig b/trunk/arch/powerpc/platforms/52xx/Kconfig index 47ea1be1481b..8b8e9560a315 100644 --- a/trunk/arch/powerpc/platforms/52xx/Kconfig +++ b/trunk/arch/powerpc/platforms/52xx/Kconfig @@ -62,8 +62,3 @@ config PPC_MPC5200_GPIO select GENERIC_GPIO help Enable gpiolib support for mpc5200 based boards - -config PPC_MPC5200_LPBFIFO - tristate "MPC5200 LocalPlus bus FIFO driver" - depends on PPC_MPC52xx - select PPC_BESTCOMM_GEN_BD diff --git a/trunk/arch/powerpc/platforms/52xx/Makefile b/trunk/arch/powerpc/platforms/52xx/Makefile index 2bc8cd0c5cfc..bfd4f52cf3dd 100644 --- a/trunk/arch/powerpc/platforms/52xx/Makefile +++ b/trunk/arch/powerpc/platforms/52xx/Makefile @@ -15,4 +15,3 @@ ifeq ($(CONFIG_PPC_LITE5200),y) endif obj-$(CONFIG_PPC_MPC5200_GPIO) += mpc52xx_gpio.o -obj-$(CONFIG_PPC_MPC5200_LPBFIFO) += mpc52xx_lpbfifo.o diff --git a/trunk/arch/powerpc/platforms/52xx/media5200.c b/trunk/arch/powerpc/platforms/52xx/media5200.c index cc0c854291d7..68e4f1696d14 100644 --- a/trunk/arch/powerpc/platforms/52xx/media5200.c +++ b/trunk/arch/powerpc/platforms/52xx/media5200.c @@ -74,7 +74,7 @@ static void media5200_irq_mask(unsigned int virq) } static struct irq_chip media5200_irq_chip = { - .name = "Media5200 FPGA", + .typename = "Media5200 FPGA", .unmask = media5200_irq_unmask, .mask = media5200_irq_mask, .mask_ack = media5200_irq_mask, @@ -114,7 +114,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) static int media5200_irq_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); set_irq_chip_data(virq, &media5200_irq); @@ -127,7 +127,7 @@ static int media5200_irq_map(struct irq_host *h, unsigned int virq, } static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/trunk/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 6f8ebe1085b3..bfbcd418e690 100644 --- a/trunk/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/trunk/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -16,14 +16,8 @@ * output signals or measure input signals. * * This driver supports the GPIO and IRQ controller functions of the GPT - * device. Timer functions are not yet supported. - * - * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used, - * this prevents the use of any gpt0 gpt function (i.e. they will fail with - * -EBUSY). Thus, the safety wdt function always has precedence over the gpt - * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT, - * this means that gpt0 is locked in wdt mode until the next reboot - this - * may be a requirement in safety applications. + * device. Timer functions are not yet supported, nor is the watchdog + * timer. * * To use the GPIO function, the following two properties must be added * to the device tree node for the gpt device (typically in the .dts file @@ -52,24 +46,17 @@ * the output mode. This driver does not change the output mode setting. */ -#include #include #include #include -#include -#include #include #include #include #include -#include -#include -#include -#include #include MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); -MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß"); +MODULE_AUTHOR("Sascha Hauer, Grant Likely"); MODULE_LICENSE("GPL"); /** @@ -79,27 +66,18 @@ MODULE_LICENSE("GPL"); * @lock: spinlock to coordinate between different functions. * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported - * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates - * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates - * if the timer is actively used as wdt which blocks gpt functions */ struct mpc52xx_gpt_priv { - struct list_head list; /* List of all GPT devices */ struct device *dev; struct mpc52xx_gpt __iomem *regs; spinlock_t lock; struct irq_host *irqhost; - u32 ipb_freq; - u8 wdt_mode; #if defined(CONFIG_GPIOLIB) struct of_gpio_chip of_gc; #endif }; -LIST_HEAD(mpc52xx_gpt_list); -DEFINE_MUTEX(mpc52xx_gpt_list_mutex); - #define MPC52xx_GPT_MODE_MS_MASK (0x07) #define MPC52xx_GPT_MODE_MS_IC (0x01) #define MPC52xx_GPT_MODE_MS_OC (0x02) @@ -110,25 +88,15 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex); #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) -#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000) -#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400) -#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200) #define MPC52xx_GPT_MODE_IRQ_EN (0x0100) -#define MPC52xx_GPT_MODE_WDT_EN (0x8000) #define MPC52xx_GPT_MODE_ICT_MASK (0x030000) #define MPC52xx_GPT_MODE_ICT_RISING (0x010000) #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) -#define MPC52xx_GPT_MODE_WDT_PING (0xa5) - #define MPC52xx_GPT_STATUS_IRQMASK (0x000f) -#define MPC52xx_GPT_CAN_WDT (1 << 0) -#define MPC52xx_GPT_IS_WDT (1 << 1) - - /* --------------------------------------------------------------------- * Cascaded interrupt controller hooks */ @@ -181,7 +149,7 @@ static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type) } static struct irq_chip mpc52xx_gpt_irq_chip = { - .name = "MPC52xx GPT", + .typename = "MPC52xx GPT", .unmask = mpc52xx_gpt_irq_unmask, .mask = mpc52xx_gpt_irq_mask, .ack = mpc52xx_gpt_irq_ack, @@ -214,7 +182,7 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, } static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { @@ -222,7 +190,7 @@ static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); - if ((intsize < 1) || (intspec[0] > 3)) { + if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) { dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name); return -EINVAL; } @@ -243,12 +211,14 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) { int cascade_virq; unsigned long flags; - u32 mode; - cascade_virq = irq_of_parse_and_map(node, 0); - if (!cascade_virq) + /* Only setup cascaded IRQ if device tree claims the GPT is + * an interrupt controller */ + if (!of_find_property(node, "interrupt-controller", NULL)) return; + cascade_virq = irq_of_parse_and_map(node, 0); + gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1, &mpc52xx_gpt_irq_ops, -1); if (!gpt->irqhost) { @@ -257,16 +227,14 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) } gpt->irqhost->host_data = gpt; + set_irq_data(cascade_virq, gpt); set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); - /* If the GPT is currently disabled, then change it to be in Input - * Capture mode. If the mode is non-zero, then the pin could be - * already in use for something. */ + /* Set to Input Capture mode */ spin_lock_irqsave(&gpt->lock, flags); - mode = in_be32(&gpt->regs->mode); - if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0) - out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC); + clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, + MPC52xx_GPT_MODE_MS_IC); spin_unlock_irqrestore(&gpt->lock, flags); dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); @@ -367,354 +335,6 @@ static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } #endif /* defined(CONFIG_GPIOLIB) */ -/*********************************************************************** - * Timer API - */ - -/** - * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number - * @irq: irq of timer. - */ -struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq) -{ - struct mpc52xx_gpt_priv *gpt; - struct list_head *pos; - - /* Iterate over the list of timers looking for a matching device */ - mutex_lock(&mpc52xx_gpt_list_mutex); - list_for_each(pos, &mpc52xx_gpt_list) { - gpt = container_of(pos, struct mpc52xx_gpt_priv, list); - if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) { - mutex_unlock(&mpc52xx_gpt_list_mutex); - return gpt; - } - } - mutex_unlock(&mpc52xx_gpt_list_mutex); - - return NULL; -} -EXPORT_SYMBOL(mpc52xx_gpt_from_irq); - -static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period, - int continuous, int as_wdt) -{ - u32 clear, set; - u64 clocks; - u32 prescale; - unsigned long flags; - - clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS; - set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE; - if (as_wdt) { - clear |= MPC52xx_GPT_MODE_IRQ_EN; - set |= MPC52xx_GPT_MODE_WDT_EN; - } else if (continuous) - set |= MPC52xx_GPT_MODE_CONTINUOUS; - - /* Determine the number of clocks in the requested period. 64 bit - * arithmatic is done here to preserve the precision until the value - * is scaled back down into the u32 range. Period is in 'ns', bus - * frequency is in Hz. */ - clocks = period * (u64)gpt->ipb_freq; - do_div(clocks, 1000000000); /* Scale it down to ns range */ - - /* This device cannot handle a clock count greater than 32 bits */ - if (clocks > 0xffffffff) - return -EINVAL; - - /* Calculate the prescaler and count values from the clocks value. - * 'clocks' is the number of clock ticks in the period. The timer - * has 16 bit precision and a 16 bit prescaler. Prescaler is - * calculated by integer dividing the clocks by 0x10000 (shifting - * down 16 bits) to obtain the smallest possible divisor for clocks - * to get a 16 bit count value. - * - * Note: the prescale register is '1' based, not '0' based. ie. a - * value of '1' means divide the clock by one. 0xffff divides the - * clock by 0xffff. '0x0000' does not divide by zero, but wraps - * around and divides by 0x10000. That is why prescale must be - * a u32 variable, not a u16, for this calculation. */ - prescale = (clocks >> 16) + 1; - do_div(clocks, prescale); - if (clocks > 0xffff) { - pr_err("calculation error; prescale:%x clocks:%llx\n", - prescale, clocks); - return -EINVAL; - } - - /* Set and enable the timer, reject an attempt to use a wdt as gpt */ - spin_lock_irqsave(&gpt->lock, flags); - if (as_wdt) - gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; - else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { - spin_unlock_irqrestore(&gpt->lock, flags); - return -EBUSY; - } - out_be32(&gpt->regs->count, prescale << 16 | clocks); - clrsetbits_be32(&gpt->regs->mode, clear, set); - spin_unlock_irqrestore(&gpt->lock, flags); - - return 0; -} - -/** - * mpc52xx_gpt_start_timer - Set and enable the GPT timer - * @gpt: Pointer to gpt private data structure - * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock - * @continuous: set to 1 to make timer continuous free running - * - * An interrupt will be generated every time the timer fires - */ -int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period, - int continuous) -{ - return mpc52xx_gpt_do_start(gpt, period, continuous, 0); -} -EXPORT_SYMBOL(mpc52xx_gpt_start_timer); - -/** - * mpc52xx_gpt_stop_timer - Stop a gpt - * @gpt: Pointer to gpt private data structure - * - * Returns an error if attempting to stop a wdt - */ -int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) -{ - unsigned long flags; - - /* reject the operation if the timer is used as watchdog (gpt 0 only) */ - spin_lock_irqsave(&gpt->lock, flags); - if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { - spin_unlock_irqrestore(&gpt->lock, flags); - return -EBUSY; - } - - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); - spin_unlock_irqrestore(&gpt->lock, flags); - return 0; -} -EXPORT_SYMBOL(mpc52xx_gpt_stop_timer); - -/** - * mpc52xx_gpt_timer_period - Read the timer period - * @gpt: Pointer to gpt private data structure - * - * Returns the timer period in ns - */ -u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt) -{ - u64 period; - u64 prescale; - unsigned long flags; - - spin_lock_irqsave(&gpt->lock, flags); - period = in_be32(&gpt->regs->count); - spin_unlock_irqrestore(&gpt->lock, flags); - - prescale = period >> 16; - period &= 0xffff; - if (prescale == 0) - prescale = 0x10000; - period = period * prescale * 1000000000ULL; - do_div(period, (u64)gpt->ipb_freq); - return period; -} -EXPORT_SYMBOL(mpc52xx_gpt_timer_period); - -#if defined(CONFIG_MPC5200_WDT) -/*********************************************************************** - * Watchdog API for gpt0 - */ - -#define WDT_IDENTITY "mpc52xx watchdog on GPT0" - -/* wdt_is_active stores wether or not the /dev/watchdog device is opened */ -static unsigned long wdt_is_active; - -/* wdt-capable gpt */ -static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt; - -/* low-level wdt functions */ -static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt) -{ - unsigned long flags; - - spin_lock_irqsave(&gpt_wdt->lock, flags); - out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING); - spin_unlock_irqrestore(&gpt_wdt->lock, flags); -} - -/* wdt misc device api */ -static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; - mpc52xx_gpt_wdt_ping(gpt_wdt); - return 0; -} - -static struct watchdog_info mpc5200_wdt_info = { - .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, - .identity = WDT_IDENTITY, -}; - -static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; - int __user *data = (int __user *)arg; - int timeout; - u64 real_timeout; - int ret = 0; - - switch (cmd) { - case WDIOC_GETSUPPORT: - ret = copy_to_user(data, &mpc5200_wdt_info, - sizeof(mpc5200_wdt_info)); - if (ret) - ret = -EFAULT; - break; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - ret = put_user(0, data); - break; - - case WDIOC_KEEPALIVE: - mpc52xx_gpt_wdt_ping(gpt_wdt); - break; - - case WDIOC_SETTIMEOUT: - ret = get_user(timeout, data); - if (ret) - break; - real_timeout = (u64) timeout * 1000000000ULL; - ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1); - if (ret) - break; - /* fall through and return the timeout */ - - case WDIOC_GETTIMEOUT: - /* we need to round here as to avoid e.g. the following - * situation: - * - timeout requested is 1 second; - * - real timeout @33MHz is 999997090ns - * - the int divide by 10^9 will return 0. - */ - real_timeout = - mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL; - do_div(real_timeout, 1000000000ULL); - timeout = (int) real_timeout; - ret = put_user(timeout, data); - break; - - default: - ret = -ENOTTY; - } - return ret; -} - -static int mpc52xx_wdt_open(struct inode *inode, struct file *file) -{ - int ret; - - /* sanity check */ - if (!mpc52xx_gpt_wdt) - return -ENODEV; - - /* /dev/watchdog can only be opened once */ - if (test_and_set_bit(0, &wdt_is_active)) - return -EBUSY; - - /* Set and activate the watchdog with 30 seconds timeout */ - ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL, - 0, 1); - if (ret) { - clear_bit(0, &wdt_is_active); - return ret; - } - - file->private_data = mpc52xx_gpt_wdt; - return nonseekable_open(inode, file); -} - -static int mpc52xx_wdt_release(struct inode *inode, struct file *file) -{ - /* note: releasing the wdt in NOWAYOUT-mode does not stop it */ -#if !defined(CONFIG_WATCHDOG_NOWAYOUT) - struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; - unsigned long flags; - - spin_lock_irqsave(&gpt_wdt->lock, flags); - clrbits32(&gpt_wdt->regs->mode, - MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); - gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; - spin_unlock_irqrestore(&gpt_wdt->lock, flags); -#endif - clear_bit(0, &wdt_is_active); - return 0; -} - - -static const struct file_operations mpc52xx_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = mpc52xx_wdt_write, - .unlocked_ioctl = mpc52xx_wdt_ioctl, - .open = mpc52xx_wdt_open, - .release = mpc52xx_wdt_release, -}; - -static struct miscdevice mpc52xx_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &mpc52xx_wdt_fops, -}; - -static int __devinit mpc52xx_gpt_wdt_init(void) -{ - int err; - - /* try to register the watchdog misc device */ - err = misc_register(&mpc52xx_wdt_miscdev); - if (err) - pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY); - else - pr_info("%s: watchdog device registered\n", WDT_IDENTITY); - return err; -} - -static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, - const u32 *period) -{ - u64 real_timeout; - - /* remember the gpt for the wdt operation */ - mpc52xx_gpt_wdt = gpt; - - /* configure the wdt if the device tree contained a timeout */ - if (!period || *period == 0) - return 0; - - real_timeout = (u64) *period * 1000000000ULL; - if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1)) - dev_warn(gpt->dev, "starting as wdt failed\n"); - else - dev_info(gpt->dev, "watchdog set to %us timeout\n", *period); - return 0; -} - -#else - -static int __devinit mpc52xx_gpt_wdt_init(void) -{ - return 0; -} - -#define mpc52xx_gpt_wdt_setup(x, y) (0) - -#endif /* CONFIG_MPC5200_WDT */ - /* --------------------------------------------------------------------- * of_platform bus binding code */ @@ -729,7 +349,6 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev, spin_lock_init(&gpt->lock); gpt->dev = &ofdev->dev; - gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->node); gpt->regs = of_iomap(ofdev->node, 0); if (!gpt->regs) { kfree(gpt); @@ -741,26 +360,6 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev, mpc52xx_gpt_gpio_setup(gpt, ofdev->node); mpc52xx_gpt_irq_setup(gpt, ofdev->node); - mutex_lock(&mpc52xx_gpt_list_mutex); - list_add(&gpt->list, &mpc52xx_gpt_list); - mutex_unlock(&mpc52xx_gpt_list_mutex); - - /* check if this device could be a watchdog */ - if (of_get_property(ofdev->node, "fsl,has-wdt", NULL) || - of_get_property(ofdev->node, "has-wdt", NULL)) { - const u32 *on_boot_wdt; - - gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; - on_boot_wdt = of_get_property(ofdev->node, "fsl,wdt-on-boot", - NULL); - if (on_boot_wdt) { - dev_info(gpt->dev, "used as watchdog\n"); - gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; - } else - dev_info(gpt->dev, "can function as watchdog\n"); - mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt); - } - return 0; } @@ -795,4 +394,3 @@ static int __init mpc52xx_gpt_init(void) /* Make sure GPIOs and IRQs get set up before anyone tries to use them */ subsys_initcall(mpc52xx_gpt_init); -device_initcall(mpc52xx_gpt_wdt_init); diff --git a/trunk/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/trunk/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c deleted file mode 100644 index 929d017535a3..000000000000 --- a/trunk/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * LocalPlus Bus FIFO driver for the Freescale MPC52xx. - * - * Copyright (C) 2009 Secret Lab Technologies Ltd. - * - * This file is released under the GPLv2 - * - * Todo: - * - Add support for multiple requests to be queued. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -MODULE_AUTHOR("Grant Likely "); -MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver"); -MODULE_LICENSE("GPL"); - -#define LPBFIFO_REG_PACKET_SIZE (0x00) -#define LPBFIFO_REG_START_ADDRESS (0x04) -#define LPBFIFO_REG_CONTROL (0x08) -#define LPBFIFO_REG_ENABLE (0x0C) -#define LPBFIFO_REG_BYTES_DONE_STATUS (0x14) -#define LPBFIFO_REG_FIFO_DATA (0x40) -#define LPBFIFO_REG_FIFO_STATUS (0x44) -#define LPBFIFO_REG_FIFO_CONTROL (0x48) -#define LPBFIFO_REG_FIFO_ALARM (0x4C) - -struct mpc52xx_lpbfifo { - struct device *dev; - phys_addr_t regs_phys; - void __iomem *regs; - int irq; - spinlock_t lock; - - struct bcom_task *bcom_tx_task; - struct bcom_task *bcom_rx_task; - struct bcom_task *bcom_cur_task; - - /* Current state data */ - struct mpc52xx_lpbfifo_request *req; - int dma_irqs_enabled; -}; - -/* The MPC5200 has only one fifo, so only need one instance structure */ -static struct mpc52xx_lpbfifo lpbfifo; - -/** - * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transfered - */ -static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req) -{ - size_t transfer_size = req->size - req->pos; - struct bcom_bd *bd; - void __iomem *reg; - u32 *data; - int i; - int bit_fields; - int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA); - int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE; - int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA; - - /* Set and clear the reset bits; is good practice in User Manual */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000); - - /* set master enable bit */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000001); - if (!dma) { - /* While the FIFO can be setup for transfer sizes as large as - * 16M-1, the FIFO itself is only 512 bytes deep and it does - * not generate interrupts for FIFO full events (only transfer - * complete will raise an IRQ). Therefore when not using - * Bestcomm to drive the FIFO it needs to either be polled, or - * transfers need to constrained to the size of the fifo. - * - * This driver restricts the size of the transfer - */ - if (transfer_size > 512) - transfer_size = 512; - - /* Load the FIFO with data */ - if (write) { - reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA; - data = req->data + req->pos; - for (i = 0; i < transfer_size; i += 4) - out_be32(reg, *data++); - } - - /* Unmask both error and completion irqs */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000301); - } else { - /* Choose the correct direction - * - * Configure the watermarks so DMA will always complete correctly. - * It may be worth experimenting with the ALARM value to see if - * there is a performance impacit. However, if it is wrong there - * is a risk of DMA not transferring the last chunk of data - */ - if (write) { - out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1e4); - out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7); - lpbfifo.bcom_cur_task = lpbfifo.bcom_tx_task; - } else { - out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1ff); - out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0); - lpbfifo.bcom_cur_task = lpbfifo.bcom_rx_task; - - if (poll_dma) { - if (lpbfifo.dma_irqs_enabled) { - disable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task)); - lpbfifo.dma_irqs_enabled = 0; - } - } else { - if (!lpbfifo.dma_irqs_enabled) { - enable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task)); - lpbfifo.dma_irqs_enabled = 1; - } - } - } - - bd = bcom_prepare_next_buffer(lpbfifo.bcom_cur_task); - bd->status = transfer_size; - if (!write) { - /* - * In the DMA read case, the DMA doesn't complete, - * possibly due to incorrect watermarks in the ALARM - * and CONTROL regs. For now instead of trying to - * determine the right watermarks that will make this - * work, just increase the number of bytes the FIFO is - * expecting. - * - * When submitting another operation, the FIFO will get - * reset, so the condition of the FIFO waiting for a - * non-existent 4 bytes will get cleared. - */ - transfer_size += 4; /* BLECH! */ - } - bd->data[0] = req->data_phys + req->pos; - bcom_submit_next_buffer(lpbfifo.bcom_cur_task, NULL); - - /* error irq & master enabled bit */ - bit_fields = 0x00000201; - - /* Unmask irqs */ - if (write && (!poll_dma)) - bit_fields |= 0x00000100; /* completion irq too */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, bit_fields); - } - - /* Set transfer size, width, chip select and READ mode */ - out_be32(lpbfifo.regs + LPBFIFO_REG_START_ADDRESS, - req->offset + req->pos); - out_be32(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, transfer_size); - - bit_fields = req->cs << 24 | 0x000008; - if (!write) - bit_fields |= 0x010000; /* read mode */ - out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields); - - /* Kick it off */ - out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01); - if (dma) - bcom_enable(lpbfifo.bcom_cur_task); -} - -/** - * mpc52xx_lpbfifo_irq - IRQ handler for LPB FIFO - * - * On transmit, the dma completion irq triggers before the fifo completion - * triggers. Handle the dma completion here instead of the LPB FIFO Bestcomm - * task completion irq becuase everyting is not really done until the LPB FIFO - * completion irq triggers. - * - * In other words: - * For DMA, on receive, the "Fat Lady" is the bestcom completion irq. on - * transmit, the fifo completion irq is the "Fat Lady". The opera (or in this - * case the DMA/FIFO operation) is not finished until the "Fat Lady" sings. - * - * Reasons for entering this routine: - * 1) PIO mode rx and tx completion irq - * 2) DMA interrupt mode tx completion irq - * 3) DMA polled mode tx - * - * Exit conditions: - * 1) Transfer aborted - * 2) FIFO complete without DMA; more data to do - * 3) FIFO complete without DMA; all data transfered - * 4) FIFO complete using DMA - * - * Condition 1 can occur regardless of whether or not DMA is used. - * It requires executing the callback to report the error and exiting - * immediately. - * - * Condition 2 requires programming the FIFO with the next block of data - * - * Condition 3 requires executing the callback to report completion - * - * Condition 4 means the same as 3, except that we also retrieve the bcom - * buffer so DMA doesn't get clogged up. - * - * To make things trickier, the spinlock must be dropped before - * executing the callback, otherwise we could end up with a deadlock - * or nested spinlock condition. The out path is non-trivial, so - * extra fiddling is done to make sure all paths lead to the same - * outbound code. - */ -static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id) -{ - struct mpc52xx_lpbfifo_request *req; - u32 status = in_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS); - void __iomem *reg; - u32 *data; - int count, i; - int do_callback = 0; - u32 ts; - unsigned long flags; - int dma, write, poll_dma; - - spin_lock_irqsave(&lpbfifo.lock, flags); - ts = get_tbl(); - - req = lpbfifo.req; - if (!req) { - spin_unlock_irqrestore(&lpbfifo.lock, flags); - pr_err("bogus LPBFIFO IRQ\n"); - return IRQ_HANDLED; - } - - dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA); - write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE; - poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA; - - if (dma && !write) { - spin_unlock_irqrestore(&lpbfifo.lock, flags); - pr_err("bogus LPBFIFO IRQ (dma and not writting)\n"); - return IRQ_HANDLED; - } - - if ((status & 0x01) == 0) { - goto out; - } - - /* check abort bit */ - if (status & 0x10) { - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000); - do_callback = 1; - goto out; - } - - /* Read result from hardware */ - count = in_be32(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS); - count &= 0x00ffffff; - - if (!dma && !write) { - /* copy the data out of the FIFO */ - reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA; - data = req->data + req->pos; - for (i = 0; i < count; i += 4) - *data++ = in_be32(reg); - } - - /* Update transfer position and count */ - req->pos += count; - - /* Decide what to do next */ - if (req->size - req->pos) - mpc52xx_lpbfifo_kick(req); /* more work to do */ - else - do_callback = 1; - - out: - /* Clear the IRQ */ - out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01); - - if (dma && (status & 0x11)) { - /* - * Count the DMA as complete only when the FIFO completion - * status or abort bits are set. - * - * (status & 0x01) should always be the case except sometimes - * when using polled DMA. - * - * (status & 0x10) {transfer aborted}: This case needs more - * testing. - */ - bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL); - } - req->last_byte = ((u8 *)req->data)[req->size - 1]; - - /* When the do_callback flag is set; it means the transfer is finished - * so set the FIFO as idle */ - if (do_callback) - lpbfifo.req = NULL; - - if (irq != 0) /* don't increment on polled case */ - req->irq_count++; - - req->irq_ticks += get_tbl() - ts; - spin_unlock_irqrestore(&lpbfifo.lock, flags); - - /* Spinlock is released; it is now safe to call the callback */ - if (do_callback && req->callback) - req->callback(req); - - return IRQ_HANDLED; -} - -/** - * mpc52xx_lpbfifo_bcom_irq - IRQ handler for LPB FIFO Bestcomm task - * - * Only used when receiving data. - */ -static irqreturn_t mpc52xx_lpbfifo_bcom_irq(int irq, void *dev_id) -{ - struct mpc52xx_lpbfifo_request *req; - unsigned long flags; - u32 status; - u32 ts; - - spin_lock_irqsave(&lpbfifo.lock, flags); - ts = get_tbl(); - - req = lpbfifo.req; - if (!req || (req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA)) { - spin_unlock_irqrestore(&lpbfifo.lock, flags); - return IRQ_HANDLED; - } - - if (irq != 0) /* don't increment on polled case */ - req->irq_count++; - - if (!bcom_buffer_done(lpbfifo.bcom_cur_task)) { - spin_unlock_irqrestore(&lpbfifo.lock, flags); - - req->buffer_not_done_cnt++; - if ((req->buffer_not_done_cnt % 1000) == 0) - pr_err("transfer stalled\n"); - - return IRQ_HANDLED; - } - - bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL); - - req->last_byte = ((u8 *)req->data)[req->size - 1]; - - req->pos = status & 0x00ffffff; - - /* Mark the FIFO as idle */ - lpbfifo.req = NULL; - - /* Release the lock before calling out to the callback. */ - req->irq_ticks += get_tbl() - ts; - spin_unlock_irqrestore(&lpbfifo.lock, flags); - - if (req->callback) - req->callback(req); - - return IRQ_HANDLED; -} - -/** - * mpc52xx_lpbfifo_bcom_poll - Poll for DMA completion - */ -void mpc52xx_lpbfifo_poll(void) -{ - struct mpc52xx_lpbfifo_request *req = lpbfifo.req; - int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA); - int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE; - - /* - * For more information, see comments on the "Fat Lady" - */ - if (dma && write) - mpc52xx_lpbfifo_irq(0, NULL); - else - mpc52xx_lpbfifo_bcom_irq(0, NULL); -} -EXPORT_SYMBOL(mpc52xx_lpbfifo_poll); - -/** - * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request. - * @req: Pointer to request structure - */ -int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req) -{ - unsigned long flags; - - if (!lpbfifo.regs) - return -ENODEV; - - spin_lock_irqsave(&lpbfifo.lock, flags); - - /* If the req pointer is already set, then a transfer is in progress */ - if (lpbfifo.req) { - spin_unlock_irqrestore(&lpbfifo.lock, flags); - return -EBUSY; - } - - /* Setup the transfer */ - lpbfifo.req = req; - req->irq_count = 0; - req->irq_ticks = 0; - req->buffer_not_done_cnt = 0; - req->pos = 0; - - mpc52xx_lpbfifo_kick(req); - spin_unlock_irqrestore(&lpbfifo.lock, flags); - return 0; -} -EXPORT_SYMBOL(mpc52xx_lpbfifo_submit); - -void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req) -{ - unsigned long flags; - - spin_lock_irqsave(&lpbfifo.lock, flags); - if (lpbfifo.req == req) { - /* Put it into reset and clear the state */ - bcom_gen_bd_rx_reset(lpbfifo.bcom_rx_task); - bcom_gen_bd_tx_reset(lpbfifo.bcom_tx_task); - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000); - lpbfifo.req = NULL; - } - spin_unlock_irqrestore(&lpbfifo.lock, flags); -} -EXPORT_SYMBOL(mpc52xx_lpbfifo_abort); - -static int __devinit -mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match) -{ - struct resource res; - int rc = -ENOMEM; - - if (lpbfifo.dev != NULL) - return -ENOSPC; - - lpbfifo.irq = irq_of_parse_and_map(op->node, 0); - if (!lpbfifo.irq) - return -ENODEV; - - if (of_address_to_resource(op->node, 0, &res)) - return -ENODEV; - lpbfifo.regs_phys = res.start; - lpbfifo.regs = of_iomap(op->node, 0); - if (!lpbfifo.regs) - return -ENOMEM; - - spin_lock_init(&lpbfifo.lock); - - /* Put FIFO into reset */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000); - - /* Register the interrupt handler */ - rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0, - "mpc52xx-lpbfifo", &lpbfifo); - if (rc) - goto err_irq; - - /* Request the Bestcomm receive (fifo --> memory) task and IRQ */ - lpbfifo.bcom_rx_task = - bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA, - BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC, - 16*1024*1024); - if (!lpbfifo.bcom_rx_task) - goto err_bcom_rx; - - rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), - mpc52xx_lpbfifo_bcom_irq, 0, - "mpc52xx-lpbfifo-rx", &lpbfifo); - if (rc) - goto err_bcom_rx_irq; - - /* Request the Bestcomm transmit (memory --> fifo) task and IRQ */ - lpbfifo.bcom_tx_task = - bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA, - BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC); - if (!lpbfifo.bcom_tx_task) - goto err_bcom_tx; - - lpbfifo.dev = &op->dev; - return 0; - - err_bcom_tx: - free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo); - err_bcom_rx_irq: - bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task); - err_bcom_rx: - err_irq: - iounmap(lpbfifo.regs); - lpbfifo.regs = NULL; - - dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n"); - return -ENODEV; -} - - -static int __devexit mpc52xx_lpbfifo_remove(struct of_device *op) -{ - if (lpbfifo.dev != &op->dev) - return 0; - - /* Put FIFO in reset */ - out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000); - - /* Release the bestcomm transmit task */ - free_irq(bcom_get_task_irq(lpbfifo.bcom_tx_task), &lpbfifo); - bcom_gen_bd_tx_release(lpbfifo.bcom_tx_task); - - /* Release the bestcomm receive task */ - free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo); - bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task); - - free_irq(lpbfifo.irq, &lpbfifo); - iounmap(lpbfifo.regs); - lpbfifo.regs = NULL; - lpbfifo.dev = NULL; - - return 0; -} - -static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = { - { .compatible = "fsl,mpc5200-lpbfifo", }, - {}, -}; - -static struct of_platform_driver mpc52xx_lpbfifo_driver = { - .owner = THIS_MODULE, - .name = "mpc52xx-lpbfifo", - .match_table = mpc52xx_lpbfifo_match, - .probe = mpc52xx_lpbfifo_probe, - .remove = __devexit_p(mpc52xx_lpbfifo_remove), -}; - -/*********************************************************************** - * Module init/exit - */ -static int __init mpc52xx_lpbfifo_init(void) -{ - pr_debug("Registering LocalPlus bus FIFO driver\n"); - return of_register_platform_driver(&mpc52xx_lpbfifo_driver); -} -module_init(mpc52xx_lpbfifo_init); - -static void __exit mpc52xx_lpbfifo_exit(void) -{ - pr_debug("Unregistering LocalPlus bus FIFO driver\n"); - of_unregister_platform_driver(&mpc52xx_lpbfifo_driver); -} -module_exit(mpc52xx_lpbfifo_exit); diff --git a/trunk/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/trunk/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 4bf4bf7b063e..480f806fd0a9 100644 --- a/trunk/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/trunk/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -220,7 +220,7 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) } static struct irq_chip mpc52xx_extirq_irqchip = { - .name = "MPC52xx External", + .typename = "MPC52xx External", .mask = mpc52xx_extirq_mask, .unmask = mpc52xx_extirq_unmask, .ack = mpc52xx_extirq_ack, @@ -258,7 +258,7 @@ static void mpc52xx_main_unmask(unsigned int virq) } static struct irq_chip mpc52xx_main_irqchip = { - .name = "MPC52xx Main", + .typename = "MPC52xx Main", .mask = mpc52xx_main_mask, .mask_ack = mpc52xx_main_mask, .unmask = mpc52xx_main_unmask, @@ -291,7 +291,7 @@ static void mpc52xx_periph_unmask(unsigned int virq) } static struct irq_chip mpc52xx_periph_irqchip = { - .name = "MPC52xx Peripherals", + .typename = "MPC52xx Peripherals", .mask = mpc52xx_periph_mask, .mask_ack = mpc52xx_periph_mask, .unmask = mpc52xx_periph_unmask, @@ -335,7 +335,7 @@ static void mpc52xx_sdma_ack(unsigned int virq) } static struct irq_chip mpc52xx_sdma_irqchip = { - .name = "MPC52xx SDMA", + .typename = "MPC52xx SDMA", .mask = mpc52xx_sdma_mask, .unmask = mpc52xx_sdma_unmask, .ack = mpc52xx_sdma_ack, @@ -355,7 +355,7 @@ static int mpc52xx_is_extirq(int l1, int l2) * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property */ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/trunk/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 9d962d7c72c1..7ee979f323d1 100644 --- a/trunk/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/trunk/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c @@ -69,6 +69,7 @@ static void pq2ads_pci_unmask_irq(unsigned int virq) } static struct irq_chip pq2ads_pci_ic = { + .typename = "PQ2 ADS PCI", .name = "PQ2 ADS PCI", .end = pq2ads_pci_unmask_irq, .mask = pq2ads_pci_mask_irq, @@ -106,7 +107,7 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) static int pci_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_data(virq, h->host_data); set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); return 0; diff --git a/trunk/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/trunk/arch/powerpc/platforms/83xx/mpc832x_rdb.c index 17f99745f0e4..567ded7c3b9b 100644 --- a/trunk/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/trunk/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -74,7 +74,7 @@ static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk, prop = of_get_property(np, "mode", NULL); if (prop && !strcmp(prop, "cpu-qe")) - pdata.flags = SPI_QE_CPU_MODE; + pdata.qe_mode = 1; for (j = 0; j < num_board_infos; j++) { if (board_infos[j].bus_num == pdata.bus_num) diff --git a/trunk/arch/powerpc/platforms/83xx/suspend.c b/trunk/arch/powerpc/platforms/83xx/suspend.c index d306f07b9aa1..08e65fc8b98c 100644 --- a/trunk/arch/powerpc/platforms/83xx/suspend.c +++ b/trunk/arch/powerpc/platforms/83xx/suspend.c @@ -96,7 +96,6 @@ int fsl_deep_sleep(void) { return deep_sleeping; } -EXPORT_SYMBOL(fsl_deep_sleep); static int mpc83xx_change_state(void) { diff --git a/trunk/arch/powerpc/platforms/85xx/Kconfig b/trunk/arch/powerpc/platforms/85xx/Kconfig index d95121894eb7..d3a975e8fd3e 100644 --- a/trunk/arch/powerpc/platforms/85xx/Kconfig +++ b/trunk/arch/powerpc/platforms/85xx/Kconfig @@ -1,7 +1,6 @@ -menuconfig FSL_SOC_BOOKE - bool "Freescale Book-E Machine Type" - depends on PPC_85xx || PPC_BOOK3E - select FSL_SOC +menuconfig MPC85xx + bool "Machine Type" + depends on PPC_85xx select PPC_UDBG_16550 select MPIC select PPC_PCI_CHOICE @@ -9,7 +8,7 @@ menuconfig FSL_SOC_BOOKE select SERIAL_8250_SHARE_IRQ if SERIAL_8250 default y -if FSL_SOC_BOOKE +if MPC85xx config MPC8540_ADS bool "Freescale MPC8540 ADS" @@ -145,19 +144,7 @@ config SBC8560 help This option enables support for the Wind River SBC8560 board -config P4080_DS - bool "Freescale P4080 DS" - select DEFAULT_UIMAGE - select PPC_FSL_BOOK3E - select PPC_E500MC - select PHYS_64BIT - select SWIOTLB - select MPC8xxx_GPIO - select HAS_RAPIDIO - help - This option enables support for the P4080 DS board - -endif # FSL_SOC_BOOKE +endif # MPC85xx config TQM85xx bool diff --git a/trunk/arch/powerpc/platforms/85xx/Makefile b/trunk/arch/powerpc/platforms/85xx/Makefile index 387c128f2c8c..9098aea0cf32 100644 --- a/trunk/arch/powerpc/platforms/85xx/Makefile +++ b/trunk/arch/powerpc/platforms/85xx/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o -obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o obj-$(CONFIG_STX_GP3) += stx_gp3.o obj-$(CONFIG_TQM85xx) += tqm85xx.o obj-$(CONFIG_SBC8560) += sbc8560.o diff --git a/trunk/arch/powerpc/platforms/85xx/corenet_ds.c b/trunk/arch/powerpc/platforms/85xx/corenet_ds.c deleted file mode 100644 index 534c2ecc89d9..000000000000 --- a/trunk/arch/powerpc/platforms/85xx/corenet_ds.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Corenet based SoC DS Setup - * - * Maintained by Kumar Gala (see MAINTAINERS for contact information) - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -void __init corenet_ds_pic_init(void) -{ - struct mpic *mpic; - struct resource r; - struct device_node *np = NULL; - unsigned int flags = MPIC_PRIMARY | MPIC_BIG_ENDIAN | - MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU; - - np = of_find_node_by_type(np, "open-pic"); - - if (np == NULL) { - printk(KERN_ERR "Could not find open-pic node\n"); - return; - } - - if (of_address_to_resource(np, 0, &r)) { - printk(KERN_ERR "Failed to map mpic register space\n"); - of_node_put(np); - return; - } - - if (ppc_md.get_irq == mpic_get_coreint_irq) - flags |= MPIC_ENABLE_COREINT; - - mpic = mpic_alloc(np, r.start, flags, 0, 256, " OpenPIC "); - BUG_ON(mpic == NULL); - - mpic_init(mpic); -} - -#ifdef CONFIG_PCI -static int primary_phb_addr; -#endif - -/* - * Setup the architecture - */ -#ifdef CONFIG_SMP -void __init mpc85xx_smp_init(void); -#endif - -void __init corenet_ds_setup_arch(void) -{ -#ifdef CONFIG_PCI - struct device_node *np; - struct pci_controller *hose; -#endif - dma_addr_t max = 0xffffffff; - -#ifdef CONFIG_SMP - mpc85xx_smp_init(); -#endif - -#ifdef CONFIG_PCI - for_each_compatible_node(np, "pci", "fsl,p4080-pcie") { - struct resource rsrc; - of_address_to_resource(np, 0, &rsrc); - if ((rsrc.start & 0xfffff) == primary_phb_addr) - fsl_add_bridge(np, 1); - else - fsl_add_bridge(np, 0); - - hose = pci_find_hose_for_OF_device(np); - max = min(max, hose->dma_window_base_cur + - hose->dma_window_size); - } -#endif - -#ifdef CONFIG_SWIOTLB - if (lmb_end_of_DRAM() > max) { - ppc_swiotlb_enable = 1; - set_pci_dma_ops(&swiotlb_dma_ops); - ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; - } -#endif - pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); -} - -static const struct of_device_id of_device_ids[] __devinitconst = { - { - .compatible = "simple-bus" - }, - { - .compatible = "fsl,rapidio-delta", - }, - {} -}; - -int __init corenet_ds_publish_devices(void) -{ - return of_platform_bus_probe(NULL, of_device_ids, NULL); -} diff --git a/trunk/arch/powerpc/platforms/85xx/corenet_ds.h b/trunk/arch/powerpc/platforms/85xx/corenet_ds.h deleted file mode 100644 index ddd700b23031..000000000000 --- a/trunk/arch/powerpc/platforms/85xx/corenet_ds.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Corenet based SoC DS Setup - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef CORENET_DS_H -#define CORENET_DS_H - -extern void __init corenet_ds_pic_init(void); -extern void __init corenet_ds_setup_arch(void); -extern int __init corenet_ds_publish_devices(void); - -#endif diff --git a/trunk/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/trunk/arch/powerpc/platforms/85xx/mpc85xx_mds.c index c5028a2e5a58..3909d57b86e3 100644 --- a/trunk/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/trunk/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -301,7 +301,6 @@ static struct of_device_id mpc85xx_ids[] = { { .compatible = "fsl,qe", }, { .compatible = "gianfar", }, { .compatible = "fsl,rapidio-delta", }, - { .compatible = "fsl,mpc8548-guts", }, {}, }; diff --git a/trunk/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/trunk/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index 088f30b0c088..c8468de4acf6 100644 --- a/trunk/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/trunk/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -44,7 +44,6 @@ void __init mpc85xx_rdb_pic_init(void) struct mpic *mpic; struct resource r; struct device_node *np; - unsigned long root = of_get_flat_dt_root(); np = of_find_node_by_type(NULL, "open-pic"); if (np == NULL) { @@ -58,18 +57,11 @@ void __init mpc85xx_rdb_pic_init(void) return; } - if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) { - mpic = mpic_alloc(np, r.start, - MPIC_PRIMARY | - MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, - 0, 256, " OpenPIC "); - } else { - mpic = mpic_alloc(np, r.start, + mpic = mpic_alloc(np, r.start, MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); - } BUG_ON(mpic == NULL); of_node_put(np); @@ -121,7 +113,6 @@ static int __init mpc85xxrdb_publish_devices(void) return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL); } machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices); -machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices); /* * Called very early, device-tree isn't unflattened @@ -135,15 +126,6 @@ static int __init p2020_rdb_probe(void) return 0; } -static int __init p1020_rdb_probe(void) -{ - unsigned long root = of_get_flat_dt_root(); - - if (of_flat_dt_is_compatible(root, "fsl,P1020RDB")) - return 1; - return 0; -} - define_machine(p2020_rdb) { .name = "P2020 RDB", .probe = p2020_rdb_probe, @@ -157,17 +139,3 @@ define_machine(p2020_rdb) { .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, }; - -define_machine(p1020_rdb) { - .name = "P1020 RDB", - .probe = p1020_rdb_probe, - .setup_arch = mpc85xx_rdb_setup_arch, - .init_IRQ = mpc85xx_rdb_pic_init, -#ifdef CONFIG_PCI - .pcibios_fixup_bus = fsl_pcibios_fixup_bus, -#endif - .get_irq = mpic_get_irq, - .restart = fsl_rstcr_restart, - .calibrate_decr = generic_calibrate_decr, - .progress = udbg_progress, -}; diff --git a/trunk/arch/powerpc/platforms/85xx/p4080_ds.c b/trunk/arch/powerpc/platforms/85xx/p4080_ds.c deleted file mode 100644 index 84170460497b..000000000000 --- a/trunk/arch/powerpc/platforms/85xx/p4080_ds.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * P4080 DS Setup - * - * Maintained by Kumar Gala (see MAINTAINERS for contact information) - * - * Copyright 2009 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "corenet_ds.h" - -#ifdef CONFIG_PCI -static int primary_phb_addr; -#endif - -/* - * Called very early, device-tree isn't unflattened - */ -static int __init p4080_ds_probe(void) -{ - unsigned long root = of_get_flat_dt_root(); - - if (of_flat_dt_is_compatible(root, "fsl,P4080DS")) { -#ifdef CONFIG_PCI - /* treat PCIe1 as primary, - * shouldn't matter as we have no ISA on the board - */ - primary_phb_addr = 0x0000; -#endif - return 1; - } else { - return 0; - } -} - -define_machine(p4080_ds) { - .name = "P4080 DS", - .probe = p4080_ds_probe, - .setup_arch = corenet_ds_setup_arch, - .init_IRQ = corenet_ds_pic_init, -#ifdef CONFIG_PCI - .pcibios_fixup_bus = fsl_pcibios_fixup_bus, -#endif - .get_irq = mpic_get_coreint_irq, - .restart = fsl_rstcr_restart, - .calibrate_decr = generic_calibrate_decr, - .progress = udbg_progress, -}; - -machine_device_initcall(p4080_ds, corenet_ds_publish_devices); -machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier); diff --git a/trunk/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/trunk/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index e5da5f62b24a..60edf63d0157 100644 --- a/trunk/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/trunk/arch/powerpc/platforms/85xx/socrates_fpga_pic.c @@ -232,7 +232,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq, } static struct irq_chip socrates_fpga_pic_chip = { - .name = " FPGA-PIC ", + .typename = " FPGA-PIC ", .ack = socrates_fpga_pic_ack, .mask = socrates_fpga_pic_mask, .mask_ack = socrates_fpga_pic_mask_ack, @@ -245,7 +245,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { /* All interrupts are LEVEL sensitive */ - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip, handle_fasteoi_irq); @@ -253,7 +253,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, } static int socrates_fpga_pic_host_xlate(struct irq_host *h, - struct device_node *ct, const u32 *intspec, unsigned int intsize, + struct device_node *ct, u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { struct socrates_fpga_irq_info *fpga_irq = &fpga_irqs[intspec[0]]; diff --git a/trunk/arch/powerpc/platforms/86xx/Kconfig b/trunk/arch/powerpc/platforms/86xx/Kconfig index 2bbfd530d6d8..9c7b64a3402b 100644 --- a/trunk/arch/powerpc/platforms/86xx/Kconfig +++ b/trunk/arch/powerpc/platforms/86xx/Kconfig @@ -35,7 +35,6 @@ config MPC8610_HPCD config GEF_PPC9A bool "GE Fanuc PPC9A" select DEFAULT_UIMAGE - select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help @@ -44,7 +43,6 @@ config GEF_PPC9A config GEF_SBC310 bool "GE Fanuc SBC310" select DEFAULT_UIMAGE - select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help @@ -53,7 +51,6 @@ config GEF_SBC310 config GEF_SBC610 bool "GE Fanuc SBC610" select DEFAULT_UIMAGE - select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select HAS_RAPIDIO diff --git a/trunk/arch/powerpc/platforms/86xx/gef_pic.c b/trunk/arch/powerpc/platforms/86xx/gef_pic.c index 0110a8736d33..50d0a2b63809 100644 --- a/trunk/arch/powerpc/platforms/86xx/gef_pic.c +++ b/trunk/arch/powerpc/platforms/86xx/gef_pic.c @@ -149,7 +149,7 @@ static void gef_pic_unmask(unsigned int virq) } static struct irq_chip gef_pic_chip = { - .name = "gefp", + .typename = "gefp", .mask = gef_pic_mask, .mask_ack = gef_pic_mask_ack, .unmask = gef_pic_unmask, @@ -163,14 +163,14 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hwirq) { /* All interrupts are LEVEL sensitive */ - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); return 0; } static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/platforms/86xx/gef_ppc9a.c b/trunk/arch/powerpc/platforms/86xx/gef_ppc9a.c index a792e5d85813..287f7bd17dd9 100644 --- a/trunk/arch/powerpc/platforms/86xx/gef_ppc9a.c +++ b/trunk/arch/powerpc/platforms/86xx/gef_ppc9a.c @@ -33,7 +33,6 @@ #include #include -#include #include #include @@ -96,10 +95,6 @@ static void __init gef_ppc9a_setup_arch(void) printk(KERN_WARNING "Unable to map board registers\n"); of_node_put(regs); } - -#if defined(CONFIG_MMIO_NVRAM) - mmio_nvram_init(); -#endif } /* Return the PCB revision */ diff --git a/trunk/arch/powerpc/platforms/86xx/gef_sbc310.c b/trunk/arch/powerpc/platforms/86xx/gef_sbc310.c index 6a1a613836c2..90754e752bd8 100644 --- a/trunk/arch/powerpc/platforms/86xx/gef_sbc310.c +++ b/trunk/arch/powerpc/platforms/86xx/gef_sbc310.c @@ -33,7 +33,6 @@ #include #include -#include #include #include @@ -96,10 +95,6 @@ static void __init gef_sbc310_setup_arch(void) printk(KERN_WARNING "Unable to map board registers\n"); of_node_put(regs); } - -#if defined(CONFIG_MMIO_NVRAM) - mmio_nvram_init(); -#endif } /* Return the PCB revision */ diff --git a/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c b/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c index e10688a0fc4e..72b31a6010a0 100644 --- a/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c +++ b/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c @@ -33,7 +33,6 @@ #include #include -#include #include #include @@ -96,10 +95,6 @@ static void __init gef_sbc610_setup_arch(void) printk(KERN_WARNING "Unable to map board registers\n"); of_node_put(regs); } - -#if defined(CONFIG_MMIO_NVRAM) - mmio_nvram_init(); -#endif } /* Return the PCB revision */ diff --git a/trunk/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/trunk/arch/powerpc/platforms/86xx/mpc8610_hpcd.c index 5abe137f6309..627908a4cd77 100644 --- a/trunk/arch/powerpc/platforms/86xx/mpc8610_hpcd.c +++ b/trunk/arch/powerpc/platforms/86xx/mpc8610_hpcd.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -42,46 +41,10 @@ #include "mpc86xx.h" -static struct device_node *pixis_node; static unsigned char *pixis_bdcfg0, *pixis_arch; -#ifdef CONFIG_SUSPEND -static irqreturn_t mpc8610_sw9_irq(int irq, void *data) -{ - pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__); - return IRQ_HANDLED; -} - -static void __init mpc8610_suspend_init(void) -{ - int irq; - int ret; - - if (!pixis_node) - return; - - irq = irq_of_parse_and_map(pixis_node, 0); - if (!irq) { - pr_err("%s: can't map pixis event IRQ.\n", __func__); - return; - } - - ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL); - if (ret) { - pr_err("%s: can't request pixis event IRQ: %d\n", - __func__, ret); - irq_dispose_mapping(irq); - } - - enable_irq_wake(irq); -} -#else -static inline void mpc8610_suspend_init(void) { } -#endif /* CONFIG_SUSPEND */ - static struct of_device_id __initdata mpc8610_ids[] = { { .compatible = "fsl,mpc8610-immr", }, - { .compatible = "fsl,mpc8610-guts", }, { .compatible = "simple-bus", }, { .compatible = "gianfar", }, {} @@ -92,9 +55,6 @@ static int __init mpc8610_declare_of_platform_devices(void) /* Firstly, register PIXIS GPIOs. */ simple_gpiochip_init("fsl,fpga-pixis-gpio-bank"); - /* Enable wakeup on PIXIS' event IRQ. */ - mpc8610_suspend_init(); - /* Without this call, the SSI device driver won't get probed. */ of_platform_bus_probe(NULL, mpc8610_ids, NULL); @@ -290,10 +250,10 @@ static void __init mpc86xx_hpcd_setup_arch(void) diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port; #endif - pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis"); - if (pixis_node) { - of_address_to_resource(pixis_node, 0, &r); - of_node_put(pixis_node); + np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis"); + if (np) { + of_address_to_resource(np, 0, &r); + of_node_put(np); pixis = ioremap(r.start, 32); if (!pixis) { printk(KERN_ERR "Err: can't map FPGA cfg register!\n"); diff --git a/trunk/arch/powerpc/platforms/8xx/m8xx_setup.c b/trunk/arch/powerpc/platforms/8xx/m8xx_setup.c index 242954c4293f..385acfc48397 100644 --- a/trunk/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/trunk/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -222,7 +222,7 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc) int cascade_irq; if ((cascade_irq = cpm_get_irq()) >= 0) { - struct irq_desc *cdesc = irq_to_desc(cascade_irq); + struct irq_desc *cdesc = irq_desc + cascade_irq; generic_handle_irq(cascade_irq); cdesc->chip->eoi(cascade_irq); diff --git a/trunk/arch/powerpc/platforms/Kconfig b/trunk/arch/powerpc/platforms/Kconfig index d1663db7810f..04a8061045c4 100644 --- a/trunk/arch/powerpc/platforms/Kconfig +++ b/trunk/arch/powerpc/platforms/Kconfig @@ -86,11 +86,6 @@ config RTAS_ERROR_LOGGING depends on PPC_RTAS default n -config PPC_RTAS_DAEMON - bool - depends on PPC_RTAS - default n - config RTAS_PROC bool "Proc interface to RTAS" depends on PPC_RTAS @@ -260,7 +255,7 @@ config QE_GPIO config CPM2 bool "Enable support for the CPM2 (Communications Processor Module)" - depends on (FSL_SOC_BOOKE && PPC32) || 8260 + depends on MPC85xx || 8260 select CPM select PPC_LIB_RHEAP select PPC_PCI_CHOICE @@ -305,7 +300,7 @@ source "arch/powerpc/sysdev/bestcomm/Kconfig" config MPC8xxx_GPIO bool "MPC8xxx GPIO support" - depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || FSL_SOC_BOOKE || PPC_86xx + depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || PPC_85xx || PPC_86xx select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help diff --git a/trunk/arch/powerpc/platforms/Kconfig.cputype b/trunk/arch/powerpc/platforms/Kconfig.cputype index 2eab27a94cc9..e382cae678b8 100644 --- a/trunk/arch/powerpc/platforms/Kconfig.cputype +++ b/trunk/arch/powerpc/platforms/Kconfig.cputype @@ -28,6 +28,8 @@ config PPC_BOOK3S_32 config PPC_85xx bool "Freescale 85xx" select E500 + select FSL_SOC + select MPC85xx config PPC_8xx bool "Freescale 8xx" @@ -136,14 +138,6 @@ config PPC_FPU bool default y if PPC64 -config FSL_EMB_PERFMON - bool "Freescale Embedded Perfmon" - depends on E500 || PPC_83xx - help - This is the Performance Monitor support found on the e500 core - and some e300 cores (c3 and c4). Select this only if your - core supports the Embedded Performance Monitor APU - config 4xx bool depends on 40x || 44x @@ -159,6 +153,13 @@ config FSL_BOOKE depends on E200 || E500 default y +config FSL_EMB_PERFMON + bool "Freescale Embedded Perfmon" + depends on E500 || PPC_83xx + help + This is the Performance Monitor support found on the e500 core + and some e300 cores (c3 and c4). Select this only if your + core supports the Embedded Performance Monitor APU config PTE_64BIT bool diff --git a/trunk/arch/powerpc/platforms/Makefile b/trunk/arch/powerpc/platforms/Makefile index fdb9f0b0d7a8..a6812ee00100 100644 --- a/trunk/arch/powerpc/platforms/Makefile +++ b/trunk/arch/powerpc/platforms/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_PPC_MPC52xx) += 52xx/ obj-$(CONFIG_PPC_8xx) += 8xx/ obj-$(CONFIG_PPC_82xx) += 82xx/ obj-$(CONFIG_PPC_83xx) += 83xx/ -obj-$(CONFIG_FSL_SOC_BOOKE) += 85xx/ +obj-$(CONFIG_PPC_85xx) += 85xx/ obj-$(CONFIG_PPC_86xx) += 86xx/ obj-$(CONFIG_PPC_PSERIES) += pseries/ obj-$(CONFIG_PPC_ISERIES) += iseries/ diff --git a/trunk/arch/powerpc/platforms/cell/axon_msi.c b/trunk/arch/powerpc/platforms/cell/axon_msi.c index 96fe896f6df3..a86c34b3bb84 100644 --- a/trunk/arch/powerpc/platforms/cell/axon_msi.c +++ b/trunk/arch/powerpc/platforms/cell/axon_msi.c @@ -312,7 +312,7 @@ static struct irq_chip msic_irq_chip = { .mask = mask_msi_irq, .unmask = unmask_msi_irq, .shutdown = unmask_msi_irq, - .name = "AXON-MSI", + .typename = "AXON-MSI", }; static int msic_host_map(struct irq_host *h, unsigned int virq, diff --git a/trunk/arch/powerpc/platforms/cell/beat_interrupt.c b/trunk/arch/powerpc/platforms/cell/beat_interrupt.c index 36052a9ebcda..72254848a228 100644 --- a/trunk/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/trunk/arch/powerpc/platforms/cell/beat_interrupt.c @@ -110,7 +110,7 @@ static void beatic_end_irq(unsigned int irq_plug) } static struct irq_chip beatic_pic = { - .name = " CELL-BEAT ", + .typename = " CELL-BEAT ", .unmask = beatic_unmask_irq, .mask = beatic_mask_irq, .eoi = beatic_end_irq, @@ -136,7 +136,7 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq) static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); int64_t err; err = beat_construct_and_connect_irq_plug(virq, hw); @@ -166,11 +166,11 @@ static void beatic_pic_host_remap(struct irq_host *h, unsigned int virq, * Note: We have only 1 entry to translate. */ static int beatic_pic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { - const u64 *intspec2 = (const u64 *)intspec; + u64 *intspec2 = (u64 *)intspec; *out_hwirq = *intspec2; *out_flags |= IRQ_TYPE_LEVEL_LOW; diff --git a/trunk/arch/powerpc/platforms/cell/interrupt.c b/trunk/arch/powerpc/platforms/cell/interrupt.c index f9dbf76a763f..882e47080e74 100644 --- a/trunk/arch/powerpc/platforms/cell/interrupt.c +++ b/trunk/arch/powerpc/platforms/cell/interrupt.c @@ -88,7 +88,7 @@ static void iic_eoi(unsigned int irq) } static struct irq_chip iic_chip = { - .name = " CELL-IIC ", + .typename = " CELL-IIC ", .mask = iic_mask, .unmask = iic_unmask, .eoi = iic_eoi, @@ -133,7 +133,7 @@ static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) static struct irq_chip iic_ioexc_chip = { - .name = " CELL-IOEX", + .typename = " CELL-IOEX", .mask = iic_mask, .unmask = iic_unmask, .eoi = iic_ioexc_eoi, @@ -297,7 +297,7 @@ static int iic_host_map(struct irq_host *h, unsigned int virq, } static int iic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/platforms/cell/spider-pic.c b/trunk/arch/powerpc/platforms/cell/spider-pic.c index 01244f254a11..4e5655624ae8 100644 --- a/trunk/arch/powerpc/platforms/cell/spider-pic.c +++ b/trunk/arch/powerpc/platforms/cell/spider-pic.c @@ -102,7 +102,7 @@ static void spider_ack_irq(unsigned int virq) /* Reset edge detection logic if necessary */ - if (irq_to_desc(virq)->status & IRQ_LEVEL) + if (get_irq_desc(virq)->status & IRQ_LEVEL) return; /* Only interrupts 47 to 50 can be set to edge */ @@ -119,7 +119,7 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type) struct spider_pic *pic = spider_virq_to_pic(virq); unsigned int hw = irq_map[virq].hwirq; void __iomem *cfg = spider_get_irq_config(pic, hw); - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); u32 old_mask; u32 ic; @@ -168,7 +168,7 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type) } static struct irq_chip spider_pic = { - .name = " SPIDER ", + .typename = " SPIDER ", .unmask = spider_unmask_irq, .mask = spider_mask_irq, .ack = spider_ack_irq, @@ -187,7 +187,7 @@ static int spider_host_map(struct irq_host *h, unsigned int virq, } static int spider_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/platforms/cell/spufs/file.c b/trunk/arch/powerpc/platforms/cell/spufs/file.c index 64a4c2d85f7c..884e8bcec499 100644 --- a/trunk/arch/powerpc/platforms/cell/spufs/file.c +++ b/trunk/arch/powerpc/platforms/cell/spufs/file.c @@ -2494,7 +2494,7 @@ static ssize_t spufs_switch_log_read(struct file *file, char __user *buf, struct spu_context *ctx = SPUFS_I(inode)->i_ctx; int error = 0, cnt = 0; - if (!buf) + if (!buf || len < 0) return -EINVAL; error = spu_acquire(ctx); diff --git a/trunk/arch/powerpc/platforms/chrp/Kconfig b/trunk/arch/powerpc/platforms/chrp/Kconfig index bc0b0efdc5fe..37d438bd5b7a 100644 --- a/trunk/arch/powerpc/platforms/chrp/Kconfig +++ b/trunk/arch/powerpc/platforms/chrp/Kconfig @@ -5,8 +5,6 @@ config PPC_CHRP select PPC_I8259 select PPC_INDIRECT_PCI select PPC_RTAS - select PPC_RTAS_DAEMON - select RTAS_ERROR_LOGGING select PPC_MPC106 select PPC_UDBG_16550 select PPC_NATIVE diff --git a/trunk/arch/powerpc/platforms/chrp/setup.c b/trunk/arch/powerpc/platforms/chrp/setup.c index 52f3df3b4ca0..cd4ad9aea760 100644 --- a/trunk/arch/powerpc/platforms/chrp/setup.c +++ b/trunk/arch/powerpc/platforms/chrp/setup.c @@ -364,6 +364,19 @@ void __init chrp_setup_arch(void) if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); } +void +chrp_event_scan(unsigned long unused) +{ + unsigned char log[1024]; + int ret = 0; + + /* XXX: we should loop until the hardware says no more error logs -- Cort */ + rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, + __pa(log), 1024); + mod_timer(&__get_cpu_var(heartbeat_timer), + jiffies + event_scan_interval); +} + static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) { unsigned int cascade_irq = i8259_irq(); @@ -555,6 +568,9 @@ void __init chrp_init_IRQ(void) void __init chrp_init2(void) { + struct device_node *device; + const unsigned int *p = NULL; + #ifdef CONFIG_NVRAM chrp_nvram_init(); #endif @@ -566,6 +582,40 @@ chrp_init2(void) request_region(0x80,0x10,"dma page reg"); request_region(0xc0,0x20,"dma2"); + /* Get the event scan rate for the rtas so we know how + * often it expects a heartbeat. -- Cort + */ + device = of_find_node_by_name(NULL, "rtas"); + if (device) + p = of_get_property(device, "rtas-event-scan-rate", NULL); + if (p && *p) { + /* + * Arrange to call chrp_event_scan at least *p times + * per minute. We use 59 rather than 60 here so that + * the rate will be slightly higher than the minimum. + * This all assumes we don't do hotplug CPU on any + * machine that needs the event scans done. + */ + unsigned long interval, offset; + int cpu, ncpus; + struct timer_list *timer; + + interval = HZ * 59 / *p; + offset = HZ; + ncpus = num_online_cpus(); + event_scan_interval = ncpus * interval; + for (cpu = 0; cpu < ncpus; ++cpu) { + timer = &per_cpu(heartbeat_timer, cpu); + setup_timer(timer, chrp_event_scan, 0); + timer->expires = jiffies + offset; + add_timer_on(timer, cpu); + offset += interval; + } + printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", + *p, interval); + } + of_node_put(device); + if (ppc_md.progress) ppc_md.progress(" Have fun! ", 0x7777); } diff --git a/trunk/arch/powerpc/platforms/iseries/htab.c b/trunk/arch/powerpc/platforms/iseries/htab.c index 3ae66ab9d5e7..f99c6c4b6985 100644 --- a/trunk/arch/powerpc/platforms/iseries/htab.c +++ b/trunk/arch/powerpc/platforms/iseries/htab.c @@ -19,7 +19,8 @@ #include "call_hpt.h" -static spinlock_t iSeries_hlocks[64] __cacheline_aligned_in_smp; +static spinlock_t iSeries_hlocks[64] __cacheline_aligned_in_smp = + { [0 ... 63] = SPIN_LOCK_UNLOCKED}; /* * Very primitive algorithm for picking up a lock @@ -244,11 +245,6 @@ static void iSeries_hpte_invalidate(unsigned long slot, unsigned long va, void __init hpte_init_iSeries(void) { - int i; - - for (i = 0; i < ARRAY_SIZE(iSeries_hlocks); i++) - spin_lock_init(&iSeries_hlocks[i]); - ppc_md.hpte_invalidate = iSeries_hpte_invalidate; ppc_md.hpte_updatepp = iSeries_hpte_updatepp; ppc_md.hpte_updateboltedpp = iSeries_hpte_updateboltedpp; diff --git a/trunk/arch/powerpc/platforms/iseries/irq.c b/trunk/arch/powerpc/platforms/iseries/irq.c index 07762259c60a..94f444758836 100644 --- a/trunk/arch/powerpc/platforms/iseries/irq.c +++ b/trunk/arch/powerpc/platforms/iseries/irq.c @@ -214,7 +214,7 @@ void __init iSeries_activate_IRQs() unsigned long flags; for_each_irq (irq) { - struct irq_desc *desc = irq_to_desc(irq); + struct irq_desc *desc = get_irq_desc(irq); if (desc && desc->chip && desc->chip->startup) { spin_lock_irqsave(&desc->lock, flags); @@ -273,7 +273,7 @@ static void iseries_end_IRQ(unsigned int irq) } static struct irq_chip iseries_pic = { - .name = "iSeries irq controller", + .typename = "iSeries irq controller", .startup = iseries_startup_IRQ, .shutdown = iseries_shutdown_IRQ, .unmask = iseries_enable_IRQ, diff --git a/trunk/arch/powerpc/platforms/powermac/pic.c b/trunk/arch/powerpc/platforms/powermac/pic.c index 09e827296276..d212006a5b3c 100644 --- a/trunk/arch/powerpc/platforms/powermac/pic.c +++ b/trunk/arch/powerpc/platforms/powermac/pic.c @@ -152,12 +152,12 @@ static unsigned int pmac_startup_irq(unsigned int virq) unsigned long bit = 1UL << (src & 0x1f); int i = src >> 5; - spin_lock_irqsave(&pmac_pic_lock, flags); - if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0) + spin_lock_irqsave(&pmac_pic_lock, flags); + if ((irq_desc[virq].status & IRQ_LEVEL) == 0) out_le32(&pmac_irq_hw[i]->ack, bit); __set_bit(src, ppc_cached_irq_mask); __pmac_set_irq_mask(src, 0); - spin_unlock_irqrestore(&pmac_pic_lock, flags); + spin_unlock_irqrestore(&pmac_pic_lock, flags); return 0; } @@ -195,7 +195,7 @@ static int pmac_retrigger(unsigned int virq) } static struct irq_chip pmac_pic = { - .name = " PMAC-PIC ", + .typename = " PMAC-PIC ", .startup = pmac_startup_irq, .mask = pmac_mask_irq, .ack = pmac_ack_irq, @@ -285,7 +285,7 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); int level; if (hw >= max_irqs) @@ -303,7 +303,7 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, } static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) diff --git a/trunk/arch/powerpc/platforms/ps3/interrupt.c b/trunk/arch/powerpc/platforms/ps3/interrupt.c index 59d9712d7364..8ec5ccf76b19 100644 --- a/trunk/arch/powerpc/platforms/ps3/interrupt.c +++ b/trunk/arch/powerpc/platforms/ps3/interrupt.c @@ -152,7 +152,7 @@ static void ps3_chip_eoi(unsigned int virq) */ static struct irq_chip ps3_irq_chip = { - .name = "ps3", + .typename = "ps3", .mask = ps3_chip_mask, .unmask = ps3_chip_unmask, .eoi = ps3_chip_eoi, diff --git a/trunk/arch/powerpc/platforms/ps3/mm.c b/trunk/arch/powerpc/platforms/ps3/mm.c index e81b028a2a48..189a25b80735 100644 --- a/trunk/arch/powerpc/platforms/ps3/mm.c +++ b/trunk/arch/powerpc/platforms/ps3/mm.c @@ -34,7 +34,7 @@ #if defined(DEBUG) #define DBG udbg_printf #else -#define DBG pr_devel +#define DBG pr_debug #endif enum { diff --git a/trunk/arch/powerpc/platforms/pseries/Kconfig b/trunk/arch/powerpc/platforms/pseries/Kconfig index 27554c807fd5..f0e6f28427bd 100644 --- a/trunk/arch/powerpc/platforms/pseries/Kconfig +++ b/trunk/arch/powerpc/platforms/pseries/Kconfig @@ -4,7 +4,6 @@ config PPC_PSERIES select MPIC select PPC_I8259 select PPC_RTAS - select PPC_RTAS_DAEMON select RTAS_ERROR_LOGGING select PPC_UDBG_16550 select PPC_NATIVE @@ -60,7 +59,7 @@ config PPC_SMLPAR config CMM tristate "Collaborative memory management" - depends on PPC_SMLPAR + depends on PPC_SMLPAR && !CRASH_DUMP default y help Select this option, if you want to enable the kernel interface diff --git a/trunk/arch/powerpc/platforms/pseries/Makefile b/trunk/arch/powerpc/platforms/pseries/Makefile index 0ff5174ae4f5..790c0b872d4f 100644 --- a/trunk/arch/powerpc/platforms/pseries/Makefile +++ b/trunk/arch/powerpc/platforms/pseries/Makefile @@ -7,8 +7,8 @@ EXTRA_CFLAGS += -DDEBUG endif obj-y := lpar.o hvCall.o nvram.o reconfig.o \ - setup.o iommu.o ras.o \ - firmware.o power.o dlpar.o + setup.o iommu.o ras.o rtasd.o \ + firmware.o power.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_XICS) += xics.o obj-$(CONFIG_SCANLOG) += scanlog.o diff --git a/trunk/arch/powerpc/platforms/pseries/cmm.c b/trunk/arch/powerpc/platforms/pseries/cmm.c index bcdcf0ccc8d7..6567439fe78d 100644 --- a/trunk/arch/powerpc/platforms/pseries/cmm.c +++ b/trunk/arch/powerpc/platforms/pseries/cmm.c @@ -229,9 +229,8 @@ static void cmm_get_mpp(void) { int rc; struct hvcall_mpp_data mpp_data; - signed long active_pages_target, page_loan_request, target; - signed long total_pages = totalram_pages + loaned_pages; - signed long min_mem_pages = (min_mem_mb * 1024 * 1024) / PAGE_SIZE; + unsigned long active_pages_target; + signed long page_loan_request; rc = h_get_mpp(&mpp_data); @@ -239,25 +238,17 @@ static void cmm_get_mpp(void) return; page_loan_request = div_s64((s64)mpp_data.loan_request, PAGE_SIZE); - target = page_loan_request + (signed long)loaned_pages; - - if (target < 0 || total_pages < min_mem_pages) - target = 0; - - if (target > oom_freed_pages) - target -= oom_freed_pages; + loaned_pages_target = page_loan_request + loaned_pages; + if (loaned_pages_target > oom_freed_pages) + loaned_pages_target -= oom_freed_pages; else - target = 0; - - active_pages_target = total_pages - target; - - if (min_mem_pages > active_pages_target) - target = total_pages - min_mem_pages; + loaned_pages_target = 0; - if (target < 0) - target = 0; + active_pages_target = totalram_pages + loaned_pages - loaned_pages_target; - loaned_pages_target = target; + if ((min_mem_mb * 1024 * 1024) > (active_pages_target * PAGE_SIZE)) + loaned_pages_target = totalram_pages + loaned_pages - + ((min_mem_mb * 1024 * 1024) / PAGE_SIZE); cmm_dbg("delta = %ld, loaned = %lu, target = %lu, oom = %lu, totalram = %lu\n", page_loan_request, loaned_pages, loaned_pages_target, diff --git a/trunk/arch/powerpc/platforms/pseries/dlpar.c b/trunk/arch/powerpc/platforms/pseries/dlpar.c deleted file mode 100644 index 12df9e8812a9..000000000000 --- a/trunk/arch/powerpc/platforms/pseries/dlpar.c +++ /dev/null @@ -1,558 +0,0 @@ -/* - * Support for dynamic reconfiguration for PCI, Memory, and CPU - * Hotplug and Dynamic Logical Partitioning on RPA platforms. - * - * Copyright (C) 2009 Nathan Fontenot - * Copyright (C) 2009 IBM Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version - * 2 as published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include "offline_states.h" - -#include -#include -#include -#include -#include - -struct cc_workarea { - u32 drc_index; - u32 zero; - u32 name_offset; - u32 prop_length; - u32 prop_offset; -}; - -static void dlpar_free_cc_property(struct property *prop) -{ - kfree(prop->name); - kfree(prop->value); - kfree(prop); -} - -static struct property *dlpar_parse_cc_property(struct cc_workarea *ccwa) -{ - struct property *prop; - char *name; - char *value; - - prop = kzalloc(sizeof(*prop), GFP_KERNEL); - if (!prop) - return NULL; - - name = (char *)ccwa + ccwa->name_offset; - prop->name = kstrdup(name, GFP_KERNEL); - - prop->length = ccwa->prop_length; - value = (char *)ccwa + ccwa->prop_offset; - prop->value = kzalloc(prop->length, GFP_KERNEL); - if (!prop->value) { - dlpar_free_cc_property(prop); - return NULL; - } - - memcpy(prop->value, value, prop->length); - return prop; -} - -static struct device_node *dlpar_parse_cc_node(struct cc_workarea *ccwa) -{ - struct device_node *dn; - char *name; - - dn = kzalloc(sizeof(*dn), GFP_KERNEL); - if (!dn) - return NULL; - - /* The configure connector reported name does not contain a - * preceeding '/', so we allocate a buffer large enough to - * prepend this to the full_name. - */ - name = (char *)ccwa + ccwa->name_offset; - dn->full_name = kmalloc(strlen(name) + 2, GFP_KERNEL); - if (!dn->full_name) { - kfree(dn); - return NULL; - } - - sprintf(dn->full_name, "/%s", name); - return dn; -} - -static void dlpar_free_one_cc_node(struct device_node *dn) -{ - struct property *prop; - - while (dn->properties) { - prop = dn->properties; - dn->properties = prop->next; - dlpar_free_cc_property(prop); - } - - kfree(dn->full_name); - kfree(dn); -} - -static void dlpar_free_cc_nodes(struct device_node *dn) -{ - if (dn->child) - dlpar_free_cc_nodes(dn->child); - - if (dn->sibling) - dlpar_free_cc_nodes(dn->sibling); - - dlpar_free_one_cc_node(dn); -} - -#define NEXT_SIBLING 1 -#define NEXT_CHILD 2 -#define NEXT_PROPERTY 3 -#define PREV_PARENT 4 -#define MORE_MEMORY 5 -#define CALL_AGAIN -2 -#define ERR_CFG_USE -9003 - -struct device_node *dlpar_configure_connector(u32 drc_index) -{ - struct device_node *dn; - struct device_node *first_dn = NULL; - struct device_node *last_dn = NULL; - struct property *property; - struct property *last_property = NULL; - struct cc_workarea *ccwa; - int cc_token; - int rc; - - cc_token = rtas_token("ibm,configure-connector"); - if (cc_token == RTAS_UNKNOWN_SERVICE) - return NULL; - - spin_lock(&rtas_data_buf_lock); - ccwa = (struct cc_workarea *)&rtas_data_buf[0]; - ccwa->drc_index = drc_index; - ccwa->zero = 0; - - rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL); - while (rc) { - switch (rc) { - case NEXT_SIBLING: - dn = dlpar_parse_cc_node(ccwa); - if (!dn) - goto cc_error; - - dn->parent = last_dn->parent; - last_dn->sibling = dn; - last_dn = dn; - break; - - case NEXT_CHILD: - dn = dlpar_parse_cc_node(ccwa); - if (!dn) - goto cc_error; - - if (!first_dn) - first_dn = dn; - else { - dn->parent = last_dn; - if (last_dn) - last_dn->child = dn; - } - - last_dn = dn; - break; - - case NEXT_PROPERTY: - property = dlpar_parse_cc_property(ccwa); - if (!property) - goto cc_error; - - if (!last_dn->properties) - last_dn->properties = property; - else - last_property->next = property; - - last_property = property; - break; - - case PREV_PARENT: - last_dn = last_dn->parent; - break; - - case CALL_AGAIN: - break; - - case MORE_MEMORY: - case ERR_CFG_USE: - default: - printk(KERN_ERR "Unexpected Error (%d) " - "returned from configure-connector\n", rc); - goto cc_error; - } - - rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL); - } - - spin_unlock(&rtas_data_buf_lock); - return first_dn; - -cc_error: - if (first_dn) - dlpar_free_cc_nodes(first_dn); - spin_unlock(&rtas_data_buf_lock); - return NULL; -} - -static struct device_node *derive_parent(const char *path) -{ - struct device_node *parent; - char *last_slash; - - last_slash = strrchr(path, '/'); - if (last_slash == path) { - parent = of_find_node_by_path("/"); - } else { - char *parent_path; - int parent_path_len = last_slash - path + 1; - parent_path = kmalloc(parent_path_len, GFP_KERNEL); - if (!parent_path) - return NULL; - - strlcpy(parent_path, path, parent_path_len); - parent = of_find_node_by_path(parent_path); - kfree(parent_path); - } - - return parent; -} - -int dlpar_attach_node(struct device_node *dn) -{ - struct proc_dir_entry *ent; - int rc; - - of_node_set_flag(dn, OF_DYNAMIC); - kref_init(&dn->kref); - dn->parent = derive_parent(dn->full_name); - if (!dn->parent) - return -ENOMEM; - - rc = blocking_notifier_call_chain(&pSeries_reconfig_chain, - PSERIES_RECONFIG_ADD, dn); - if (rc == NOTIFY_BAD) { - printk(KERN_ERR "Failed to add device node %s\n", - dn->full_name); - return -ENOMEM; /* For now, safe to assume kmalloc failure */ - } - - of_attach_node(dn); - -#ifdef CONFIG_PROC_DEVICETREE - ent = proc_mkdir(strrchr(dn->full_name, '/') + 1, dn->parent->pde); - if (ent) - proc_device_tree_add_node(dn, ent); -#endif - - of_node_put(dn->parent); - return 0; -} - -int dlpar_detach_node(struct device_node *dn) -{ - struct device_node *parent = dn->parent; - struct property *prop = dn->properties; - -#ifdef CONFIG_PROC_DEVICETREE - while (prop) { - remove_proc_entry(prop->name, dn->pde); - prop = prop->next; - } - - if (dn->pde) - remove_proc_entry(dn->pde->name, parent->pde); -#endif - - blocking_notifier_call_chain(&pSeries_reconfig_chain, - PSERIES_RECONFIG_REMOVE, dn); - of_detach_node(dn); - of_node_put(dn); /* Must decrement the refcount */ - - return 0; -} - -#define DR_ENTITY_SENSE 9003 -#define DR_ENTITY_PRESENT 1 -#define DR_ENTITY_UNUSABLE 2 -#define ALLOCATION_STATE 9003 -#define ALLOC_UNUSABLE 0 -#define ALLOC_USABLE 1 -#define ISOLATION_STATE 9001 -#define ISOLATE 0 -#define UNISOLATE 1 - -int dlpar_acquire_drc(u32 drc_index) -{ - int dr_status, rc; - - rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status, - DR_ENTITY_SENSE, drc_index); - if (rc || dr_status != DR_ENTITY_UNUSABLE) - return -1; - - rc = rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_USABLE); - if (rc) - return rc; - - rc = rtas_set_indicator(ISOLATION_STATE, drc_index, UNISOLATE); - if (rc) { - rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_UNUSABLE); - return rc; - } - - return 0; -} - -int dlpar_release_drc(u32 drc_index) -{ - int dr_status, rc; - - rc = rtas_call(rtas_token("get-sensor-state"), 2, 2, &dr_status, - DR_ENTITY_SENSE, drc_index); - if (rc || dr_status != DR_ENTITY_PRESENT) - return -1; - - rc = rtas_set_indicator(ISOLATION_STATE, drc_index, ISOLATE); - if (rc) - return rc; - - rc = rtas_set_indicator(ALLOCATION_STATE, drc_index, ALLOC_UNUSABLE); - if (rc) { - rtas_set_indicator(ISOLATION_STATE, drc_index, UNISOLATE); - return rc; - } - - return 0; -} - -#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE - -static DEFINE_MUTEX(pseries_cpu_hotplug_mutex); - -void cpu_hotplug_driver_lock() -{ - mutex_lock(&pseries_cpu_hotplug_mutex); -} - -void cpu_hotplug_driver_unlock() -{ - mutex_unlock(&pseries_cpu_hotplug_mutex); -} - -static int dlpar_online_cpu(struct device_node *dn) -{ - int rc = 0; - unsigned int cpu; - int len, nthreads, i; - const u32 *intserv; - - intserv = of_get_property(dn, "ibm,ppc-interrupt-server#s", &len); - if (!intserv) - return -EINVAL; - - nthreads = len / sizeof(u32); - - cpu_maps_update_begin(); - for (i = 0; i < nthreads; i++) { - for_each_present_cpu(cpu) { - if (get_hard_smp_processor_id(cpu) != intserv[i]) - continue; - BUG_ON(get_cpu_current_state(cpu) - != CPU_STATE_OFFLINE); - cpu_maps_update_done(); - rc = cpu_up(cpu); - if (rc) - goto out; - cpu_maps_update_begin(); - - break; - } - if (cpu == num_possible_cpus()) - printk(KERN_WARNING "Could not find cpu to online " - "with physical id 0x%x\n", intserv[i]); - } - cpu_maps_update_done(); - -out: - return rc; - -} - -static ssize_t dlpar_cpu_probe(const char *buf, size_t count) -{ - struct device_node *dn; - unsigned long drc_index; - char *cpu_name; - int rc; - - cpu_hotplug_driver_lock(); - rc = strict_strtoul(buf, 0, &drc_index); - if (rc) { - rc = -EINVAL; - goto out; - } - - dn = dlpar_configure_connector(drc_index); - if (!dn) { - rc = -EINVAL; - goto out; - } - - /* configure-connector reports cpus as living in the base - * directory of the device tree. CPUs actually live in the - * cpus directory so we need to fixup the full_name. - */ - cpu_name = kzalloc(strlen(dn->full_name) + strlen("/cpus") + 1, - GFP_KERNEL); - if (!cpu_name) { - dlpar_free_cc_nodes(dn); - rc = -ENOMEM; - goto out; - } - - sprintf(cpu_name, "/cpus%s", dn->full_name); - kfree(dn->full_name); - dn->full_name = cpu_name; - - rc = dlpar_acquire_drc(drc_index); - if (rc) { - dlpar_free_cc_nodes(dn); - rc = -EINVAL; - goto out; - } - - rc = dlpar_attach_node(dn); - if (rc) { - dlpar_release_drc(drc_index); - dlpar_free_cc_nodes(dn); - } - - rc = dlpar_online_cpu(dn); -out: - cpu_hotplug_driver_unlock(); - - return rc ? rc : count; -} - -static int dlpar_offline_cpu(struct device_node *dn) -{ - int rc = 0; - unsigned int cpu; - int len, nthreads, i; - const u32 *intserv; - - intserv = of_get_property(dn, "ibm,ppc-interrupt-server#s", &len); - if (!intserv) - return -EINVAL; - - nthreads = len / sizeof(u32); - - cpu_maps_update_begin(); - for (i = 0; i < nthreads; i++) { - for_each_present_cpu(cpu) { - if (get_hard_smp_processor_id(cpu) != intserv[i]) - continue; - - if (get_cpu_current_state(cpu) == CPU_STATE_OFFLINE) - break; - - if (get_cpu_current_state(cpu) == CPU_STATE_ONLINE) { - cpu_maps_update_done(); - rc = cpu_down(cpu); - if (rc) - goto out; - cpu_maps_update_begin(); - break; - - } - - /* - * The cpu is in CPU_STATE_INACTIVE. - * Upgrade it's state to CPU_STATE_OFFLINE. - */ - set_preferred_offline_state(cpu, CPU_STATE_OFFLINE); - BUG_ON(plpar_hcall_norets(H_PROD, intserv[i]) - != H_SUCCESS); - __cpu_die(cpu); - break; - } - if (cpu == num_possible_cpus()) - printk(KERN_WARNING "Could not find cpu to offline " - "with physical id 0x%x\n", intserv[i]); - } - cpu_maps_update_done(); - -out: - return rc; - -} - -static ssize_t dlpar_cpu_release(const char *buf, size_t count) -{ - struct device_node *dn; - const u32 *drc_index; - int rc; - - dn = of_find_node_by_path(buf); - if (!dn) - return -EINVAL; - - drc_index = of_get_property(dn, "ibm,my-drc-index", NULL); - if (!drc_index) { - of_node_put(dn); - return -EINVAL; - } - - cpu_hotplug_driver_lock(); - rc = dlpar_offline_cpu(dn); - if (rc) { - of_node_put(dn); - rc = -EINVAL; - goto out; - } - - rc = dlpar_release_drc(*drc_index); - if (rc) { - of_node_put(dn); - goto out; - } - - rc = dlpar_detach_node(dn); - if (rc) { - dlpar_acquire_drc(*drc_index); - goto out; - } - - of_node_put(dn); -out: - cpu_hotplug_driver_unlock(); - return rc ? rc : count; -} - -static int __init pseries_dlpar_init(void) -{ - ppc_md.cpu_probe = dlpar_cpu_probe; - ppc_md.cpu_release = dlpar_cpu_release; - - return 0; -} -machine_device_initcall(pseries, pseries_dlpar_init); - -#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ diff --git a/trunk/arch/powerpc/platforms/pseries/eeh_driver.c b/trunk/arch/powerpc/platforms/pseries/eeh_driver.c index ef8e45448480..0e8db6771252 100644 --- a/trunk/arch/powerpc/platforms/pseries/eeh_driver.c +++ b/trunk/arch/powerpc/platforms/pseries/eeh_driver.c @@ -63,6 +63,22 @@ static void print_device_node_tree(struct pci_dn *pdn, int dent) } #endif +/** + * irq_in_use - return true if this irq is being used + */ +static int irq_in_use(unsigned int irq) +{ + int rc = 0; + unsigned long flags; + struct irq_desc *desc = irq_desc + irq; + + spin_lock_irqsave(&desc->lock, flags); + if (desc->action) + rc = 1; + spin_unlock_irqrestore(&desc->lock, flags); + return rc; +} + /** * eeh_disable_irq - disable interrupt for the recovering device */ @@ -77,7 +93,7 @@ static void eeh_disable_irq(struct pci_dev *dev) if (dev->msi_enabled || dev->msix_enabled) return; - if (!irq_has_action(dev->irq)) + if (!irq_in_use(dev->irq)) return; PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED; diff --git a/trunk/arch/powerpc/platforms/pseries/hotplug-cpu.c b/trunk/arch/powerpc/platforms/pseries/hotplug-cpu.c index 6ea4698d9176..ebff6d9a4e39 100644 --- a/trunk/arch/powerpc/platforms/pseries/hotplug-cpu.c +++ b/trunk/arch/powerpc/platforms/pseries/hotplug-cpu.c @@ -30,7 +30,6 @@ #include #include "xics.h" #include "plpar_wrappers.h" -#include "offline_states.h" /* This version can't take the spinlock, because it never returns */ static struct rtas_args rtas_stop_self_args = { @@ -40,55 +39,6 @@ static struct rtas_args rtas_stop_self_args = { .rets = &rtas_stop_self_args.args[0], }; -static DEFINE_PER_CPU(enum cpu_state_vals, preferred_offline_state) = - CPU_STATE_OFFLINE; -static DEFINE_PER_CPU(enum cpu_state_vals, current_state) = CPU_STATE_OFFLINE; - -static enum cpu_state_vals default_offline_state = CPU_STATE_OFFLINE; - -static int cede_offline_enabled __read_mostly = 1; - -/* - * Enable/disable cede_offline when available. - */ -static int __init setup_cede_offline(char *str) -{ - if (!strcmp(str, "off")) - cede_offline_enabled = 0; - else if (!strcmp(str, "on")) - cede_offline_enabled = 1; - else - return 0; - return 1; -} - -__setup("cede_offline=", setup_cede_offline); - -enum cpu_state_vals get_cpu_current_state(int cpu) -{ - return per_cpu(current_state, cpu); -} - -void set_cpu_current_state(int cpu, enum cpu_state_vals state) -{ - per_cpu(current_state, cpu) = state; -} - -enum cpu_state_vals get_preferred_offline_state(int cpu) -{ - return per_cpu(preferred_offline_state, cpu); -} - -void set_preferred_offline_state(int cpu, enum cpu_state_vals state) -{ - per_cpu(preferred_offline_state, cpu) = state; -} - -void set_default_offline_state(int cpu) -{ - per_cpu(preferred_offline_state, cpu) = default_offline_state; -} - static void rtas_stop_self(void) { struct rtas_args *args = &rtas_stop_self_args; @@ -106,61 +56,11 @@ static void rtas_stop_self(void) static void pseries_mach_cpu_die(void) { - unsigned int cpu = smp_processor_id(); - unsigned int hwcpu = hard_smp_processor_id(); - u8 cede_latency_hint = 0; - local_irq_disable(); idle_task_exit(); xics_teardown_cpu(); - - if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) { - set_cpu_current_state(cpu, CPU_STATE_INACTIVE); - cede_latency_hint = 2; - - get_lppaca()->idle = 1; - if (!get_lppaca()->shared_proc) - get_lppaca()->donate_dedicated_cpu = 1; - - printk(KERN_INFO - "cpu %u (hwid %u) ceding for offline with hint %d\n", - cpu, hwcpu, cede_latency_hint); - while (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) { - extended_cede_processor(cede_latency_hint); - printk(KERN_INFO "cpu %u (hwid %u) returned from cede.\n", - cpu, hwcpu); - printk(KERN_INFO - "Decrementer value = %x Timebase value = %llx\n", - get_dec(), get_tb()); - } - - printk(KERN_INFO "cpu %u (hwid %u) got prodded to go online\n", - cpu, hwcpu); - - if (!get_lppaca()->shared_proc) - get_lppaca()->donate_dedicated_cpu = 0; - get_lppaca()->idle = 0; - } - - if (get_preferred_offline_state(cpu) == CPU_STATE_ONLINE) { - unregister_slb_shadow(hwcpu, __pa(get_slb_shadow())); - - /* - * NOTE: Calling start_secondary() here for now to - * start new context. - * However, need to do it cleanly by resetting the - * stack pointer. - */ - start_secondary(); - - } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) { - - set_cpu_current_state(cpu, CPU_STATE_OFFLINE); - unregister_slb_shadow(hard_smp_processor_id(), - __pa(get_slb_shadow())); - rtas_stop_self(); - } - + unregister_slb_shadow(hard_smp_processor_id(), __pa(get_slb_shadow())); + rtas_stop_self(); /* Should never get here... */ BUG(); for(;;); @@ -206,43 +106,18 @@ static int pseries_cpu_disable(void) return 0; } -/* - * pseries_cpu_die: Wait for the cpu to die. - * @cpu: logical processor id of the CPU whose death we're awaiting. - * - * This function is called from the context of the thread which is performing - * the cpu-offline. Here we wait for long enough to allow the cpu in question - * to self-destroy so that the cpu-offline thread can send the CPU_DEAD - * notifications. - * - * OTOH, pseries_mach_cpu_die() is called by the @cpu when it wants to - * self-destruct. - */ static void pseries_cpu_die(unsigned int cpu) { int tries; - int cpu_status = 1; + int cpu_status; unsigned int pcpu = get_hard_smp_processor_id(cpu); - if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) { - cpu_status = 1; - for (tries = 0; tries < 1000; tries++) { - if (get_cpu_current_state(cpu) == CPU_STATE_INACTIVE) { - cpu_status = 0; - break; - } - cpu_relax(); - } - } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) { - - for (tries = 0; tries < 25; tries++) { - cpu_status = query_cpu_stopped(pcpu); - if (cpu_status == 0 || cpu_status == -1) - break; - cpu_relax(); - } + for (tries = 0; tries < 25; tries++) { + cpu_status = query_cpu_stopped(pcpu); + if (cpu_status == 0 || cpu_status == -1) + break; + cpu_relax(); } - if (cpu_status != 0) { printk("Querying DEAD? cpu %i (%i) shows %i\n", cpu, pcpu, cpu_status); @@ -377,41 +252,10 @@ static struct notifier_block pseries_smp_nb = { .notifier_call = pseries_smp_notifier, }; -#define MAX_CEDE_LATENCY_LEVELS 4 -#define CEDE_LATENCY_PARAM_LENGTH 10 -#define CEDE_LATENCY_PARAM_MAX_LENGTH \ - (MAX_CEDE_LATENCY_LEVELS * CEDE_LATENCY_PARAM_LENGTH * sizeof(char)) -#define CEDE_LATENCY_TOKEN 45 - -static char cede_parameters[CEDE_LATENCY_PARAM_MAX_LENGTH]; - -static int parse_cede_parameters(void) -{ - int call_status; - - memset(cede_parameters, 0, CEDE_LATENCY_PARAM_MAX_LENGTH); - call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, - NULL, - CEDE_LATENCY_TOKEN, - __pa(cede_parameters), - CEDE_LATENCY_PARAM_MAX_LENGTH); - - if (call_status != 0) - printk(KERN_INFO "CEDE_LATENCY: \ - %s %s Error calling get-system-parameter(0x%x)\n", - __FILE__, __func__, call_status); - else - printk(KERN_INFO "CEDE_LATENCY: \ - get-system-parameter successful.\n"); - - return call_status; -} - static int __init pseries_cpu_hotplug_init(void) { struct device_node *np; const char *typep; - int cpu; for_each_node_by_name(np, "interrupt-controller") { typep = of_get_property(np, "compatible", NULL); @@ -439,16 +283,8 @@ static int __init pseries_cpu_hotplug_init(void) smp_ops->cpu_die = pseries_cpu_die; /* Processors can be added/removed only on LPAR */ - if (firmware_has_feature(FW_FEATURE_LPAR)) { + if (firmware_has_feature(FW_FEATURE_LPAR)) pSeries_reconfig_notifier_register(&pseries_smp_nb); - cpu_maps_update_begin(); - if (cede_offline_enabled && parse_cede_parameters() == 0) { - default_offline_state = CPU_STATE_INACTIVE; - for_each_online_cpu(cpu) - set_default_offline_state(cpu); - } - cpu_maps_update_done(); - } return 0; } diff --git a/trunk/arch/powerpc/platforms/pseries/offline_states.h b/trunk/arch/powerpc/platforms/pseries/offline_states.h deleted file mode 100644 index 22574e0d9d91..000000000000 --- a/trunk/arch/powerpc/platforms/pseries/offline_states.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _OFFLINE_STATES_H_ -#define _OFFLINE_STATES_H_ - -/* Cpu offline states go here */ -enum cpu_state_vals { - CPU_STATE_OFFLINE, - CPU_STATE_INACTIVE, - CPU_STATE_ONLINE, - CPU_MAX_OFFLINE_STATES -}; - -extern enum cpu_state_vals get_cpu_current_state(int cpu); -extern void set_cpu_current_state(int cpu, enum cpu_state_vals state); -extern enum cpu_state_vals get_preferred_offline_state(int cpu); -extern void set_preferred_offline_state(int cpu, enum cpu_state_vals state); -extern void set_default_offline_state(int cpu); -extern int start_secondary(void); -#endif diff --git a/trunk/arch/powerpc/platforms/pseries/plpar_wrappers.h b/trunk/arch/powerpc/platforms/pseries/plpar_wrappers.h index 0603c91538ae..a24a6b2333b2 100644 --- a/trunk/arch/powerpc/platforms/pseries/plpar_wrappers.h +++ b/trunk/arch/powerpc/platforms/pseries/plpar_wrappers.h @@ -9,33 +9,11 @@ static inline long poll_pending(void) return plpar_hcall_norets(H_POLL_PENDING); } -static inline u8 get_cede_latency_hint(void) -{ - return get_lppaca()->gpr5_dword.fields.cede_latency_hint; -} - -static inline void set_cede_latency_hint(u8 latency_hint) -{ - get_lppaca()->gpr5_dword.fields.cede_latency_hint = latency_hint; -} - static inline long cede_processor(void) { return plpar_hcall_norets(H_CEDE); } -static inline long extended_cede_processor(unsigned long latency_hint) -{ - long rc; - u8 old_latency_hint = get_cede_latency_hint(); - - set_cede_latency_hint(latency_hint); - rc = cede_processor(); - set_cede_latency_hint(old_latency_hint); - - return rc; -} - static inline long vpa_call(unsigned long flags, unsigned long cpu, unsigned long vpa) { diff --git a/trunk/arch/powerpc/platforms/pseries/reconfig.c b/trunk/arch/powerpc/platforms/pseries/reconfig.c index a2305d29bbbd..2e2bbe120b90 100644 --- a/trunk/arch/powerpc/platforms/pseries/reconfig.c +++ b/trunk/arch/powerpc/platforms/pseries/reconfig.c @@ -96,7 +96,7 @@ static struct device_node *derive_parent(const char *path) return parent; } -BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain); +static BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain); int pSeries_reconfig_notifier_register(struct notifier_block *nb) { @@ -184,7 +184,7 @@ static int pSeries_reconfig_remove_node(struct device_node *np) } /* - * /proc/powerpc/ofdt - yucky binary interface for adding and removing + * /proc/ppc64/ofdt - yucky binary interface for adding and removing * OF device nodes. Should be deprecated as soon as we get an * in-kernel wrapper for the RTAS ibm,configure-connector call. */ @@ -543,7 +543,7 @@ static const struct file_operations ofdt_fops = { .write = ofdt_write }; -/* create /proc/powerpc/ofdt write-only by root */ +/* create /proc/ppc64/ofdt write-only by root */ static int proc_ppc64_create_ofdt(void) { struct proc_dir_entry *ent; @@ -551,7 +551,7 @@ static int proc_ppc64_create_ofdt(void) if (!machine_is(pseries)) return 0; - ent = proc_create("powerpc/ofdt", S_IWUSR, NULL, &ofdt_fops); + ent = proc_create("ppc64/ofdt", S_IWUSR, NULL, &ofdt_fops); if (ent) ent->size = 0; diff --git a/trunk/arch/powerpc/kernel/rtasd.c b/trunk/arch/powerpc/platforms/pseries/rtasd.c similarity index 95% rename from trunk/arch/powerpc/kernel/rtasd.c rename to trunk/arch/powerpc/platforms/pseries/rtasd.c index 2e4832ab2108..b3cbac855924 100644 --- a/trunk/arch/powerpc/kernel/rtasd.c +++ b/trunk/arch/powerpc/platforms/pseries/rtasd.c @@ -39,7 +39,6 @@ static unsigned long rtas_log_start; static unsigned long rtas_log_size; static int surveillance_timeout = -1; - static unsigned int rtas_error_log_max; static unsigned int rtas_error_log_buffer_max; @@ -214,11 +213,9 @@ void pSeries_log_error(char *buf, unsigned int err_type, int fatal) return; } -#ifdef CONFIG_PPC64 /* Write error to NVRAM */ if (logging_enabled && !(err_type & ERR_FLAG_BOOT)) nvram_write_error_log(buf, len, err_type, error_log_cnt); -#endif /* CONFIG_PPC64 */ /* * rtas errors can occur during boot, and we do want to capture @@ -267,6 +264,7 @@ void pSeries_log_error(char *buf, unsigned int err_type, int fatal) } + static int rtas_log_open(struct inode * inode, struct file * file) { return 0; @@ -302,7 +300,6 @@ static ssize_t rtas_log_read(struct file * file, char __user * buf, return -ENOMEM; spin_lock_irqsave(&rtasd_log_lock, s); - /* if it's 0, then we know we got the last one (the one in NVRAM) */ while (rtas_log_size == 0) { if (file->f_flags & O_NONBLOCK) { @@ -316,9 +313,7 @@ static ssize_t rtas_log_read(struct file * file, char __user * buf, error = -ENODATA; goto out; } -#ifdef CONFIG_PPC64 nvram_clear_error_log(); -#endif /* CONFIG_PPC64 */ spin_unlock_irqrestore(&rtasd_log_lock, s); error = wait_event_interruptible(rtas_log_wait, rtas_log_size); @@ -432,11 +427,14 @@ static void rtas_event_scan(struct work_struct *w) put_online_cpus(); } -#ifdef CONFIG_PPC64 -static void retreive_nvram_error_log(void) +static void start_event_scan(void) { - unsigned int err_type ; - int rc ; + unsigned int err_type; + int rc; + + printk(KERN_DEBUG "RTAS daemon started\n"); + pr_debug("rtasd: will sleep for %d milliseconds\n", + (30000 / rtas_event_scan_rate)); /* See if we have any error stored in NVRAM */ memset(logdata, 0, rtas_error_log_max); @@ -444,26 +442,12 @@ static void retreive_nvram_error_log(void) &err_type, &error_log_cnt); /* We can use rtas_log_buf now */ logging_enabled = 1; + if (!rc) { if (err_type != ERR_FLAG_ALREADY_LOGGED) { pSeries_log_error(logdata, err_type | ERR_FLAG_BOOT, 0); } } -} -#else /* CONFIG_PPC64 */ -static void retreive_nvram_error_log(void) -{ -} -#endif /* CONFIG_PPC64 */ - -static void start_event_scan(void) -{ - printk(KERN_DEBUG "RTAS daemon started\n"); - pr_debug("rtasd: will sleep for %d milliseconds\n", - (30000 / rtas_event_scan_rate)); - - /* Retreive errors from nvram if any */ - retreive_nvram_error_log(); schedule_delayed_work_on(first_cpu(cpu_online_map), &event_scan_work, event_scan_delay); @@ -473,13 +457,13 @@ static int __init rtas_init(void) { struct proc_dir_entry *entry; - if (!machine_is(pseries) && !machine_is(chrp)) + if (!machine_is(pseries)) return 0; /* No RTAS */ event_scan = rtas_token("event-scan"); if (event_scan == RTAS_UNKNOWN_SERVICE) { - printk(KERN_INFO "rtasd: No event-scan on system\n"); + printk(KERN_DEBUG "rtasd: no event-scan on system\n"); return -ENODEV; } @@ -499,7 +483,7 @@ static int __init rtas_init(void) return -ENOMEM; } - entry = proc_create("powerpc/rtas/error_log", S_IRUSR, NULL, + entry = proc_create("ppc64/rtas/error_log", S_IRUSR, NULL, &proc_rtas_log_operations); if (!entry) printk(KERN_ERR "Failed to create error_log proc entry\n"); @@ -508,16 +492,11 @@ static int __init rtas_init(void) return 0; } -__initcall(rtas_init); static int __init surveillance_setup(char *str) { int i; - /* We only do surveillance on pseries */ - if (!machine_is(pseries)) - return 0; - if (get_option(&str,&i)) { if (i >= 0 && i <= 255) surveillance_timeout = i; @@ -525,7 +504,6 @@ static int __init surveillance_setup(char *str) return 1; } -__setup("surveillance=", surveillance_setup); static int __init rtasmsgs_setup(char *str) { @@ -536,4 +514,6 @@ static int __init rtasmsgs_setup(char *str) return 1; } +__initcall(rtas_init); +__setup("surveillance=", surveillance_setup); __setup("rtasmsgs=", rtasmsgs_setup); diff --git a/trunk/arch/powerpc/platforms/pseries/scanlog.c b/trunk/arch/powerpc/platforms/pseries/scanlog.c index 1b45c458f952..417eca79df69 100644 --- a/trunk/arch/powerpc/platforms/pseries/scanlog.c +++ b/trunk/arch/powerpc/platforms/pseries/scanlog.c @@ -13,7 +13,7 @@ * of this data using this driver. A dump exists if the device-tree * /chosen/ibm,scan-log-data property exists. * - * This driver exports /proc/powerpc/scan-log-dump which can be read. + * This driver exports /proc/ppc64/scan-log-dump which can be read. * The driver supports only sequential reads. * * The driver looks at a write to the driver for the single word "reset". @@ -186,7 +186,7 @@ static int __init scanlog_init(void) if (!data) goto err; - ent = proc_create_data("powerpc/rtas/scan-log-dump", S_IRUSR, NULL, + ent = proc_create_data("ppc64/rtas/scan-log-dump", S_IRUSR, NULL, &scanlog_fops, data); if (!ent) goto err; diff --git a/trunk/arch/powerpc/platforms/pseries/smp.c b/trunk/arch/powerpc/platforms/pseries/smp.c index 8868c012268a..440000cc7130 100644 --- a/trunk/arch/powerpc/platforms/pseries/smp.c +++ b/trunk/arch/powerpc/platforms/pseries/smp.c @@ -48,7 +48,6 @@ #include "plpar_wrappers.h" #include "pseries.h" #include "xics.h" -#include "offline_states.h" /* @@ -85,9 +84,6 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu) /* Fixup atomic count: it exited inside IRQ handler. */ task_thread_info(paca[lcpu].__current)->preempt_count = 0; - if (get_cpu_current_state(lcpu) == CPU_STATE_INACTIVE) - goto out; - /* * If the RTAS start-cpu token does not exist then presume the * cpu is already spinning. @@ -102,7 +98,6 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu) return 0; } -out: return 1; } @@ -116,16 +111,12 @@ static void __devinit smp_xics_setup_cpu(int cpu) vpa_init(cpu); cpu_clear(cpu, of_spin_map); - set_cpu_current_state(cpu, CPU_STATE_ONLINE); - set_default_offline_state(cpu); } #endif /* CONFIG_XICS */ static void __devinit smp_pSeries_kick_cpu(int nr) { - long rc; - unsigned long hcpuid; BUG_ON(nr < 0 || nr >= NR_CPUS); if (!smp_startup_cpu(nr)) @@ -137,16 +128,6 @@ static void __devinit smp_pSeries_kick_cpu(int nr) * the processor will continue on to secondary_start */ paca[nr].cpu_start = 1; - - set_preferred_offline_state(nr, CPU_STATE_ONLINE); - - if (get_cpu_current_state(nr) == CPU_STATE_INACTIVE) { - hcpuid = get_hard_smp_processor_id(nr); - rc = plpar_hcall_norets(H_PROD, hcpuid); - if (rc != H_SUCCESS) - panic("Error: Prod to wake up processor %d Ret= %ld\n", - nr, rc); - } } static int smp_pSeries_cpu_bootable(unsigned int nr) diff --git a/trunk/arch/powerpc/platforms/pseries/xics.c b/trunk/arch/powerpc/platforms/pseries/xics.c index 7d01b58f3989..b9bf0eedccf2 100644 --- a/trunk/arch/powerpc/platforms/pseries/xics.c +++ b/trunk/arch/powerpc/platforms/pseries/xics.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -47,12 +46,6 @@ static struct irq_host *xics_host; */ #define IPI_PRIORITY 4 -/* The least favored priority */ -#define LOWEST_PRIORITY 0xFF - -/* The number of priorities defined above */ -#define MAX_NUM_PRIORITIES 3 - static unsigned int default_server = 0xFF; static unsigned int default_distrib_server = 0; static unsigned int interrupt_server_size = 8; @@ -63,12 +56,6 @@ static int ibm_set_xive; static int ibm_int_on; static int ibm_int_off; -struct xics_cppr { - unsigned char stack[MAX_NUM_PRIORITIES]; - int index; -}; - -static DEFINE_PER_CPU(struct xics_cppr, xics_cppr); /* Direct hardware low level accessors */ @@ -170,7 +157,7 @@ static int get_irq_server(unsigned int virq, unsigned int strict_check) cpumask_t cpumask; cpumask_t tmp = CPU_MASK_NONE; - cpumask_copy(&cpumask, irq_to_desc(virq)->affinity); + cpumask_copy(&cpumask, irq_desc[virq].affinity); if (!distribute_irqs) return default_server; @@ -297,19 +284,6 @@ static inline unsigned int xics_xirr_vector(unsigned int xirr) return xirr & 0x00ffffff; } -static void push_cppr(unsigned int vec) -{ - struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); - - if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1)) - return; - - if (vec == XICS_IPI) - os_cppr->stack[++os_cppr->index] = IPI_PRIORITY; - else - os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY; -} - static unsigned int xics_get_irq_direct(void) { unsigned int xirr = direct_xirr_info_get(); @@ -320,10 +294,8 @@ static unsigned int xics_get_irq_direct(void) return NO_IRQ; irq = irq_radix_revmap_lookup(xics_host, vec); - if (likely(irq != NO_IRQ)) { - push_cppr(vec); + if (likely(irq != NO_IRQ)) return irq; - } /* We don't have a linux mapping, so have rtas mask it. */ xics_mask_unknown_vec(vec); @@ -343,10 +315,8 @@ static unsigned int xics_get_irq_lpar(void) return NO_IRQ; irq = irq_radix_revmap_lookup(xics_host, vec); - if (likely(irq != NO_IRQ)) { - push_cppr(vec); + if (likely(irq != NO_IRQ)) return irq; - } /* We don't have a linux mapping, so have RTAS mask it. */ xics_mask_unknown_vec(vec); @@ -356,22 +326,12 @@ static unsigned int xics_get_irq_lpar(void) return NO_IRQ; } -static unsigned char pop_cppr(void) -{ - struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); - - if (WARN_ON(os_cppr->index < 1)) - return LOWEST_PRIORITY; - - return os_cppr->stack[--os_cppr->index]; -} - static void xics_eoi_direct(unsigned int virq) { unsigned int irq = (unsigned int)irq_map[virq].hwirq; iosync(); - direct_xirr_info_set((pop_cppr() << 24) | irq); + direct_xirr_info_set((0xff << 24) | irq); } static void xics_eoi_lpar(unsigned int virq) @@ -379,7 +339,7 @@ static void xics_eoi_lpar(unsigned int virq) unsigned int irq = (unsigned int)irq_map[virq].hwirq; iosync(); - lpar_xirr_info_set((pop_cppr() << 24) | irq); + lpar_xirr_info_set((0xff << 24) | irq); } static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) @@ -428,7 +388,7 @@ static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) } static struct irq_chip xics_pic_direct = { - .name = " XICS ", + .typename = " XICS ", .startup = xics_startup, .mask = xics_mask_irq, .unmask = xics_unmask_irq, @@ -437,7 +397,7 @@ static struct irq_chip xics_pic_direct = { }; static struct irq_chip xics_pic_lpar = { - .name = " XICS ", + .typename = " XICS ", .startup = xics_startup, .mask = xics_mask_irq, .unmask = xics_unmask_irq, @@ -468,13 +428,13 @@ static int xics_host_map(struct irq_host *h, unsigned int virq, /* Insert the interrupt mapping into the radix tree for fast lookup */ irq_radix_revmap_insert(xics_host, virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); return 0; } static int xics_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { @@ -786,12 +746,6 @@ void __init xics_init_IRQ(void) static void xics_set_cpu_priority(unsigned char cppr) { - struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); - - BUG_ON(os_cppr->index != 0); - - os_cppr->stack[os_cppr->index] = cppr; - if (firmware_has_feature(FW_FEATURE_LPAR)) lpar_cppr_info(cppr); else @@ -818,7 +772,7 @@ static void xics_set_cpu_giq(unsigned int gserver, unsigned int join) void xics_setup_cpu(void) { - xics_set_cpu_priority(LOWEST_PRIORITY); + xics_set_cpu_priority(0xff); xics_set_cpu_giq(default_distrib_server, 1); } @@ -898,7 +852,7 @@ void xics_migrate_irqs_away(void) /* We need to get IPIs still. */ if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) continue; - desc = irq_to_desc(virq); + desc = get_irq_desc(virq); /* We only need to migrate enabled IRQS */ if (desc == NULL || desc->chip == NULL @@ -927,7 +881,7 @@ void xics_migrate_irqs_away(void) virq, cpu); /* Reset affinity to all cpus */ - cpumask_setall(irq_to_desc(virq)->affinity); + cpumask_setall(irq_desc[virq].affinity); desc->chip->set_affinity(virq, cpu_all_mask); unlock: spin_unlock_irqrestore(&desc->lock, flags); diff --git a/trunk/arch/powerpc/sysdev/Makefile b/trunk/arch/powerpc/sysdev/Makefile index 5642924fb9fb..9d4b17462f13 100644 --- a/trunk/arch/powerpc/sysdev/Makefile +++ b/trunk/arch/powerpc/sysdev/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) -obj-$(CONFIG_FSL_PMC) += fsl_pmc.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_FSL_GTM) += fsl_gtm.o obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o diff --git a/trunk/arch/powerpc/sysdev/cpm1.c b/trunk/arch/powerpc/sysdev/cpm1.c index a4b41dbde128..82424cd7e128 100644 --- a/trunk/arch/powerpc/sysdev/cpm1.c +++ b/trunk/arch/powerpc/sysdev/cpm1.c @@ -77,7 +77,7 @@ static void cpm_end_irq(unsigned int irq) } static struct irq_chip cpm_pic = { - .name = " CPM PIC ", + .typename = " CPM PIC ", .mask = cpm_mask_irq, .unmask = cpm_unmask_irq, .eoi = cpm_end_irq, @@ -102,7 +102,7 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, { pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); return 0; } diff --git a/trunk/arch/powerpc/sysdev/cpm2_pic.c b/trunk/arch/powerpc/sysdev/cpm2_pic.c index 971483f0dfac..78f1f7cca0a0 100644 --- a/trunk/arch/powerpc/sysdev/cpm2_pic.c +++ b/trunk/arch/powerpc/sysdev/cpm2_pic.c @@ -115,13 +115,11 @@ static void cpm2_ack(unsigned int virq) static void cpm2_end_irq(unsigned int virq) { - struct irq_desc *desc; int bit, word; unsigned int irq_nr = virq_to_hw(virq); - desc = irq_to_desc(irq_nr); - if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) - && desc->action) { + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) + && irq_desc[irq_nr].action) { bit = irq_to_siubit[irq_nr]; word = irq_to_siureg[irq_nr]; @@ -140,7 +138,7 @@ static void cpm2_end_irq(unsigned int virq) static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type) { unsigned int src = virq_to_hw(virq); - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); unsigned int vold, vnew, edibit; if (flow_type == IRQ_TYPE_NONE) @@ -184,7 +182,7 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type) } static struct irq_chip cpm2_pic = { - .name = " CPM2 SIU ", + .typename = " CPM2 SIU ", .mask = cpm2_mask_irq, .unmask = cpm2_unmask_irq, .ack = cpm2_ack, @@ -212,13 +210,13 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq, { pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq); return 0; } static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { *out_hwirq = intspec[0]; diff --git a/trunk/arch/powerpc/sysdev/cpm_common.c b/trunk/arch/powerpc/sysdev/cpm_common.c index 9de72c96e6d1..e4b6d66d93de 100644 --- a/trunk/arch/powerpc/sysdev/cpm_common.c +++ b/trunk/arch/powerpc/sysdev/cpm_common.c @@ -72,7 +72,7 @@ static phys_addr_t muram_pbase; /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 -int cpm_muram_init(void) +int __init cpm_muram_init(void) { struct device_node *np; struct resource r; @@ -81,9 +81,6 @@ int cpm_muram_init(void) int i = 0; int ret = 0; - if (muram_pbase) - return 0; - spin_lock_init(&cpm_muram_lock); /* initialize the info header */ rh_init(&cpm_muram_info, 1, diff --git a/trunk/arch/powerpc/sysdev/fsl_msi.c b/trunk/arch/powerpc/sysdev/fsl_msi.c index 62e50258cdef..da38a1ff97bb 100644 --- a/trunk/arch/powerpc/sysdev/fsl_msi.c +++ b/trunk/arch/powerpc/sysdev/fsl_msi.c @@ -47,7 +47,7 @@ static struct irq_chip fsl_msi_chip = { .mask = mask_msi_irq, .unmask = unmask_msi_irq, .ack = fsl_msi_end_irq, - .name = " FSL-MSI ", + .typename = " FSL-MSI ", }; static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, @@ -55,7 +55,7 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, { struct irq_chip *chip = &fsl_msi_chip; - irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; + get_irq_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; set_irq_chip_and_handler(virq, chip, handle_edge_irq); diff --git a/trunk/arch/powerpc/sysdev/fsl_pci.c b/trunk/arch/powerpc/sysdev/fsl_pci.c index 4e3a3e345ab3..ae88b1448018 100644 --- a/trunk/arch/powerpc/sysdev/fsl_pci.c +++ b/trunk/arch/powerpc/sysdev/fsl_pci.c @@ -56,7 +56,7 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) +#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, unsigned int index, const struct resource *res, resource_size_t offset) @@ -392,23 +392,9 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header); DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header); -DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header); -#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ +#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header); diff --git a/trunk/arch/powerpc/sysdev/fsl_pmc.c b/trunk/arch/powerpc/sysdev/fsl_pmc.c deleted file mode 100644 index a7635a993dca..000000000000 --- a/trunk/arch/powerpc/sysdev/fsl_pmc.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Suspend/resume support - * - * Copyright 2009 MontaVista Software, Inc. - * - * Author: Anton Vorontsov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -struct pmc_regs { - __be32 devdisr; - __be32 devdisr2; - __be32 :32; - __be32 :32; - __be32 pmcsr; -#define PMCSR_SLP (1 << 17) -}; - -static struct device *pmc_dev; -static struct pmc_regs __iomem *pmc_regs; - -static int pmc_suspend_enter(suspend_state_t state) -{ - int ret; - - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); - /* At this point, the CPU is asleep. */ - - /* Upon resume, wait for SLP bit to be clear. */ - ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP) == 0, - 10000, 10) ? 0 : -ETIMEDOUT; - if (ret) - dev_err(pmc_dev, "tired waiting for SLP bit to clear\n"); - return ret; -} - -static int pmc_suspend_valid(suspend_state_t state) -{ - if (state != PM_SUSPEND_STANDBY) - return 0; - return 1; -} - -static struct platform_suspend_ops pmc_suspend_ops = { - .valid = pmc_suspend_valid, - .enter = pmc_suspend_enter, -}; - -static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id) -{ - pmc_regs = of_iomap(ofdev->node, 0); - if (!pmc_regs) - return -ENOMEM; - - pmc_dev = &ofdev->dev; - suspend_set_ops(&pmc_suspend_ops); - return 0; -} - -static const struct of_device_id pmc_ids[] = { - { .compatible = "fsl,mpc8548-pmc", }, - { .compatible = "fsl,mpc8641d-pmc", }, - { }, -}; - -static struct of_platform_driver pmc_driver = { - .driver.name = "fsl-pmc", - .match_table = pmc_ids, - .probe = pmc_probe, -}; - -static int __init pmc_init(void) -{ - return of_register_platform_driver(&pmc_driver); -} -device_initcall(pmc_init); diff --git a/trunk/arch/powerpc/sysdev/fsl_soc.c b/trunk/arch/powerpc/sysdev/fsl_soc.c index b91f7acdda6f..adca4affcf1f 100644 --- a/trunk/arch/powerpc/sysdev/fsl_soc.c +++ b/trunk/arch/powerpc/sysdev/fsl_soc.c @@ -372,7 +372,7 @@ static int __init fsl_usb_of_init(void) arch_initcall(fsl_usb_of_init); -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) +#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) static __be32 __iomem *rstcr; static int __init setup_rstcr(void) diff --git a/trunk/arch/powerpc/sysdev/i8259.c b/trunk/arch/powerpc/sysdev/i8259.c index 0a55db8a5a29..a96584ab33dd 100644 --- a/trunk/arch/powerpc/sysdev/i8259.c +++ b/trunk/arch/powerpc/sysdev/i8259.c @@ -135,7 +135,7 @@ static void i8259_unmask_irq(unsigned int irq_nr) } static struct irq_chip i8259_pic = { - .name = " i8259 ", + .typename = " i8259 ", .mask = i8259_mask_irq, .disable = i8259_mask_irq, .unmask = i8259_unmask_irq, @@ -175,12 +175,12 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq, /* We block the internal cascade */ if (hw == 2) - irq_to_desc(virq)->status |= IRQ_NOREQUEST; + get_irq_desc(virq)->status |= IRQ_NOREQUEST; /* We use the level handler only for now, we might want to * be more cautious here but that works for now */ - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); return 0; } @@ -198,7 +198,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq) } static int i8259_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { static unsigned char map_isa_senses[4] = { diff --git a/trunk/arch/powerpc/sysdev/ipic.c b/trunk/arch/powerpc/sysdev/ipic.c index 28cdddd2f89e..cb7689c4bfbd 100644 --- a/trunk/arch/powerpc/sysdev/ipic.c +++ b/trunk/arch/powerpc/sysdev/ipic.c @@ -605,7 +605,7 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) { struct ipic *ipic = ipic_from_irq(virq); unsigned int src = ipic_irq_to_hw(virq); - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); unsigned int vold, vnew, edibit; if (flow_type == IRQ_TYPE_NONE) @@ -660,7 +660,7 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) /* level interrupts and edge interrupts have different ack operations */ static struct irq_chip ipic_level_irq_chip = { - .name = " IPIC ", + .typename = " IPIC ", .unmask = ipic_unmask_irq, .mask = ipic_mask_irq, .mask_ack = ipic_mask_irq, @@ -668,7 +668,7 @@ static struct irq_chip ipic_level_irq_chip = { }; static struct irq_chip ipic_edge_irq_chip = { - .name = " IPIC ", + .typename = " IPIC ", .unmask = ipic_unmask_irq, .mask = ipic_mask_irq, .mask_ack = ipic_mask_irq_and_ack, @@ -697,7 +697,7 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq, } static int ipic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/sysdev/mpc8xx_pic.c b/trunk/arch/powerpc/sysdev/mpc8xx_pic.c index 69bd6f4dff83..5d2d5522ef41 100644 --- a/trunk/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/trunk/arch/powerpc/sysdev/mpc8xx_pic.c @@ -72,7 +72,7 @@ static void mpc8xx_end_irq(unsigned int virq) static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; @@ -94,7 +94,7 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) } static struct irq_chip mpc8xx_pic = { - .name = " MPC8XX SIU ", + .typename = " MPC8XX SIU ", .unmask = mpc8xx_unmask_irq, .mask = mpc8xx_mask_irq, .ack = mpc8xx_ack, @@ -130,7 +130,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq, static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { static unsigned char map_pic_senses[4] = { diff --git a/trunk/arch/powerpc/sysdev/mpic.c b/trunk/arch/powerpc/sysdev/mpic.c index aa9d06e5925b..30c44e6b0413 100644 --- a/trunk/arch/powerpc/sysdev/mpic.c +++ b/trunk/arch/powerpc/sysdev/mpic.c @@ -572,7 +572,7 @@ static int irq_choose_cpu(unsigned int virt_irq) cpumask_t mask; int cpuid; - cpumask_copy(&mask, irq_to_desc(virt_irq)->affinity); + cpumask_copy(&mask, irq_desc[virt_irq].affinity); if (cpus_equal(mask, CPU_MASK_ALL)) { static int irq_rover; static DEFINE_SPINLOCK(irq_rover_lock); @@ -621,7 +621,7 @@ static struct mpic *mpic_find(unsigned int irq) if (irq < NUM_ISA_INTERRUPTS) return NULL; - return irq_to_desc(irq)->chip_data; + return irq_desc[irq].chip_data; } /* Determine if the linux irq is an IPI */ @@ -648,14 +648,14 @@ static inline u32 mpic_physmask(u32 cpumask) /* Get the mpic structure from the IPI number */ static inline struct mpic * mpic_from_ipi(unsigned int ipi) { - return irq_to_desc(ipi)->chip_data; + return irq_desc[ipi].chip_data; } #endif /* Get the mpic structure from the irq number */ static inline struct mpic * mpic_from_irq(unsigned int irq) { - return irq_to_desc(irq)->chip_data; + return irq_desc[irq].chip_data; } /* Send an EOI */ @@ -735,7 +735,7 @@ static void mpic_unmask_ht_irq(unsigned int irq) mpic_unmask_irq(irq); - if (irq_to_desc(irq)->status & IRQ_LEVEL) + if (irq_desc[irq].status & IRQ_LEVEL) mpic_ht_end_irq(mpic, src); } @@ -745,7 +745,7 @@ static unsigned int mpic_startup_ht_irq(unsigned int irq) unsigned int src = mpic_irq_to_hw(irq); mpic_unmask_irq(irq); - mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); + mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status); return 0; } @@ -755,7 +755,7 @@ static void mpic_shutdown_ht_irq(unsigned int irq) struct mpic *mpic = mpic_from_irq(irq); unsigned int src = mpic_irq_to_hw(irq); - mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); + mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status); mpic_mask_irq(irq); } @@ -772,7 +772,7 @@ static void mpic_end_ht_irq(unsigned int irq) * latched another edge interrupt coming in anyway */ - if (irq_to_desc(irq)->status & IRQ_LEVEL) + if (irq_desc[irq].status & IRQ_LEVEL) mpic_ht_end_irq(mpic, src); mpic_eoi(mpic); } @@ -856,7 +856,7 @@ int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) { struct mpic *mpic = mpic_from_irq(virq); unsigned int src = mpic_irq_to_hw(virq); - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); unsigned int vecpri, vold, vnew; DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", @@ -994,7 +994,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, } static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { @@ -1062,19 +1062,19 @@ struct mpic * __init mpic_alloc(struct device_node *node, mpic->name = name; mpic->hc_irq = mpic_irq_chip; - mpic->hc_irq.name = name; + mpic->hc_irq.typename = name; if (flags & MPIC_PRIMARY) mpic->hc_irq.set_affinity = mpic_set_affinity; #ifdef CONFIG_MPIC_U3_HT_IRQS mpic->hc_ht_irq = mpic_irq_ht_chip; - mpic->hc_ht_irq.name = name; + mpic->hc_ht_irq.typename = name; if (flags & MPIC_PRIMARY) mpic->hc_ht_irq.set_affinity = mpic_set_affinity; #endif /* CONFIG_MPIC_U3_HT_IRQS */ #ifdef CONFIG_SMP mpic->hc_ipi = mpic_ipi_chip; - mpic->hc_ipi.name = name; + mpic->hc_ipi.typename = name; #endif /* CONFIG_SMP */ mpic->flags = flags; diff --git a/trunk/arch/powerpc/sysdev/mpic_pasemi_msi.c b/trunk/arch/powerpc/sysdev/mpic_pasemi_msi.c index 0f6ab06f8474..656cb772b691 100644 --- a/trunk/arch/powerpc/sysdev/mpic_pasemi_msi.c +++ b/trunk/arch/powerpc/sysdev/mpic_pasemi_msi.c @@ -60,7 +60,7 @@ static struct irq_chip mpic_pasemi_msi_chip = { .eoi = mpic_end_irq, .set_type = mpic_set_irq_type, .set_affinity = mpic_set_affinity, - .name = "PASEMI-MSI ", + .typename = "PASEMI-MSI ", }; static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type) diff --git a/trunk/arch/powerpc/sysdev/mpic_u3msi.c b/trunk/arch/powerpc/sysdev/mpic_u3msi.c index d3caf23e6312..0a8f5a9e87c9 100644 --- a/trunk/arch/powerpc/sysdev/mpic_u3msi.c +++ b/trunk/arch/powerpc/sysdev/mpic_u3msi.c @@ -42,7 +42,7 @@ static struct irq_chip mpic_u3msi_chip = { .eoi = mpic_end_irq, .set_type = mpic_set_irq_type, .set_affinity = mpic_set_affinity, - .name = "MPIC-U3MSI", + .typename = "MPIC-U3MSI", }; static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) diff --git a/trunk/arch/powerpc/sysdev/mv64x60_pic.c b/trunk/arch/powerpc/sysdev/mv64x60_pic.c index 485b92477d7c..2aa4ed066db1 100644 --- a/trunk/arch/powerpc/sysdev/mv64x60_pic.c +++ b/trunk/arch/powerpc/sysdev/mv64x60_pic.c @@ -213,7 +213,7 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq, { int level1; - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; BUG_ON(level1 > MV64x60_LEVEL1_GPP); diff --git a/trunk/arch/powerpc/sysdev/qe_lib/qe.c b/trunk/arch/powerpc/sysdev/qe_lib/qe.c index 149393c02c3f..464271bea6c9 100644 --- a/trunk/arch/powerpc/sysdev/qe_lib/qe.c +++ b/trunk/arch/powerpc/sysdev/qe_lib/qe.c @@ -27,8 +27,6 @@ #include #include #include -#include -#include #include #include #include @@ -67,6 +65,19 @@ static unsigned int qe_num_of_snum; static phys_addr_t qebase = -1; +int qe_alive_during_sleep(void) +{ + static int ret = -1; + + if (ret != -1) + return ret; + + ret = !of_find_compatible_node(NULL, NULL, "fsl,mpc8569-pmc"); + + return ret; +} +EXPORT_SYMBOL(qe_alive_during_sleep); + phys_addr_t get_qe_base(void) { struct device_node *qe; @@ -93,7 +104,7 @@ phys_addr_t get_qe_base(void) EXPORT_SYMBOL(get_qe_base); -void qe_reset(void) +void __init qe_reset(void) { if (qe_immr == NULL) qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE); @@ -319,18 +330,16 @@ EXPORT_SYMBOL(qe_put_snum); static int qe_sdma_init(void) { struct sdma __iomem *sdma = &qe_immr->sdma; - static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM; + unsigned long sdma_buf_offset; if (!sdma) return -ENODEV; /* allocate 2 internal temporary buffers (512 bytes size each) for * the SDMA */ - if (IS_ERR_VALUE(sdma_buf_offset)) { - sdma_buf_offset = qe_muram_alloc(512 * 2, 4096); - if (IS_ERR_VALUE(sdma_buf_offset)) - return -ENOMEM; - } + sdma_buf_offset = qe_muram_alloc(512 * 2, 4096); + if (IS_ERR_VALUE(sdma_buf_offset)) + return -ENOMEM; out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK); out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | @@ -340,7 +349,7 @@ static int qe_sdma_init(void) } /* The maximum number of RISCs we support */ -#define MAX_QE_RISC 4 +#define MAX_QE_RISC 2 /* Firmware information stored here for qe_get_firmware_info() */ static struct qe_firmware_info qe_firmware_info; @@ -649,35 +658,3 @@ unsigned int qe_get_num_of_snums(void) return num_of_snums; } EXPORT_SYMBOL(qe_get_num_of_snums); - -#if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) -static int qe_resume(struct of_device *ofdev) -{ - if (!qe_alive_during_sleep()) - qe_reset(); - return 0; -} - -static int qe_probe(struct of_device *ofdev, const struct of_device_id *id) -{ - return 0; -} - -static const struct of_device_id qe_ids[] = { - { .compatible = "fsl,qe", }, - { }, -}; - -static struct of_platform_driver qe_driver = { - .driver.name = "fsl-qe", - .match_table = qe_ids, - .probe = qe_probe, - .resume = qe_resume, -}; - -static int __init qe_drv_init(void) -{ - return of_register_platform_driver(&qe_driver); -} -device_initcall(qe_drv_init); -#endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */ diff --git a/trunk/arch/powerpc/sysdev/qe_lib/qe_ic.c b/trunk/arch/powerpc/sysdev/qe_lib/qe_ic.c index 2acc928d1920..3faa42e03a85 100644 --- a/trunk/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/trunk/arch/powerpc/sysdev/qe_lib/qe_ic.c @@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) { - return irq_to_desc(virq)->chip_data; + return irq_desc[virq].chip_data; } #define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) @@ -237,7 +237,7 @@ static void qe_ic_mask_irq(unsigned int virq) } static struct irq_chip qe_ic_irq_chip = { - .name = " QEIC ", + .typename = " QEIC ", .unmask = qe_ic_unmask_irq, .mask = qe_ic_mask_irq, .mask_ack = qe_ic_mask_irq, @@ -263,7 +263,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq, chip = &qe_ic->hc_irq; set_irq_chip_data(virq, qe_ic); - irq_to_desc(virq)->status |= IRQ_LEVEL; + get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip_and_handler(virq, chip, handle_level_irq); @@ -271,7 +271,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq, } static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 * intspec, unsigned int intsize, + u32 * intspec, unsigned int intsize, irq_hw_number_t * out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/sysdev/tsi108_pci.c b/trunk/arch/powerpc/sysdev/tsi108_pci.c index 595034cfb85a..cf244a419e96 100644 --- a/trunk/arch/powerpc/sysdev/tsi108_pci.c +++ b/trunk/arch/powerpc/sysdev/tsi108_pci.c @@ -376,7 +376,7 @@ static void tsi108_pci_irq_end(u_int irq) */ static struct irq_chip tsi108_pci_irq = { - .name = "tsi108_PCI_int", + .typename = "tsi108_PCI_int", .mask = tsi108_pci_irq_disable, .ack = tsi108_pci_irq_ack, .end = tsi108_pci_irq_end, @@ -384,7 +384,7 @@ static struct irq_chip tsi108_pci_irq = { }; static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { *out_hwirq = intspec[0]; @@ -398,7 +398,7 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq, DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); if ((virq >= 1) && (virq <= 4)){ irq = virq + IRQ_PCI_INTAD_BASE - 1; - irq_to_desc(irq)->status |= IRQ_LEVEL; + get_irq_desc(irq)->status |= IRQ_LEVEL; set_irq_chip(irq, &tsi108_pci_irq); } return 0; diff --git a/trunk/arch/powerpc/sysdev/uic.c b/trunk/arch/powerpc/sysdev/uic.c index 7d10074b3304..466ce9ace127 100644 --- a/trunk/arch/powerpc/sysdev/uic.c +++ b/trunk/arch/powerpc/sysdev/uic.c @@ -57,7 +57,7 @@ struct uic { static void uic_unmask_irq(unsigned int virq) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); struct uic *uic = get_irq_chip_data(virq); unsigned int src = uic_irq_to_hw(virq); unsigned long flags; @@ -101,7 +101,7 @@ static void uic_ack_irq(unsigned int virq) static void uic_mask_ack_irq(unsigned int virq) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); struct uic *uic = get_irq_chip_data(virq); unsigned int src = uic_irq_to_hw(virq); unsigned long flags; @@ -129,7 +129,7 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) { struct uic *uic = get_irq_chip_data(virq); unsigned int src = uic_irq_to_hw(virq); - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); unsigned long flags; int trigger, polarity; u32 tr, pr, mask; @@ -177,7 +177,7 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) } static struct irq_chip uic_irq_chip = { - .name = " UIC ", + .typename = " UIC ", .unmask = uic_unmask_irq, .mask = uic_mask_irq, .mask_ack = uic_mask_ack_irq, @@ -202,7 +202,7 @@ static int uic_host_map(struct irq_host *h, unsigned int virq, } static int uic_host_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { diff --git a/trunk/arch/powerpc/sysdev/xilinx_intc.c b/trunk/arch/powerpc/sysdev/xilinx_intc.c index 1e0ccfaf403e..40edad520770 100644 --- a/trunk/arch/powerpc/sysdev/xilinx_intc.c +++ b/trunk/arch/powerpc/sysdev/xilinx_intc.c @@ -79,7 +79,7 @@ static void xilinx_intc_mask(unsigned int virq) static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type) { - struct irq_desc *desc = irq_to_desc(virq); + struct irq_desc *desc = get_irq_desc(virq); desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; @@ -106,7 +106,7 @@ static void xilinx_intc_level_unmask(unsigned int virq) } static struct irq_chip xilinx_intc_level_irqchip = { - .name = "Xilinx Level INTC", + .typename = "Xilinx Level INTC", .mask = xilinx_intc_mask, .mask_ack = xilinx_intc_mask, .unmask = xilinx_intc_level_unmask, @@ -133,7 +133,7 @@ static void xilinx_intc_edge_ack(unsigned int virq) } static struct irq_chip xilinx_intc_edge_irqchip = { - .name = "Xilinx Edge INTC", + .typename = "Xilinx Edge INTC", .mask = xilinx_intc_mask, .unmask = xilinx_intc_edge_unmask, .ack = xilinx_intc_edge_ack, @@ -148,7 +148,7 @@ static struct irq_chip xilinx_intc_edge_irqchip = { * xilinx_intc_xlate - translate virq# from device tree interrupts property */ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct, - const u32 *intspec, unsigned int intsize, + u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_flags) { diff --git a/trunk/arch/powerpc/xmon/xmon.c b/trunk/arch/powerpc/xmon/xmon.c index 4e6152c13764..bdbe96c8a7e4 100644 --- a/trunk/arch/powerpc/xmon/xmon.c +++ b/trunk/arch/powerpc/xmon/xmon.c @@ -1641,8 +1641,7 @@ static void super_regs(void) ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1); printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n", ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4); - printf(" Saved Gpr5=%.16lx \n", - ptrLpPaca->gpr5_dword.saved_gpr5); + printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5); } #endif diff --git a/trunk/drivers/ata/Kconfig b/trunk/drivers/ata/Kconfig index 85844d053846..676f08b004b3 100644 --- a/trunk/drivers/ata/Kconfig +++ b/trunk/drivers/ata/Kconfig @@ -790,15 +790,5 @@ config PATA_BF54X If unsure, say N. -config PATA_MACIO - tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE" - depends on PPC_PMAC - help - Most IDE capable PowerMacs have IDE busses driven by a variant - of this controller which is part of the Apple chipset used on - most PowerMac models. Some models have multiple busses using - different chipsets, though generally, MacIO is one of them. - - endif # ATA_SFF endif # ATA diff --git a/trunk/drivers/ata/Makefile b/trunk/drivers/ata/Makefile index fc936d4471d6..d909435e9d81 100644 --- a/trunk/drivers/ata/Makefile +++ b/trunk/drivers/ata/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o obj-$(CONFIG_PDC_ADMA) += pdc_adma.o obj-$(CONFIG_SATA_FSL) += sata_fsl.o -obj-$(CONFIG_PATA_MACIO) += pata_macio.o obj-$(CONFIG_PATA_ALI) += pata_ali.o obj-$(CONFIG_PATA_AMD) += pata_amd.o diff --git a/trunk/drivers/ata/pata_macio.c b/trunk/drivers/ata/pata_macio.c deleted file mode 100644 index 4cc7bbd10ec2..000000000000 --- a/trunk/drivers/ata/pata_macio.c +++ /dev/null @@ -1,1427 +0,0 @@ -/* - * Libata based driver for Apple "macio" family of PATA controllers - * - * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp - * - * - * Some bits and pieces from drivers/ide/ppc/pmac.c - * - */ - -#undef DEBUG -#undef DEBUG_DMA - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#ifdef DEBUG_DMA -#define dev_dbgdma(dev, format, arg...) \ - dev_printk(KERN_DEBUG , dev , format , ## arg) -#else -#define dev_dbgdma(dev, format, arg...) \ - ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; }) -#endif - -#define DRV_NAME "pata_macio" -#define DRV_VERSION "0.9" - -/* Models of macio ATA controller */ -enum { - controller_ohare, /* OHare based */ - controller_heathrow, /* Heathrow/Paddington */ - controller_kl_ata3, /* KeyLargo ATA-3 */ - controller_kl_ata4, /* KeyLargo ATA-4 */ - controller_un_ata6, /* UniNorth2 ATA-6 */ - controller_k2_ata6, /* K2 ATA-6 */ - controller_sh_ata6, /* Shasta ATA-6 */ -}; - -static const char* macio_ata_names[] = { - "OHare ATA", /* OHare based */ - "Heathrow ATA", /* Heathrow/Paddington */ - "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ - "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ - "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ - "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ - "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ -}; - -/* - * Extra registers, both 32-bit little-endian - */ -#define IDE_TIMING_CONFIG 0x200 -#define IDE_INTERRUPT 0x300 - -/* Kauai (U2) ATA has different register setup */ -#define IDE_KAUAI_PIO_CONFIG 0x200 -#define IDE_KAUAI_ULTRA_CONFIG 0x210 -#define IDE_KAUAI_POLL_CONFIG 0x220 - -/* - * Timing configuration register definitions - */ - -/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ -#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) -#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) -#define IDE_SYSCLK_NS 30 /* 33Mhz cell */ -#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ - -/* 133Mhz cell, found in shasta. - * See comments about 100 Mhz Uninorth 2... - * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just - * weird and I don't now why .. at this stage - */ -#define TR_133_PIOREG_PIO_MASK 0xff000fff -#define TR_133_PIOREG_MDMA_MASK 0x00fff800 -#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff -#define TR_133_UDMAREG_UDMA_EN 0x00000001 - -/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device - * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is - * controlled like gem or fw. It appears to be an evolution of keylargo - * ATA4 with a timing register extended to 2x32bits registers (one - * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel. - * It has it's own local feature control register as well. - * - * After scratching my mind over the timing values, at least for PIO - * and MDMA, I think I've figured the format of the timing register, - * though I use pre-calculated tables for UDMA as usual... - */ -#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */ -#define TR_100_PIO_ADDRSETUP_SHIFT 24 -#define TR_100_MDMA_MASK 0x00fff000 -#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000 -#define TR_100_MDMA_RECOVERY_SHIFT 18 -#define TR_100_MDMA_ACCESS_MASK 0x0003f000 -#define TR_100_MDMA_ACCESS_SHIFT 12 -#define TR_100_PIO_MASK 0xff000fff -#define TR_100_PIO_RECOVERY_MASK 0x00000fc0 -#define TR_100_PIO_RECOVERY_SHIFT 6 -#define TR_100_PIO_ACCESS_MASK 0x0000003f -#define TR_100_PIO_ACCESS_SHIFT 0 - -#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff -#define TR_100_UDMAREG_UDMA_EN 0x00000001 - - -/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on - * 40 connector cable and to 4 on 80 connector one. - * Clock unit is 15ns (66Mhz) - * - * 3 Values can be programmed: - * - Write data setup, which appears to match the cycle time. They - * also call it DIOW setup. - * - Ready to pause time (from spec) - * - Address setup. That one is weird. I don't see where exactly - * it fits in UDMA cycles, I got it's name from an obscure piece - * of commented out code in Darwin. They leave it to 0, we do as - * well, despite a comment that would lead to think it has a - * min value of 45ns. - * Apple also add 60ns to the write data setup (or cycle time ?) on - * reads. - */ -#define TR_66_UDMA_MASK 0xfff00000 -#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ -#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */ -#define TR_66_PIO_ADDRSETUP_SHIFT 29 -#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ -#define TR_66_UDMA_RDY2PAUS_SHIFT 25 -#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ -#define TR_66_UDMA_WRDATASETUP_SHIFT 21 -#define TR_66_MDMA_MASK 0x000ffc00 -#define TR_66_MDMA_RECOVERY_MASK 0x000f8000 -#define TR_66_MDMA_RECOVERY_SHIFT 15 -#define TR_66_MDMA_ACCESS_MASK 0x00007c00 -#define TR_66_MDMA_ACCESS_SHIFT 10 -#define TR_66_PIO_MASK 0xe00003ff -#define TR_66_PIO_RECOVERY_MASK 0x000003e0 -#define TR_66_PIO_RECOVERY_SHIFT 5 -#define TR_66_PIO_ACCESS_MASK 0x0000001f -#define TR_66_PIO_ACCESS_SHIFT 0 - -/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo - * Can do pio & mdma modes, clock unit is 30ns (33Mhz) - * - * The access time and recovery time can be programmed. Some older - * Darwin code base limit OHare to 150ns cycle time. I decided to do - * the same here fore safety against broken old hardware ;) - * The HalfTick bit, when set, adds half a clock (15ns) to the access - * time and removes one from recovery. It's not supported on KeyLargo - * implementation afaik. The E bit appears to be set for PIO mode 0 and - * is used to reach long timings used in this mode. - */ -#define TR_33_MDMA_MASK 0x003ff800 -#define TR_33_MDMA_RECOVERY_MASK 0x001f0000 -#define TR_33_MDMA_RECOVERY_SHIFT 16 -#define TR_33_MDMA_ACCESS_MASK 0x0000f800 -#define TR_33_MDMA_ACCESS_SHIFT 11 -#define TR_33_MDMA_HALFTICK 0x00200000 -#define TR_33_PIO_MASK 0x000007ff -#define TR_33_PIO_E 0x00000400 -#define TR_33_PIO_RECOVERY_MASK 0x000003e0 -#define TR_33_PIO_RECOVERY_SHIFT 5 -#define TR_33_PIO_ACCESS_MASK 0x0000001f -#define TR_33_PIO_ACCESS_SHIFT 0 - -/* - * Interrupt register definitions. Only present on newer cells - * (Keylargo and later afaik) so we don't use it. - */ -#define IDE_INTR_DMA 0x80000000 -#define IDE_INTR_DEVICE 0x40000000 - -/* - * FCR Register on Kauai. Not sure what bit 0x4 is ... - */ -#define KAUAI_FCR_UATA_MAGIC 0x00000004 -#define KAUAI_FCR_UATA_RESET_N 0x00000002 -#define KAUAI_FCR_UATA_ENABLE 0x00000001 - - -/* Allow up to 256 DBDMA commands per xfer */ -#define MAX_DCMDS 256 - -/* Don't let a DMA segment go all the way to 64K */ -#define MAX_DBDMA_SEG 0xff00 - - -/* - * Wait 1s for disk to answer on IDE bus after a hard reset - * of the device (via GPIO/FCR). - * - * Some devices seem to "pollute" the bus even after dropping - * the BSY bit (typically some combo drives slave on the UDMA - * bus) after a hard reset. Since we hard reset all drives on - * KeyLargo ATA66, we have to keep that delay around. I may end - * up not hard resetting anymore on these and keep the delay only - * for older interfaces instead (we have to reset when coming - * from MacOS...) --BenH. - */ -#define IDE_WAKEUP_DELAY_MS 1000 - -struct pata_macio_timing; - -struct pata_macio_priv { - int kind; - int aapl_bus_id; - int mediabay : 1; - struct device_node *node; - struct macio_dev *mdev; - struct pci_dev *pdev; - struct device *dev; - int irq; - u32 treg[2][2]; - void __iomem *tfregs; - void __iomem *kauai_fcr; - struct dbdma_cmd * dma_table_cpu; - dma_addr_t dma_table_dma; - struct ata_host *host; - const struct pata_macio_timing *timings; -}; - -/* Previous variants of this driver used to calculate timings - * for various variants of the chip and use tables for others. - * - * Not only was this confusing, but in addition, it isn't clear - * whether our calculation code was correct. It didn't entirely - * match the darwin code and whatever documentation I could find - * on these cells - * - * I decided to entirely rely on a table instead for this version - * of the driver. Also, because I don't really care about derated - * modes and really old HW other than making it work, I'm not going - * to calculate / snoop timing values for something else than the - * standard modes. - */ -struct pata_macio_timing { - int mode; - u32 reg1; /* Bits to set in first timing reg */ - u32 reg2; /* Bits to set in second timing reg */ -}; - -static const struct pata_macio_timing pata_macio_ohare_timings[] = { - { XFER_PIO_0, 0x00000526, 0, }, - { XFER_PIO_1, 0x00000085, 0, }, - { XFER_PIO_2, 0x00000025, 0, }, - { XFER_PIO_3, 0x00000025, 0, }, - { XFER_PIO_4, 0x00000025, 0, }, - { XFER_MW_DMA_0, 0x00074000, 0, }, - { XFER_MW_DMA_1, 0x00221000, 0, }, - { XFER_MW_DMA_2, 0x00211000, 0, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing pata_macio_heathrow_timings[] = { - { XFER_PIO_0, 0x00000526, 0, }, - { XFER_PIO_1, 0x00000085, 0, }, - { XFER_PIO_2, 0x00000025, 0, }, - { XFER_PIO_3, 0x00000025, 0, }, - { XFER_PIO_4, 0x00000025, 0, }, - { XFER_MW_DMA_0, 0x00074000, 0, }, - { XFER_MW_DMA_1, 0x00221000, 0, }, - { XFER_MW_DMA_2, 0x00211000, 0, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing pata_macio_kl33_timings[] = { - { XFER_PIO_0, 0x00000526, 0, }, - { XFER_PIO_1, 0x00000085, 0, }, - { XFER_PIO_2, 0x00000025, 0, }, - { XFER_PIO_3, 0x00000025, 0, }, - { XFER_PIO_4, 0x00000025, 0, }, - { XFER_MW_DMA_0, 0x00084000, 0, }, - { XFER_MW_DMA_1, 0x00021800, 0, }, - { XFER_MW_DMA_2, 0x00011800, 0, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing pata_macio_kl66_timings[] = { - { XFER_PIO_0, 0x0000038c, 0, }, - { XFER_PIO_1, 0x0000020a, 0, }, - { XFER_PIO_2, 0x00000127, 0, }, - { XFER_PIO_3, 0x000000c6, 0, }, - { XFER_PIO_4, 0x00000065, 0, }, - { XFER_MW_DMA_0, 0x00084000, 0, }, - { XFER_MW_DMA_1, 0x00029800, 0, }, - { XFER_MW_DMA_2, 0x00019400, 0, }, - { XFER_UDMA_0, 0x19100000, 0, }, - { XFER_UDMA_1, 0x14d00000, 0, }, - { XFER_UDMA_2, 0x10900000, 0, }, - { XFER_UDMA_3, 0x0c700000, 0, }, - { XFER_UDMA_4, 0x0c500000, 0, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing pata_macio_kauai_timings[] = { - { XFER_PIO_0, 0x08000a92, 0, }, - { XFER_PIO_1, 0x0800060f, 0, }, - { XFER_PIO_2, 0x0800038b, 0, }, - { XFER_PIO_3, 0x05000249, 0, }, - { XFER_PIO_4, 0x04000148, 0, }, - { XFER_MW_DMA_0, 0x00618000, 0, }, - { XFER_MW_DMA_1, 0x00209000, 0, }, - { XFER_MW_DMA_2, 0x00148000, 0, }, - { XFER_UDMA_0, 0, 0x000070c1, }, - { XFER_UDMA_1, 0, 0x00005d81, }, - { XFER_UDMA_2, 0, 0x00004a61, }, - { XFER_UDMA_3, 0, 0x00003a51, }, - { XFER_UDMA_4, 0, 0x00002a31, }, - { XFER_UDMA_5, 0, 0x00002921, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing pata_macio_shasta_timings[] = { - { XFER_PIO_0, 0x0a000c97, 0, }, - { XFER_PIO_1, 0x07000712, 0, }, - { XFER_PIO_2, 0x040003cd, 0, }, - { XFER_PIO_3, 0x0500028b, 0, }, - { XFER_PIO_4, 0x0400010a, 0, }, - { XFER_MW_DMA_0, 0x00820800, 0, }, - { XFER_MW_DMA_1, 0x0028b000, 0, }, - { XFER_MW_DMA_2, 0x001ca000, 0, }, - { XFER_UDMA_0, 0, 0x00035901, }, - { XFER_UDMA_1, 0, 0x000348b1, }, - { XFER_UDMA_2, 0, 0x00033881, }, - { XFER_UDMA_3, 0, 0x00033861, }, - { XFER_UDMA_4, 0, 0x00033841, }, - { XFER_UDMA_5, 0, 0x00033031, }, - { XFER_UDMA_6, 0, 0x00033021, }, - { -1, 0, 0 } -}; - -static const struct pata_macio_timing *pata_macio_find_timing( - struct pata_macio_priv *priv, - int mode) -{ - int i; - - for (i = 0; priv->timings[i].mode > 0; i++) { - if (priv->timings[i].mode == mode) - return &priv->timings[i]; - } - return NULL; -} - - -static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device) -{ - struct pata_macio_priv *priv = ap->private_data; - void __iomem *rbase = ap->ioaddr.cmd_addr; - - if (priv->kind == controller_sh_ata6 || - priv->kind == controller_un_ata6 || - priv->kind == controller_k2_ata6) { - writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG); - writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG); - } else - writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG); -} - -static void pata_macio_dev_select(struct ata_port *ap, unsigned int device) -{ - ata_sff_dev_select(ap, device); - - /* Apply timings */ - pata_macio_apply_timings(ap, device); -} - -static void pata_macio_set_timings(struct ata_port *ap, - struct ata_device *adev) -{ - struct pata_macio_priv *priv = ap->private_data; - const struct pata_macio_timing *t; - - dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n", - adev->devno, - adev->pio_mode, - ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)), - adev->dma_mode, - ata_mode_string(ata_xfer_mode2mask(adev->dma_mode))); - - /* First clear timings */ - priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0; - - /* Now get the PIO timings */ - t = pata_macio_find_timing(priv, adev->pio_mode); - if (t == NULL) { - dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n", - adev->pio_mode); - t = pata_macio_find_timing(priv, XFER_PIO_0); - } - BUG_ON(t == NULL); - - /* PIO timings only ever use the first treg */ - priv->treg[adev->devno][0] |= t->reg1; - - /* Now get DMA timings */ - t = pata_macio_find_timing(priv, adev->dma_mode); - if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { - dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n"); - t = pata_macio_find_timing(priv, XFER_MW_DMA_0); - } - BUG_ON(t == NULL); - - /* DMA timings can use both tregs */ - priv->treg[adev->devno][0] |= t->reg1; - priv->treg[adev->devno][1] |= t->reg2; - - dev_dbg(priv->dev, " -> %08x %08x\n", - priv->treg[adev->devno][0], - priv->treg[adev->devno][1]); - - /* Apply to hardware */ - pata_macio_apply_timings(ap, adev->devno); -} - -/* - * Blast some well known "safe" values to the timing registers at init or - * wakeup from sleep time, before we do real calculation - */ -static void pata_macio_default_timings(struct pata_macio_priv *priv) -{ - unsigned int value, value2 = 0; - - switch(priv->kind) { - case controller_sh_ata6: - value = 0x0a820c97; - value2 = 0x00033031; - break; - case controller_un_ata6: - case controller_k2_ata6: - value = 0x08618a92; - value2 = 0x00002921; - break; - case controller_kl_ata4: - value = 0x0008438c; - break; - case controller_kl_ata3: - value = 0x00084526; - break; - case controller_heathrow: - case controller_ohare: - default: - value = 0x00074526; - break; - } - priv->treg[0][0] = priv->treg[1][0] = value; - priv->treg[0][1] = priv->treg[1][1] = value2; -} - -static int pata_macio_cable_detect(struct ata_port *ap) -{ - struct pata_macio_priv *priv = ap->private_data; - - /* Get cable type from device-tree */ - if (priv->kind == controller_kl_ata4 || - priv->kind == controller_un_ata6 || - priv->kind == controller_k2_ata6 || - priv->kind == controller_sh_ata6) { - const char* cable = of_get_property(priv->node, "cable-type", - NULL); - struct device_node *root = of_find_node_by_path("/"); - const char *model = of_get_property(root, "model", NULL); - - if (cable && !strncmp(cable, "80-", 3)) { - /* Some drives fail to detect 80c cable in PowerBook - * These machine use proprietary short IDE cable - * anyway - */ - if (!strncmp(model, "PowerBook", 9)) - return ATA_CBL_PATA40_SHORT; - else - return ATA_CBL_PATA80; - } - } - - /* G5's seem to have incorrect cable type in device-tree. - * Let's assume they always have a 80 conductor cable, this seem to - * be always the case unless the user mucked around - */ - if (of_device_is_compatible(priv->node, "K2-UATA") || - of_device_is_compatible(priv->node, "shasta-ata")) - return ATA_CBL_PATA80; - - /* Anything else is 40 connectors */ - return ATA_CBL_PATA40; -} - -static void pata_macio_qc_prep(struct ata_queued_cmd *qc) -{ - unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE); - struct ata_port *ap = qc->ap; - struct pata_macio_priv *priv = ap->private_data; - struct scatterlist *sg; - struct dbdma_cmd *table; - unsigned int si, pi; - - dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n", - __func__, qc, qc->flags, write, qc->dev->devno); - - if (!(qc->flags & ATA_QCFLAG_DMAMAP)) - return; - - table = (struct dbdma_cmd *) priv->dma_table_cpu; - - pi = 0; - for_each_sg(qc->sg, sg, qc->n_elem, si) { - u32 addr, sg_len, len; - - /* determine if physical DMA addr spans 64K boundary. - * Note h/w doesn't support 64-bit, so we unconditionally - * truncate dma_addr_t to u32. - */ - addr = (u32) sg_dma_address(sg); - sg_len = sg_dma_len(sg); - - while (sg_len) { - /* table overflow should never happen */ - BUG_ON (pi++ >= MAX_DCMDS); - - len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG; - st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE); - st_le16(&table->req_count, len); - st_le32(&table->phy_addr, addr); - table->cmd_dep = 0; - table->xfer_status = 0; - table->res_count = 0; - addr += len; - sg_len -= len; - ++table; - } - } - - /* Should never happen according to Tejun */ - BUG_ON(!pi); - - /* Convert the last command to an input/output */ - table--; - st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST); - table++; - - /* Add the stop command to the end of the list */ - memset(table, 0, sizeof(struct dbdma_cmd)); - st_le16(&table->command, DBDMA_STOP); - - dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi); -} - - -static void pata_macio_freeze(struct ata_port *ap) -{ - struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; - - if (dma_regs) { - unsigned int timeout = 1000000; - - /* Make sure DMA controller is stopped */ - writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); - while (--timeout && (readl(&dma_regs->status) & RUN)) - udelay(1); - } - - ata_sff_freeze(ap); -} - - -static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc) -{ - struct ata_port *ap = qc->ap; - struct pata_macio_priv *priv = ap->private_data; - struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; - int dev = qc->dev->devno; - - dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); - - /* Make sure DMA commands updates are visible */ - writel(priv->dma_table_dma, &dma_regs->cmdptr); - - /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on - * UDMA reads - */ - if (priv->kind == controller_kl_ata4 && - (priv->treg[dev][0] & TR_66_UDMA_EN)) { - void __iomem *rbase = ap->ioaddr.cmd_addr; - u32 reg = priv->treg[dev][0]; - - if (!(qc->tf.flags & ATA_TFLAG_WRITE)) - reg += 0x00800000; - writel(reg, rbase + IDE_TIMING_CONFIG); - } - - /* issue r/w command */ - ap->ops->sff_exec_command(ap, &qc->tf); -} - -static void pata_macio_bmdma_start(struct ata_queued_cmd *qc) -{ - struct ata_port *ap = qc->ap; - struct pata_macio_priv *priv = ap->private_data; - struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; - - dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); - - writel((RUN << 16) | RUN, &dma_regs->control); - /* Make sure it gets to the controller right now */ - (void)readl(&dma_regs->control); -} - -static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc) -{ - struct ata_port *ap = qc->ap; - struct pata_macio_priv *priv = ap->private_data; - struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; - unsigned int timeout = 1000000; - - dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); - - /* Stop the DMA engine and wait for it to full halt */ - writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control); - while (--timeout && (readl(&dma_regs->status) & RUN)) - udelay(1); -} - -static u8 pata_macio_bmdma_status(struct ata_port *ap) -{ - struct pata_macio_priv *priv = ap->private_data; - struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; - u32 dstat, rstat = ATA_DMA_INTR; - unsigned long timeout = 0; - - dstat = readl(&dma_regs->status); - - dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat); - - /* We have two things to deal with here: - * - * - The dbdma won't stop if the command was started - * but completed with an error without transferring all - * datas. This happens when bad blocks are met during - * a multi-block transfer. - * - * - The dbdma fifo hasn't yet finished flushing to - * to system memory when the disk interrupt occurs. - * - */ - - /* First check for errors */ - if ((dstat & (RUN|DEAD)) != RUN) - rstat |= ATA_DMA_ERR; - - /* If ACTIVE is cleared, the STOP command has been hit and - * the transfer is complete. If not, we have to flush the - * channel. - */ - if ((dstat & ACTIVE) == 0) - return rstat; - - dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__); - - /* If dbdma didn't execute the STOP command yet, the - * active bit is still set. We consider that we aren't - * sharing interrupts (which is hopefully the case with - * those controllers) and so we just try to flush the - * channel for pending data in the fifo - */ - udelay(1); - writel((FLUSH << 16) | FLUSH, &dma_regs->control); - for (;;) { - udelay(1); - dstat = readl(&dma_regs->status); - if ((dstat & FLUSH) == 0) - break; - if (++timeout > 1000) { - dev_warn(priv->dev, "timeout flushing DMA\n"); - rstat |= ATA_DMA_ERR; - break; - } - } - return rstat; -} - -/* port_start is when we allocate the DMA command list */ -static int pata_macio_port_start(struct ata_port *ap) -{ - struct pata_macio_priv *priv = ap->private_data; - - if (ap->ioaddr.bmdma_addr == NULL) - return 0; - - /* Allocate space for the DBDMA commands. - * - * The +2 is +1 for the stop command and +1 to allow for - * aligning the start address to a multiple of 16 bytes. - */ - priv->dma_table_cpu = - dmam_alloc_coherent(priv->dev, - (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), - &priv->dma_table_dma, GFP_KERNEL); - if (priv->dma_table_cpu == NULL) { - dev_err(priv->dev, "Unable to allocate DMA command list\n"); - ap->ioaddr.bmdma_addr = NULL; - } - return 0; -} - -static void pata_macio_irq_clear(struct ata_port *ap) -{ - struct pata_macio_priv *priv = ap->private_data; - - /* Nothing to do here */ - - dev_dbgdma(priv->dev, "%s\n", __func__); -} - -static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume) -{ - dev_dbg(priv->dev, "Enabling & resetting... \n"); - - if (priv->mediabay) - return; - - if (priv->kind == controller_ohare && !resume) { - /* The code below is having trouble on some ohare machines - * (timing related ?). Until I can put my hand on one of these - * units, I keep the old way - */ - ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1); - } else { - int rc; - - /* Reset and enable controller */ - rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET, - priv->node, priv->aapl_bus_id, 1); - ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, - priv->node, priv->aapl_bus_id, 1); - msleep(10); - /* Only bother waiting if there's a reset control */ - if (rc == 0) { - ppc_md.feature_call(PMAC_FTR_IDE_RESET, - priv->node, priv->aapl_bus_id, 0); - msleep(IDE_WAKEUP_DELAY_MS); - } - } - - /* If resuming a PCI device, restore the config space here */ - if (priv->pdev && resume) { - int rc; - - pci_restore_state(priv->pdev); - rc = pcim_enable_device(priv->pdev); - if (rc) - dev_printk(KERN_ERR, &priv->pdev->dev, - "Failed to enable device after resume (%d)\n", rc); - else - pci_set_master(priv->pdev); - } - - /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really - * seem necessary and speeds up the boot process - */ - if (priv->kauai_fcr) - writel(KAUAI_FCR_UATA_MAGIC | - KAUAI_FCR_UATA_RESET_N | - KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr); -} - -/* Hook the standard slave config to fixup some HW related alignment - * restrictions - */ -static int pata_macio_slave_config(struct scsi_device *sdev) -{ - struct ata_port *ap = ata_shost_to_port(sdev->host); - struct pata_macio_priv *priv = ap->private_data; - struct ata_device *dev; - u16 cmd; - int rc; - - /* First call original */ - rc = ata_scsi_slave_config(sdev); - if (rc) - return rc; - - /* This is lifted from sata_nv */ - dev = &ap->link.device[sdev->id]; - - /* OHare has issues with non cache aligned DMA on some chipsets */ - if (priv->kind == controller_ohare) { - blk_queue_update_dma_alignment(sdev->request_queue, 31); - blk_queue_update_dma_pad(sdev->request_queue, 31); - - /* Tell the world about it */ - ata_dev_printk(dev, KERN_INFO, "OHare alignment limits applied\n"); - return 0; - } - - /* We only have issues with ATAPI */ - if (dev->class != ATA_DEV_ATAPI) - return 0; - - /* Shasta and K2 seem to have "issues" with reads ... */ - if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) { - /* Allright these are bad, apply restrictions */ - blk_queue_update_dma_alignment(sdev->request_queue, 15); - blk_queue_update_dma_pad(sdev->request_queue, 15); - - /* We enable MWI and hack cache line size directly here, this - * is specific to this chipset and not normal values, we happen - * to somewhat know what we are doing here (which is basically - * to do the same Apple does and pray they did not get it wrong :-) - */ - BUG_ON(!priv->pdev); - pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08); - pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd); - pci_write_config_word(priv->pdev, PCI_COMMAND, - cmd | PCI_COMMAND_INVALIDATE); - - /* Tell the world about it */ - ata_dev_printk(dev, KERN_INFO, - "K2/Shasta alignment limits applied\n"); - } - - return 0; -} - -#ifdef CONFIG_PM - -static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg) -{ - int rc; - - /* First, core libata suspend to do most of the work */ - rc = ata_host_suspend(priv->host, mesg); - if (rc) - return rc; - - /* Restore to default timings */ - pata_macio_default_timings(priv); - - /* Mask interrupt. Not strictly necessary but old driver did - * it and I'd rather not change that here */ - disable_irq(priv->irq); - - /* The media bay will handle itself just fine */ - if (priv->mediabay) - return 0; - - /* Kauai has bus control FCRs directly here */ - if (priv->kauai_fcr) { - u32 fcr = readl(priv->kauai_fcr); - fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); - writel(fcr, priv->kauai_fcr); - } - - /* For PCI, save state and disable DMA. No need to call - * pci_set_power_state(), the HW doesn't do D states that - * way, the platform code will take care of suspending the - * ASIC properly - */ - if (priv->pdev) { - pci_save_state(priv->pdev); - pci_disable_device(priv->pdev); - } - - /* Disable the bus on older machines and the cell on kauai */ - ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, - priv->aapl_bus_id, 0); - - return 0; -} - -static int pata_macio_do_resume(struct pata_macio_priv *priv) -{ - /* Reset and re-enable the HW */ - pata_macio_reset_hw(priv, 1); - - /* Sanitize drive timings */ - pata_macio_apply_timings(priv->host->ports[0], 0); - - /* We want our IRQ back ! */ - enable_irq(priv->irq); - - /* Let the libata core take it from there */ - ata_host_resume(priv->host); - - return 0; -} - -#endif /* CONFIG_PM */ - -static struct scsi_host_template pata_macio_sht = { - ATA_BASE_SHT(DRV_NAME), - .sg_tablesize = MAX_DCMDS, - /* We may not need that strict one */ - .dma_boundary = ATA_DMA_BOUNDARY, - .slave_configure = pata_macio_slave_config, -}; - -static struct ata_port_operations pata_macio_ops = { - .inherits = &ata_sff_port_ops, - - .freeze = pata_macio_freeze, - .set_piomode = pata_macio_set_timings, - .set_dmamode = pata_macio_set_timings, - .cable_detect = pata_macio_cable_detect, - .sff_dev_select = pata_macio_dev_select, - .qc_prep = pata_macio_qc_prep, - .mode_filter = ata_bmdma_mode_filter, - .bmdma_setup = pata_macio_bmdma_setup, - .bmdma_start = pata_macio_bmdma_start, - .bmdma_stop = pata_macio_bmdma_stop, - .bmdma_status = pata_macio_bmdma_status, - .port_start = pata_macio_port_start, - .sff_irq_clear = pata_macio_irq_clear, -}; - -static void __devinit pata_macio_invariants(struct pata_macio_priv *priv) -{ - const int *bidp; - - /* Identify the type of controller */ - if (of_device_is_compatible(priv->node, "shasta-ata")) { - priv->kind = controller_sh_ata6; - priv->timings = pata_macio_shasta_timings; - } else if (of_device_is_compatible(priv->node, "kauai-ata")) { - priv->kind = controller_un_ata6; - priv->timings = pata_macio_kauai_timings; - } else if (of_device_is_compatible(priv->node, "K2-UATA")) { - priv->kind = controller_k2_ata6; - priv->timings = pata_macio_kauai_timings; - } else if (of_device_is_compatible(priv->node, "keylargo-ata")) { - if (strcmp(priv->node->name, "ata-4") == 0) { - priv->kind = controller_kl_ata4; - priv->timings = pata_macio_kl66_timings; - } else { - priv->kind = controller_kl_ata3; - priv->timings = pata_macio_kl33_timings; - } - } else if (of_device_is_compatible(priv->node, "heathrow-ata")) { - priv->kind = controller_heathrow; - priv->timings = pata_macio_heathrow_timings; - } else { - priv->kind = controller_ohare; - priv->timings = pata_macio_ohare_timings; - } - - /* XXX FIXME --- setup priv->mediabay here */ - - /* Get Apple bus ID (for clock and ASIC control) */ - bidp = of_get_property(priv->node, "AAPL,bus-id", NULL); - priv->aapl_bus_id = bidp ? *bidp : 0; - - /* Fixup missing Apple bus ID in case of media-bay */ - if (priv->mediabay && bidp == 0) - priv->aapl_bus_id = 1; -} - -static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr, - void __iomem * base, - void __iomem * dma) -{ - /* cmd_addr is the base of regs for that port */ - ioaddr->cmd_addr = base; - - /* taskfile registers */ - ioaddr->data_addr = base + (ATA_REG_DATA << 4); - ioaddr->error_addr = base + (ATA_REG_ERR << 4); - ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4); - ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4); - ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4); - ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4); - ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4); - ioaddr->device_addr = base + (ATA_REG_DEVICE << 4); - ioaddr->status_addr = base + (ATA_REG_STATUS << 4); - ioaddr->command_addr = base + (ATA_REG_CMD << 4); - ioaddr->altstatus_addr = base + 0x160; - ioaddr->ctl_addr = base + 0x160; - ioaddr->bmdma_addr = dma; -} - -static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv, - struct ata_port_info *pinfo) -{ - int i = 0; - - pinfo->pio_mask = 0; - pinfo->mwdma_mask = 0; - pinfo->udma_mask = 0; - - while (priv->timings[i].mode > 0) { - unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); - switch(priv->timings[i].mode & 0xf0) { - case 0x00: /* PIO */ - pinfo->pio_mask |= (mask >> 8); - break; - case 0x20: /* MWDMA */ - pinfo->mwdma_mask |= mask; - break; - case 0x40: /* UDMA */ - pinfo->udma_mask |= mask; - break; - } - i++; - } - dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n", - pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask); -} - -static int __devinit pata_macio_common_init(struct pata_macio_priv *priv, - resource_size_t tfregs, - resource_size_t dmaregs, - resource_size_t fcregs, - unsigned long irq) -{ - struct ata_port_info pinfo; - const struct ata_port_info *ppi[] = { &pinfo, NULL }; - void __iomem *dma_regs = NULL; - - /* Fill up privates with various invariants collected from the - * device-tree - */ - pata_macio_invariants(priv); - - /* Make sure we have sane initial timings in the cache */ - pata_macio_default_timings(priv); - - /* Not sure what the real max is but we know it's less than 64K, let's - * use 64K minus 256 - */ - dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG); - - /* Allocate libata host for 1 port */ - memset(&pinfo, 0, sizeof(struct ata_port_info)); - pmac_macio_calc_timing_masks(priv, &pinfo); - pinfo.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | - ATA_FLAG_NO_LEGACY; - pinfo.port_ops = &pata_macio_ops; - pinfo.private_data = priv; - - priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1); - if (priv->host == NULL) { - dev_err(priv->dev, "Failed to allocate ATA port structure\n"); - return -ENOMEM; - } - - /* Setup the private data in host too */ - priv->host->private_data = priv; - - /* Map base registers */ - priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100); - if (priv->tfregs == NULL) { - dev_err(priv->dev, "Failed to map ATA ports\n"); - return -ENOMEM; - } - priv->host->iomap = &priv->tfregs; - - /* Map DMA regs */ - if (dmaregs != 0) { - dma_regs = devm_ioremap(priv->dev, dmaregs, - sizeof(struct dbdma_regs)); - if (dma_regs == NULL) - dev_warn(priv->dev, "Failed to map ATA DMA registers\n"); - } - - /* If chip has local feature control, map those regs too */ - if (fcregs != 0) { - priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4); - if (priv->kauai_fcr == NULL) { - dev_err(priv->dev, "Failed to map ATA FCR register\n"); - return -ENOMEM; - } - } - - /* Setup port data structure */ - pata_macio_setup_ios(&priv->host->ports[0]->ioaddr, - priv->tfregs, dma_regs); - priv->host->ports[0]->private_data = priv; - - /* hard-reset the controller */ - pata_macio_reset_hw(priv, 0); - pata_macio_apply_timings(priv->host->ports[0], 0); - - /* Enable bus master if necessary */ - if (priv->pdev && dma_regs) - pci_set_master(priv->pdev); - - dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n", - macio_ata_names[priv->kind], priv->aapl_bus_id); - - /* Start it up */ - priv->irq = irq; - return ata_host_activate(priv->host, irq, ata_sff_interrupt, 0, - &pata_macio_sht); -} - -static int __devinit pata_macio_attach(struct macio_dev *mdev, - const struct of_device_id *match) -{ - struct pata_macio_priv *priv; - resource_size_t tfregs, dmaregs = 0; - unsigned long irq; - int rc; - - /* Check for broken device-trees */ - if (macio_resource_count(mdev) == 0) { - dev_err(&mdev->ofdev.dev, - "No addresses for controller\n"); - return -ENXIO; - } - - /* Enable managed resources */ - macio_enable_devres(mdev); - - /* Allocate and init private data structure */ - priv = devm_kzalloc(&mdev->ofdev.dev, - sizeof(struct pata_macio_priv), GFP_KERNEL); - if (priv == NULL) { - dev_err(&mdev->ofdev.dev, - "Failed to allocate private memory\n"); - return -ENOMEM; - } - priv->node = of_node_get(mdev->ofdev.node); - priv->mdev = mdev; - priv->dev = &mdev->ofdev.dev; - - /* Request memory resource for taskfile registers */ - if (macio_request_resource(mdev, 0, "pata-macio")) { - dev_err(&mdev->ofdev.dev, - "Cannot obtain taskfile resource\n"); - return -EBUSY; - } - tfregs = macio_resource_start(mdev, 0); - - /* Request resources for DMA registers if any */ - if (macio_resource_count(mdev) >= 2) { - if (macio_request_resource(mdev, 1, "pata-macio-dma")) - dev_err(&mdev->ofdev.dev, - "Cannot obtain DMA resource\n"); - else - dmaregs = macio_resource_start(mdev, 1); - } - - /* - * Fixup missing IRQ for some old implementations with broken - * device-trees. - * - * This is a bit bogus, it should be fixed in the device-tree itself, - * via the existing macio fixups, based on the type of interrupt - * controller in the machine. However, I have no test HW for this case, - * and this trick works well enough on those old machines... - */ - if (macio_irq_count(mdev) == 0) { - dev_warn(&mdev->ofdev.dev, - "No interrupts for controller, using 13\n"); - irq = irq_create_mapping(NULL, 13); - } else - irq = macio_irq(mdev, 0); - - /* Prevvent media bay callbacks until fully registered */ - lock_media_bay(priv->mdev->media_bay); - - /* Get register addresses and call common initialization */ - rc = pata_macio_common_init(priv, - tfregs, /* Taskfile regs */ - dmaregs, /* DBDMA regs */ - 0, /* Feature control */ - irq); - unlock_media_bay(priv->mdev->media_bay); - - return rc; -} - -static int __devexit pata_macio_detach(struct macio_dev *mdev) -{ - struct ata_host *host = macio_get_drvdata(mdev); - struct pata_macio_priv *priv = host->private_data; - - lock_media_bay(priv->mdev->media_bay); - - /* Make sure the mediabay callback doesn't try to access - * dead stuff - */ - priv->host->private_data = NULL; - - ata_host_detach(host); - - unlock_media_bay(priv->mdev->media_bay); - - return 0; -} - -#ifdef CONFIG_PM - -static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) -{ - struct ata_host *host = macio_get_drvdata(mdev); - - return pata_macio_do_suspend(host->private_data, mesg); -} - -static int pata_macio_resume(struct macio_dev *mdev) -{ - struct ata_host *host = macio_get_drvdata(mdev); - - return pata_macio_do_resume(host->private_data); -} - -#endif /* CONFIG_PM */ - -#ifdef CONFIG_PMAC_MEDIABAY -static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state) -{ - struct ata_host *host = macio_get_drvdata(mdev); - struct ata_port *ap; - struct ata_eh_info *ehi; - struct ata_device *dev; - unsigned long flags; - - if (!host || !host->private_data) - return; - ap = host->ports[0]; - spin_lock_irqsave(ap->lock, flags); - ehi = &ap->link.eh_info; - if (mb_state == MB_CD) { - ata_ehi_push_desc(ehi, "mediabay plug"); - ata_ehi_hotplugged(ehi); - ata_port_freeze(ap); - } else { - ata_ehi_push_desc(ehi, "mediabay unplug"); - ata_for_each_dev(dev, &ap->link, ALL) - dev->flags |= ATA_DFLAG_DETACH; - ata_port_abort(ap); - } - spin_unlock_irqrestore(ap->lock, flags); - -} -#endif /* CONFIG_PMAC_MEDIABAY */ - - -static int __devinit pata_macio_pci_attach(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - struct pata_macio_priv *priv; - struct device_node *np; - resource_size_t rbase; - - /* We cannot use a MacIO controller without its OF device node */ - np = pci_device_to_OF_node(pdev); - if (np == NULL) { - dev_err(&pdev->dev, - "Cannot find OF device node for controller\n"); - return -ENODEV; - } - - /* Check that it can be enabled */ - if (pcim_enable_device(pdev)) { - dev_err(&pdev->dev, - "Cannot enable controller PCI device\n"); - return -ENXIO; - } - - /* Allocate and init private data structure */ - priv = devm_kzalloc(&pdev->dev, - sizeof(struct pata_macio_priv), GFP_KERNEL); - if (priv == NULL) { - dev_err(&pdev->dev, - "Failed to allocate private memory\n"); - return -ENOMEM; - } - priv->node = of_node_get(np); - priv->pdev = pdev; - priv->dev = &pdev->dev; - - /* Get MMIO regions */ - if (pci_request_regions(pdev, "pata-macio")) { - dev_err(&pdev->dev, - "Cannot obtain PCI resources\n"); - return -EBUSY; - } - - /* Get register addresses and call common initialization */ - rbase = pci_resource_start(pdev, 0); - if (pata_macio_common_init(priv, - rbase + 0x2000, /* Taskfile regs */ - rbase + 0x1000, /* DBDMA regs */ - rbase, /* Feature control */ - pdev->irq)) - return -ENXIO; - - return 0; -} - -static void __devexit pata_macio_pci_detach(struct pci_dev *pdev) -{ - struct ata_host *host = dev_get_drvdata(&pdev->dev); - - ata_host_detach(host); -} - -#ifdef CONFIG_PM - -static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) -{ - struct ata_host *host = dev_get_drvdata(&pdev->dev); - - return pata_macio_do_suspend(host->private_data, mesg); -} - -static int pata_macio_pci_resume(struct pci_dev *pdev) -{ - struct ata_host *host = dev_get_drvdata(&pdev->dev); - - return pata_macio_do_resume(host->private_data); -} - -#endif /* CONFIG_PM */ - -static struct of_device_id pata_macio_match[] = -{ - { - .name = "IDE", - }, - { - .name = "ATA", - }, - { - .type = "ide", - }, - { - .type = "ata", - }, - {}, -}; - -static struct macio_driver pata_macio_driver = -{ - .name = "pata-macio", - .match_table = pata_macio_match, - .probe = pata_macio_attach, - .remove = pata_macio_detach, -#ifdef CONFIG_PM - .suspend = pata_macio_suspend, - .resume = pata_macio_resume, -#endif -#ifdef CONFIG_PMAC_MEDIABAY - .mediabay_event = pata_macio_mb_event, -#endif - .driver = { - .owner = THIS_MODULE, - }, -}; - -static const struct pci_device_id pata_macio_pci_match[] = { - { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, - { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, - { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, - { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, - { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, - {}, -}; - -static struct pci_driver pata_macio_pci_driver = { - .name = "pata-pci-macio", - .id_table = pata_macio_pci_match, - .probe = pata_macio_pci_attach, - .remove = pata_macio_pci_detach, -#ifdef CONFIG_PM - .suspend = pata_macio_pci_suspend, - .resume = pata_macio_pci_resume, -#endif - .driver = { - .owner = THIS_MODULE, - }, -}; -MODULE_DEVICE_TABLE(pci, pata_macio_pci_match); - - -static int __init pata_macio_init(void) -{ - int rc; - - if (!machine_is(powermac)) - return -ENODEV; - - rc = pci_register_driver(&pata_macio_pci_driver); - if (rc) - return rc; - rc = macio_register_driver(&pata_macio_driver); - if (rc) { - pci_unregister_driver(&pata_macio_pci_driver); - return rc; - } - return 0; -} - -static void __exit pata_macio_exit(void) -{ - macio_unregister_driver(&pata_macio_driver); - pci_unregister_driver(&pata_macio_pci_driver); -} - -module_init(pata_macio_init); -module_exit(pata_macio_exit); - -MODULE_AUTHOR("Benjamin Herrenschmidt"); -MODULE_DESCRIPTION("Apple MacIO PATA driver"); -MODULE_LICENSE("GPL"); -MODULE_VERSION(DRV_VERSION); diff --git a/trunk/drivers/base/cpu.c b/trunk/drivers/base/cpu.c index 27fd775375b0..e62a4ccea54d 100644 --- a/trunk/drivers/base/cpu.c +++ b/trunk/drivers/base/cpu.c @@ -35,7 +35,6 @@ static ssize_t __ref store_online(struct sys_device *dev, struct sysdev_attribut struct cpu *cpu = container_of(dev, struct cpu, sysdev); ssize_t ret; - cpu_hotplug_driver_lock(); switch (buf[0]) { case '0': ret = cpu_down(cpu->sysdev.id); @@ -50,7 +49,6 @@ static ssize_t __ref store_online(struct sys_device *dev, struct sysdev_attribut default: ret = -EINVAL; } - cpu_hotplug_driver_unlock(); if (ret >= 0) ret = count; @@ -74,38 +72,6 @@ void unregister_cpu(struct cpu *cpu) per_cpu(cpu_sys_devices, logical_cpu) = NULL; return; } - -#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE -static ssize_t cpu_probe_store(struct class *class, const char *buf, - size_t count) -{ - return arch_cpu_probe(buf, count); -} - -static ssize_t cpu_release_store(struct class *class, const char *buf, - size_t count) -{ - return arch_cpu_release(buf, count); -} - -static CLASS_ATTR(probe, S_IWUSR, NULL, cpu_probe_store); -static CLASS_ATTR(release, S_IWUSR, NULL, cpu_release_store); - -int __init cpu_probe_release_init(void) -{ - int rc; - - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &class_attr_probe.attr); - if (!rc) - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &class_attr_release.attr); - - return rc; -} -device_initcall(cpu_probe_release_init); -#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ - #else /* ... !CONFIG_HOTPLUG_CPU */ static inline void register_cpu_control(struct cpu *cpu) { diff --git a/trunk/drivers/block/swim3.c b/trunk/drivers/block/swim3.c index 59ca2b77b574..6380ad8d91bd 100644 --- a/trunk/drivers/block/swim3.c +++ b/trunk/drivers/block/swim3.c @@ -200,7 +200,7 @@ struct floppy_state { int ejected; wait_queue_head_t wait; int wanted; - struct macio_dev *mdev; + struct device_node* media_bay; /* NULL when not in bay */ char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)]; }; @@ -303,13 +303,14 @@ static int swim3_readbit(struct floppy_state *fs, int bit) static void do_fd_request(struct request_queue * q) { int i; - - for(i=0; imdev->media_bay && - check_media_bay(fs->mdev->media_bay) != MB_FD) + for(i=0;imdev->media_bay && - check_media_bay(fs->mdev->media_bay) != MB_FD) +#ifdef CONFIG_PMAC_MEDIABAY + if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD)) return -ENXIO; +#endif switch (cmd) { case FDEJECT: @@ -874,9 +876,10 @@ static int floppy_open(struct block_device *bdev, fmode_t mode) int n, err = 0; if (fs->ref_count == 0) { - if (fs->mdev->media_bay && - check_media_bay(fs->mdev->media_bay) != MB_FD) +#ifdef CONFIG_PMAC_MEDIABAY + if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD)) return -ENXIO; +#endif out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2); out_8(&sw->control_bic, 0xff); out_8(&sw->mode, 0x95); @@ -960,9 +963,10 @@ static int floppy_revalidate(struct gendisk *disk) struct swim3 __iomem *sw; int ret, n; - if (fs->mdev->media_bay && - check_media_bay(fs->mdev->media_bay) != MB_FD) +#ifdef CONFIG_PMAC_MEDIABAY + if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD)) return -ENXIO; +#endif sw = fs->swim3; grab_drive(fs, revalidating, 0); @@ -1005,6 +1009,7 @@ static const struct block_device_operations floppy_fops = { static int swim3_add_device(struct macio_dev *mdev, int index) { struct device_node *swim = mdev->ofdev.node; + struct device_node *mediabay; struct floppy_state *fs = &floppy_states[index]; int rc = -EBUSY; @@ -1031,7 +1036,9 @@ static int swim3_add_device(struct macio_dev *mdev, int index) } dev_set_drvdata(&mdev->ofdev.dev, fs); - if (mdev->media_bay == NULL) + mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ? + swim->parent : NULL; + if (mediabay == NULL) pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1); memset(fs, 0, sizeof(*fs)); @@ -1061,7 +1068,7 @@ static int swim3_add_device(struct macio_dev *mdev, int index) fs->secpercyl = 36; fs->secpertrack = 18; fs->total_secs = 2880; - fs->mdev = mdev; + fs->media_bay = mediabay; init_waitqueue_head(&fs->wait); fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space); @@ -1086,7 +1093,7 @@ static int swim3_add_device(struct macio_dev *mdev, int index) init_timer(&fs->timeout); printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count, - mdev->media_bay ? "in media bay" : ""); + mediabay ? "in media bay" : ""); return 0; diff --git a/trunk/drivers/char/agp/uninorth-agp.c b/trunk/drivers/char/agp/uninorth-agp.c index d89da4ac061f..703959eba45a 100644 --- a/trunk/drivers/char/agp/uninorth-agp.c +++ b/trunk/drivers/char/agp/uninorth-agp.c @@ -144,13 +144,16 @@ static int uninorth_configure(void) return 0; } -static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) +static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, + int type) { - int i, num_entries; + int i, j, num_entries; void *temp; - u32 *gp; int mask_type; + temp = agp_bridge->current_size; + num_entries = A_SIZE_32(temp)->num_entries; + if (type != mem->type) return -EINVAL; @@ -160,12 +163,49 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int ty return -EINVAL; } - if (mem->page_count == 0) - return 0; + if ((pg_start + mem->page_count) > num_entries) + return -EINVAL; + + j = pg_start; + + while (j < (pg_start + mem->page_count)) { + if (agp_bridge->gatt_table[j]) + return -EBUSY; + j++; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { + agp_bridge->gatt_table[j] = + cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 0x1UL); + flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), + (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); + } + (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); + mb(); + + uninorth_tlbflush(mem); + return 0; +} + +static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type) +{ + int i, num_entries; + void *temp; + u32 *gp; + int mask_type; temp = agp_bridge->current_size; num_entries = A_SIZE_32(temp)->num_entries; + if (type != mem->type) + return -EINVAL; + + mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); + if (mask_type != 0) { + /* We know nothing of memory types */ + return -EINVAL; + } + if ((pg_start + mem->page_count) > num_entries) return -EINVAL; @@ -173,18 +213,14 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int ty for (i = 0; i < mem->page_count; ++i) { if (gp[i]) { dev_info(&agp_bridge->dev->dev, - "uninorth_insert_memory: entry 0x%x occupied (%x)\n", + "u3_insert_memory: entry 0x%x occupied (%x)\n", i, gp[i]); return -EBUSY; } } for (i = 0; i < mem->page_count; i++) { - if (is_u3) - gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; - else - gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | - 0x1UL); + gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); } @@ -194,23 +230,14 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int ty return 0; } -int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) +int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type) { size_t i; u32 *gp; - int mask_type; - - if (type != mem->type) - return -EINVAL; - mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); - if (mask_type != 0) { + if (type != 0 || mem->type != 0) /* We know nothing of memory types */ return -EINVAL; - } - - if (mem->page_count == 0) - return 0; gp = (u32 *) &agp_bridge->gatt_table[pg_start]; for (i = 0; i < mem->page_count; ++i) @@ -509,7 +536,7 @@ const struct agp_bridge_driver uninorth_agp_driver = { .create_gatt_table = uninorth_create_gatt_table, .free_gatt_table = uninorth_free_gatt_table, .insert_memory = uninorth_insert_memory, - .remove_memory = uninorth_remove_memory, + .remove_memory = agp_generic_remove_memory, .alloc_by_type = agp_generic_alloc_by_type, .free_by_type = agp_generic_free_by_type, .agp_alloc_page = agp_generic_alloc_page, @@ -535,8 +562,8 @@ const struct agp_bridge_driver u3_agp_driver = { .agp_enable = uninorth_agp_enable, .create_gatt_table = uninorth_create_gatt_table, .free_gatt_table = uninorth_free_gatt_table, - .insert_memory = uninorth_insert_memory, - .remove_memory = uninorth_remove_memory, + .insert_memory = u3_insert_memory, + .remove_memory = u3_remove_memory, .alloc_by_type = agp_generic_alloc_by_type, .free_by_type = agp_generic_free_by_type, .agp_alloc_page = agp_generic_alloc_page, diff --git a/trunk/drivers/char/hvc_console.c b/trunk/drivers/char/hvc_console.c index 416d3423150d..a632f25f144a 100644 --- a/trunk/drivers/char/hvc_console.c +++ b/trunk/drivers/char/hvc_console.c @@ -832,7 +832,6 @@ int hvc_remove(struct hvc_struct *hp) tty_hangup(tty); return 0; } -EXPORT_SYMBOL_GPL(hvc_remove); /* Driver initialization: called as soon as someone uses hvc_alloc(). */ static int hvc_init(void) diff --git a/trunk/drivers/char/tty_io.c b/trunk/drivers/char/tty_io.c index f15df40bc318..684f0e0b175e 100644 --- a/trunk/drivers/char/tty_io.c +++ b/trunk/drivers/char/tty_io.c @@ -516,6 +516,7 @@ static void do_tty_hangup(struct work_struct *work) /* inuse_filps is protected by the single kernel lock */ lock_kernel(); check_tty_count(tty, "do_tty_hangup"); + unlock_kernel(); file_list_lock(); /* This breaks for file handles being sent over AF_UNIX sockets ? */ @@ -530,6 +531,7 @@ static void do_tty_hangup(struct work_struct *work) } file_list_unlock(); + lock_kernel(); tty_ldisc_hangup(tty); read_lock(&tasklist_lock); diff --git a/trunk/drivers/ide/pmac.c b/trunk/drivers/ide/pmac.c index 7a4e788cab2f..97642a7a79c4 100644 --- a/trunk/drivers/ide/pmac.c +++ b/trunk/drivers/ide/pmac.c @@ -43,7 +43,10 @@ #include #include #include + +#ifndef CONFIG_PPC64 #include +#endif #define DRV_NAME "ide-pmac" @@ -56,14 +59,13 @@ typedef struct pmac_ide_hwif { int irq; int kind; int aapl_bus_id; + unsigned mediabay : 1; unsigned broken_dma : 1; unsigned broken_dma_warn : 1; struct device_node* node; struct macio_dev *mdev; u32 timings[4]; volatile u32 __iomem * *kauai_fcr; - ide_hwif_t *hwif; - /* Those fields are duplicating what is in hwif. We currently * can't use the hwif ones because of some assumptions that are * beeing done by the generic code about the kind of dma controller @@ -852,11 +854,6 @@ sanitize_timings(pmac_ide_hwif_t *pmif) pmif->timings[2] = pmif->timings[3] = value2; } -static int on_media_bay(pmac_ide_hwif_t *pmif) -{ - return pmif->mdev && pmif->mdev->media_bay != NULL; -} - /* Suspend call back, should be called after the child devices * have actually been suspended */ @@ -869,7 +866,7 @@ static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif) disable_irq(pmif->irq); /* The media bay will handle itself just fine */ - if (on_media_bay(pmif)) + if (pmif->mediabay) return 0; /* Kauai has bus control FCRs directly here */ @@ -892,7 +889,7 @@ static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif) static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif) { /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */ - if (!on_media_bay(pmif)) { + if (!pmif->mediabay) { ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1); ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1); msleep(10); @@ -953,11 +950,13 @@ static void pmac_ide_init_dev(ide_drive_t *drive) pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); - if (on_media_bay(pmif)) { - if (check_media_bay(pmif->mdev->media_bay) == MB_CD) { + if (pmif->mediabay) { +#ifdef CONFIG_PMAC_MEDIABAY + if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) { drive->dev_flags &= ~IDE_DFLAG_NOPROBE; return; } +#endif drive->dev_flags |= IDE_DFLAG_NOPROBE; } } @@ -1073,23 +1072,26 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, writel(KAUAI_FCR_UATA_MAGIC | KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr); + + pmif->mediabay = 0; /* Make sure we have sane timings */ sanitize_timings(pmif); - /* If we are on a media bay, wait for it to settle and lock it */ - if (pmif->mdev) - lock_media_bay(pmif->mdev->media_bay); - host = ide_host_alloc(&d, hws, 1); - if (host == NULL) { - rc = -ENOMEM; - goto bail; - } - hwif = pmif->hwif = host->ports[0]; + if (host == NULL) + return -ENOMEM; + hwif = host->ports[0]; - if (on_media_bay(pmif)) { - /* Fixup bus ID for media bay */ +#ifndef CONFIG_PPC64 + /* XXX FIXME: Media bay stuff need re-organizing */ + if (np->parent && np->parent->name + && strcasecmp(np->parent->name, "media-bay") == 0) { +#ifdef CONFIG_PMAC_MEDIABAY + media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, + hwif); +#endif /* CONFIG_PMAC_MEDIABAY */ + pmif->mediabay = 1; if (!bidp) pmif->aapl_bus_id = 1; } else if (pmif->kind == controller_ohare) { @@ -1098,7 +1100,9 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, * units, I keep the old way */ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1); - } else { + } else +#endif + { /* This is necessary to enable IDE when net-booting */ ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1); ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1); @@ -1108,21 +1112,17 @@ static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, } printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), " - "bus ID %d%s, irq %d\n", model_name[pmif->kind], - pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id, - on_media_bay(pmif) ? " (mediabay)" : "", hw->irq); + "bus ID %d%s, irq %d\n", model_name[pmif->kind], + pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id, + pmif->mediabay ? " (mediabay)" : "", hw->irq); rc = ide_host_register(host, &d, hws); - if (rc) - pmif->hwif = NULL; - - if (pmif->mdev) - unlock_media_bay(pmif->mdev->media_bay); - - bail: - if (rc && host) + if (rc) { ide_host_free(host); - return rc; + return rc; + } + + return 0; } static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base) @@ -1362,25 +1362,6 @@ pmac_ide_pci_resume(struct pci_dev *pdev) return rc; } -#ifdef CONFIG_PMAC_MEDIABAY -static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state) -{ - pmac_ide_hwif_t *pmif = - (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev); - - switch(mb_state) { - case MB_CD: - if (!pmif->hwif->present) - ide_port_scan(pmif->hwif); - break; - default: - if (pmif->hwif->present) - ide_port_unregister_devices(pmif->hwif); - } -} -#endif /* CONFIG_PMAC_MEDIABAY */ - - static struct of_device_id pmac_ide_macio_match[] = { { @@ -1405,9 +1386,6 @@ static struct macio_driver pmac_ide_macio_driver = .probe = pmac_ide_macio_attach, .suspend = pmac_ide_macio_suspend, .resume = pmac_ide_macio_resume, -#ifdef CONFIG_PMAC_MEDIABAY - .mediabay_event = pmac_ide_macio_mb_event, -#endif }; static const struct pci_device_id pmac_ide_pci_match[] = { diff --git a/trunk/drivers/leds/leds-fsg.c b/trunk/drivers/leds/leds-fsg.c index d11d05be0dee..5f7c9c5c09b1 100644 --- a/trunk/drivers/leds/leds-fsg.c +++ b/trunk/drivers/leds/leds-fsg.c @@ -22,13 +22,6 @@ #include #include -#define FSG_LED_WLAN_BIT 0 -#define FSG_LED_WAN_BIT 1 -#define FSG_LED_SATA_BIT 2 -#define FSG_LED_USB_BIT 4 -#define FSG_LED_RING_BIT 5 -#define FSG_LED_SYNC_BIT 7 - static short __iomem *latch_address; static unsigned short latch_value; diff --git a/trunk/drivers/macintosh/macio_asic.c b/trunk/drivers/macintosh/macio_asic.c index 26a303a1d1ab..588a5b0bc4b5 100644 --- a/trunk/drivers/macintosh/macio_asic.c +++ b/trunk/drivers/macintosh/macio_asic.c @@ -379,11 +379,6 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip, dev->ofdev.dev.parent = parent; dev->ofdev.dev.bus = &macio_bus_type; dev->ofdev.dev.release = macio_release_dev; - dev->ofdev.dev.dma_parms = &dev->dma_parms; - - /* Standard DMA paremeters */ - dma_set_max_seg_size(&dev->ofdev.dev, 65536); - dma_set_seg_boundary(&dev->ofdev.dev, 0xffffffff); #ifdef CONFIG_PCI /* Set the DMA ops to the ones from the PCI device, this could be @@ -543,42 +538,6 @@ void macio_unregister_driver(struct macio_driver *drv) driver_unregister(&drv->driver); } -/* Managed MacIO resources */ -struct macio_devres { - u32 res_mask; -}; - -static void maciom_release(struct device *gendev, void *res) -{ - struct macio_dev *dev = to_macio_device(gendev); - struct macio_devres *dr = res; - int i, max; - - max = min(dev->n_resources, 32); - for (i = 0; i < max; i++) { - if (dr->res_mask & (1 << i)) - macio_release_resource(dev, i); - } -} - -int macio_enable_devres(struct macio_dev *dev) -{ - struct macio_devres *dr; - - dr = devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL); - if (!dr) { - dr = devres_alloc(maciom_release, sizeof(*dr), GFP_KERNEL); - if (!dr) - return -ENOMEM; - } - return devres_get(&dev->ofdev.dev, dr, NULL, NULL) != NULL; -} - -static struct macio_devres * find_macio_dr(struct macio_dev *dev) -{ - return devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL); -} - /** * macio_request_resource - Request an MMIO resource * @dev: pointer to the device holding the resource @@ -596,8 +555,6 @@ static struct macio_devres * find_macio_dr(struct macio_dev *dev) int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name) { - struct macio_devres *dr = find_macio_dr(dev); - if (macio_resource_len(dev, resource_no) == 0) return 0; @@ -605,9 +562,6 @@ int macio_request_resource(struct macio_dev *dev, int resource_no, macio_resource_len(dev, resource_no), name)) goto err_out; - - if (dr && resource_no < 32) - dr->res_mask |= 1 << resource_no; return 0; @@ -628,14 +582,10 @@ int macio_request_resource(struct macio_dev *dev, int resource_no, */ void macio_release_resource(struct macio_dev *dev, int resource_no) { - struct macio_devres *dr = find_macio_dr(dev); - if (macio_resource_len(dev, resource_no) == 0) return; release_mem_region(macio_resource_start(dev, resource_no), macio_resource_len(dev, resource_no)); - if (dr && resource_no < 32) - dr->res_mask &= ~(1 << resource_no); } /** @@ -794,5 +744,3 @@ EXPORT_SYMBOL(macio_request_resource); EXPORT_SYMBOL(macio_release_resource); EXPORT_SYMBOL(macio_request_resources); EXPORT_SYMBOL(macio_release_resources); -EXPORT_SYMBOL(macio_enable_devres); - diff --git a/trunk/drivers/macintosh/mediabay.c b/trunk/drivers/macintosh/mediabay.c index 08002b88f342..029ad8ce8a7e 100644 --- a/trunk/drivers/macintosh/mediabay.c +++ b/trunk/drivers/macintosh/mediabay.c @@ -33,6 +33,15 @@ #include #include + +#define MB_DEBUG + +#ifdef MB_DEBUG +#define MBDBG(fmt, arg...) printk(KERN_INFO fmt , ## arg) +#else +#define MBDBG(fmt, arg...) do { } while (0) +#endif + #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2)) #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r)) @@ -67,14 +76,28 @@ struct media_bay_info { int index; int cached_gpio; int sleeping; - int user_lock; struct mutex lock; +#ifdef CONFIG_BLK_DEV_IDE_PMAC + ide_hwif_t *cd_port; + void __iomem *cd_base; + int cd_irq; + int cd_retry; +#endif +#if defined(CONFIG_BLK_DEV_IDE_PMAC) + int cd_index; +#endif }; #define MAX_BAYS 2 static struct media_bay_info media_bays[MAX_BAYS]; -static int media_bay_count = 0; +int media_bay_count = 0; + +#ifdef CONFIG_BLK_DEV_IDE_PMAC +/* check the busy bit in the media-bay ide interface + (assumes the media-bay contains an ide device) */ +#define MB_IDE_READY(i) ((readb(media_bays[i].cd_base + 0x70) & 0x80) == 0) +#endif /* * Wait that number of ms between each step in normal polling mode @@ -107,10 +130,20 @@ static int media_bay_count = 0; /* * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted - * (or until the device is ready) before calling into the driver + * (or until the device is ready) before waiting for busy bit to disappear */ #define MB_IDE_WAIT 1000 +/* + * Timeout waiting for busy bit of an IDE device to go down + */ +#define MB_IDE_TIMEOUT 5000 + +/* + * Max retries of the full power up/down sequence for an IDE device + */ +#define MAX_CD_RETRIES 3 + /* * States of a media bay */ @@ -120,6 +153,7 @@ enum { mb_enabling_bay, /* enable bits set, waiting MB_RESET_DELAY */ mb_resetting, /* reset bit unset, waiting MB_SETUP_DELAY */ mb_ide_resetting, /* IDE reset bit unser, waiting MB_IDE_WAIT */ + mb_ide_waiting, /* Waiting for BUSY bit to go away until MB_IDE_TIMEOUT */ mb_up, /* Media bay full */ mb_powering_down /* Powering down (avoid too fast down/up) */ }; @@ -339,12 +373,12 @@ static inline void set_mb_power(struct media_bay_info* bay, int onoff) if (onoff) { bay->ops->power(bay, 1); bay->state = mb_powering_up; - pr_debug("mediabay%d: powering up\n", bay->index); + MBDBG("mediabay%d: powering up\n", bay->index); } else { /* Make sure everything is powered down & disabled */ bay->ops->power(bay, 0); bay->state = mb_powering_down; - pr_debug("mediabay%d: powering down\n", bay->index); + MBDBG("mediabay%d: powering down\n", bay->index); } bay->timer = msecs_to_jiffies(MB_POWER_DELAY); } @@ -353,118 +387,107 @@ static void poll_media_bay(struct media_bay_info* bay) { int id = bay->ops->content(bay); - static char *mb_content_types[] = { - "a floppy drive", - "a floppy drive", - "an unsuported audio device", - "an ATA device", - "an unsupported PCI device", - "an unknown device", - }; - - if (id != bay->last_value) { + if (id == bay->last_value) { + if (id != bay->content_id) { + bay->value_count += msecs_to_jiffies(MB_POLL_DELAY); + if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) { + /* If the device type changes without going thru + * "MB_NO", we force a pass by "MB_NO" to make sure + * things are properly reset + */ + if ((id != MB_NO) && (bay->content_id != MB_NO)) { + id = MB_NO; + MBDBG("mediabay%d: forcing MB_NO\n", bay->index); + } + MBDBG("mediabay%d: switching to %d\n", bay->index, id); + set_mb_power(bay, id != MB_NO); + bay->content_id = id; + if (id == MB_NO) { +#ifdef CONFIG_BLK_DEV_IDE_PMAC + bay->cd_retry = 0; +#endif + printk(KERN_INFO "media bay %d is empty\n", bay->index); + } + } + } + } else { bay->last_value = id; bay->value_count = 0; - return; - } - if (id == bay->content_id) - return; - - bay->value_count += msecs_to_jiffies(MB_POLL_DELAY); - if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) { - /* If the device type changes without going thru - * "MB_NO", we force a pass by "MB_NO" to make sure - * things are properly reset - */ - if ((id != MB_NO) && (bay->content_id != MB_NO)) { - id = MB_NO; - pr_debug("mediabay%d: forcing MB_NO\n", bay->index); - } - pr_debug("mediabay%d: switching to %d\n", bay->index, id); - set_mb_power(bay, id != MB_NO); - bay->content_id = id; - if (id >= MB_NO || id < 0) - printk(KERN_INFO "mediabay%d: Bay is now empty\n", bay->index); - else - printk(KERN_INFO "mediabay%d: Bay contains %s\n", - bay->index, mb_content_types[id]); } } -int check_media_bay(struct macio_dev *baydev) +#ifdef CONFIG_BLK_DEV_IDE_PMAC +int check_media_bay(struct device_node *which_bay, int what) { - struct media_bay_info* bay; - int id; - - if (baydev == NULL) - return MB_NO; + int i; - /* This returns an instant snapshot, not locking, sine - * we may be called with the bay lock held. The resulting - * fuzzyness of the result if called at the wrong time is - * not actually a huge deal - */ - bay = macio_get_drvdata(baydev); - if (bay == NULL) - return MB_NO; - id = bay->content_id; - if (bay->state != mb_up) - return MB_NO; - if (id == MB_FD1) - return MB_FD; - return id; + for (i=0; iofdev.node) { + if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up) + return 0; + media_bays[i].cd_index = -1; + return -EINVAL; + } + return -ENODEV; } -EXPORT_SYMBOL_GPL(check_media_bay); +EXPORT_SYMBOL(check_media_bay); -void lock_media_bay(struct macio_dev *baydev) +int check_media_bay_by_base(unsigned long base, int what) { - struct media_bay_info* bay; - - if (baydev == NULL) - return; - bay = macio_get_drvdata(baydev); - if (bay == NULL) - return; - mutex_lock(&bay->lock); - bay->user_lock = 1; -} -EXPORT_SYMBOL_GPL(lock_media_bay); + int i; -void unlock_media_bay(struct macio_dev *baydev) -{ - struct media_bay_info* bay; + for (i=0; iuser_lock) { - bay->user_lock = 0; - mutex_unlock(&bay->lock); - } + return -ENODEV; } -EXPORT_SYMBOL_GPL(unlock_media_bay); +EXPORT_SYMBOL_GPL(check_media_bay_by_base); -static int mb_broadcast_hotplug(struct device *dev, void *data) +int media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base, + int irq, ide_hwif_t *hwif) { - struct media_bay_info* bay = data; - struct macio_dev *mdev; - struct macio_driver *drv; - int state; + int i; - if (dev->bus != &macio_bus_type) - return 0; + for (i=0; imdev && which_bay == bay->mdev->ofdev.node) { + int timeout = 5000, index = hwif->index; + + mutex_lock(&bay->lock); + + bay->cd_port = hwif; + bay->cd_base = (void __iomem *) base; + bay->cd_irq = irq; + + if ((MB_CD != bay->content_id) || bay->state != mb_up) { + mutex_unlock(&bay->lock); + return 0; + } + printk(KERN_DEBUG "Registered ide%d for media bay %d\n", index, i); + do { + if (MB_IDE_READY(i)) { + bay->cd_index = index; + mutex_unlock(&bay->lock); + return 0; + } + mdelay(1); + } while(--timeout); + printk(KERN_DEBUG "Timeount waiting IDE in bay %d\n", i); + mutex_unlock(&bay->lock); + return -ENODEV; + } + } - state = bay->state == mb_up ? bay->content_id : MB_NO; - if (state == MB_FD1) - state = MB_FD; - mdev = to_macio_device(dev); - drv = to_macio_driver(dev->driver); - if (dev->driver && drv->mediabay_event) - drv->mediabay_event(mdev, state); - return 0; + return -ENODEV; } +EXPORT_SYMBOL_GPL(media_bay_set_ide_infos); +#endif /* CONFIG_BLK_DEV_IDE_PMAC */ static void media_bay_step(int i) { @@ -474,8 +497,8 @@ static void media_bay_step(int i) if (bay->state != mb_powering_down) poll_media_bay(bay); - /* If timer expired run state machine */ - if (bay->timer != 0) { + /* If timer expired or polling IDE busy, run state machine */ + if ((bay->state != mb_ide_waiting) && (bay->timer != 0)) { bay->timer -= msecs_to_jiffies(MB_POLL_DELAY); if (bay->timer > 0) return; @@ -485,50 +508,100 @@ static void media_bay_step(int i) switch(bay->state) { case mb_powering_up: if (bay->ops->setup_bus(bay, bay->last_value) < 0) { - pr_debug("mediabay%d: device not supported (kind:%d)\n", - i, bay->content_id); + MBDBG("mediabay%d: device not supported (kind:%d)\n", i, bay->content_id); set_mb_power(bay, 0); break; } bay->timer = msecs_to_jiffies(MB_RESET_DELAY); bay->state = mb_enabling_bay; - pr_debug("mediabay%d: enabling (kind:%d)\n", i, bay->content_id); + MBDBG("mediabay%d: enabling (kind:%d)\n", i, bay->content_id); break; case mb_enabling_bay: bay->ops->un_reset(bay); bay->timer = msecs_to_jiffies(MB_SETUP_DELAY); bay->state = mb_resetting; - pr_debug("mediabay%d: releasing bay reset (kind:%d)\n", - i, bay->content_id); + MBDBG("mediabay%d: waiting reset (kind:%d)\n", i, bay->content_id); break; case mb_resetting: if (bay->content_id != MB_CD) { - pr_debug("mediabay%d: bay is up (kind:%d)\n", i, - bay->content_id); + MBDBG("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id); bay->state = mb_up; - device_for_each_child(&bay->mdev->ofdev.dev, - bay, mb_broadcast_hotplug); break; } - pr_debug("mediabay%d: releasing ATA reset (kind:%d)\n", - i, bay->content_id); +#ifdef CONFIG_BLK_DEV_IDE_PMAC + MBDBG("mediabay%d: waiting IDE reset (kind:%d)\n", i, bay->content_id); bay->ops->un_reset_ide(bay); bay->timer = msecs_to_jiffies(MB_IDE_WAIT); bay->state = mb_ide_resetting; +#else + printk(KERN_DEBUG "media-bay %d is ide (not compiled in kernel)\n", i); + set_mb_power(bay, 0); +#endif /* CONFIG_BLK_DEV_IDE_PMAC */ break; - +#ifdef CONFIG_BLK_DEV_IDE_PMAC case mb_ide_resetting: - pr_debug("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id); - bay->state = mb_up; - device_for_each_child(&bay->mdev->ofdev.dev, - bay, mb_broadcast_hotplug); + bay->timer = msecs_to_jiffies(MB_IDE_TIMEOUT); + bay->state = mb_ide_waiting; + MBDBG("mediabay%d: waiting IDE ready (kind:%d)\n", i, bay->content_id); break; - + case mb_ide_waiting: + if (bay->cd_base == NULL) { + bay->timer = 0; + bay->state = mb_up; + MBDBG("mediabay%d: up before IDE init\n", i); + break; + } else if (MB_IDE_READY(i)) { + bay->timer = 0; + bay->state = mb_up; + if (bay->cd_index < 0) { + printk("mediabay %d, registering IDE...\n", i); + pmu_suspend(); + ide_port_scan(bay->cd_port); + if (bay->cd_port->present) + bay->cd_index = bay->cd_port->index; + pmu_resume(); + } + if (bay->cd_index == -1) { + /* We eventually do a retry */ + bay->cd_retry++; + printk("IDE register error\n"); + set_mb_power(bay, 0); + } else { + printk(KERN_DEBUG "media-bay %d is ide%d\n", i, bay->cd_index); + MBDBG("mediabay %d IDE ready\n", i); + } + break; + } else if (bay->timer > 0) + bay->timer -= msecs_to_jiffies(MB_POLL_DELAY); + if (bay->timer <= 0) { + printk("\nIDE Timeout in bay %d !, IDE state is: 0x%02x\n", + i, readb(bay->cd_base + 0x70)); + MBDBG("mediabay%d: nIDE Timeout !\n", i); + set_mb_power(bay, 0); + bay->timer = 0; + } + break; +#endif /* CONFIG_BLK_DEV_IDE_PMAC */ case mb_powering_down: bay->state = mb_empty; - device_for_each_child(&bay->mdev->ofdev.dev, - bay, mb_broadcast_hotplug); - pr_debug("mediabay%d: end of power down\n", i); +#ifdef CONFIG_BLK_DEV_IDE_PMAC + if (bay->cd_index >= 0) { + printk(KERN_DEBUG "Unregistering mb %d ide, index:%d\n", i, + bay->cd_index); + ide_port_unregister_devices(bay->cd_port); + bay->cd_index = -1; + } + if (bay->cd_retry) { + if (bay->cd_retry > MAX_CD_RETRIES) { + /* Should add an error sound (sort of beep in dmasound) */ + printk("\nmedia-bay %d, IDE device badly inserted or unrecognised\n", i); + } else { + /* Force a new power down/up sequence */ + bay->content_id = MB_NO; + } + } +#endif /* CONFIG_BLK_DEV_IDE_PMAC */ + MBDBG("mediabay%d: end of power down\n", i); break; } } @@ -603,6 +676,11 @@ static int __devinit media_bay_attach(struct macio_dev *mdev, const struct of_de bay->last_value = bay->ops->content(bay); bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY); bay->state = mb_empty; + do { + msleep(MB_POLL_DELAY); + media_bay_step(i); + } while((bay->state != mb_empty) && + (bay->state != mb_up)); /* Mark us ready by filling our mdev data */ macio_set_drvdata(mdev, bay); @@ -647,7 +725,7 @@ static int media_bay_resume(struct macio_dev *mdev) set_mb_power(bay, 0); msleep(MB_POWER_DELAY); if (bay->ops->content(bay) != bay->content_id) { - printk("mediabay%d: Content changed during sleep...\n", bay->index); + printk("mediabay%d: content changed during sleep...\n", bay->index); mutex_unlock(&bay->lock); return 0; } @@ -655,6 +733,9 @@ static int media_bay_resume(struct macio_dev *mdev) bay->last_value = bay->content_id; bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY); bay->timer = msecs_to_jiffies(MB_POWER_DELAY); +#ifdef CONFIG_BLK_DEV_IDE_PMAC + bay->cd_retry = 0; +#endif do { msleep(MB_POLL_DELAY); media_bay_step(bay->index); @@ -742,6 +823,9 @@ static int __init media_bay_init(void) for (i=0; i #include #include +#include #include #include @@ -20,6 +21,7 @@ static loff_t nvram_llseek(struct file *file, loff_t offset, int origin) { + lock_kernel(); switch (origin) { case 1: offset += file->f_pos; @@ -28,10 +30,12 @@ static loff_t nvram_llseek(struct file *file, loff_t offset, int origin) offset += NVRAM_SIZE; break; } - if (offset < 0) + if (offset < 0) { + unlock_kernel(); return -EINVAL; - + } file->f_pos = offset; + unlock_kernel(); return file->f_pos; } @@ -72,7 +76,8 @@ static ssize_t write_nvram(struct file *file, const char __user *buf, return p - buf; } -static long nvram_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +static int nvram_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) { switch(cmd) { case PMAC_NVRAM_GET_OFFSET: diff --git a/trunk/drivers/macintosh/therm_adt746x.c b/trunk/drivers/macintosh/therm_adt746x.c index 5ff47ba7f2d0..556f0feaa4df 100644 --- a/trunk/drivers/macintosh/therm_adt746x.c +++ b/trunk/drivers/macintosh/therm_adt746x.c @@ -79,7 +79,6 @@ struct thermostat { u8 limits[3]; int last_speed[2]; int last_var[2]; - int pwm_inv[2]; }; static enum {ADT7460, ADT7467} therm_type; @@ -230,23 +229,19 @@ static void write_fan_speed(struct thermostat *th, int speed, int fan) if (speed >= 0) { manual = read_reg(th, MANUAL_MODE[fan]); - manual &= ~INVERT_MASK; write_reg(th, MANUAL_MODE[fan], - manual | MANUAL_MASK | th->pwm_inv[fan]); + (manual|MANUAL_MASK) & (~INVERT_MASK)); write_reg(th, FAN_SPD_SET[fan], speed); } else { /* back to automatic */ if(therm_type == ADT7460) { manual = read_reg(th, MANUAL_MODE[fan]) & (~MANUAL_MASK); - manual &= ~INVERT_MASK; - manual |= th->pwm_inv[fan]; + write_reg(th, MANUAL_MODE[fan], manual|REM_CONTROL[fan]); } else { manual = read_reg(th, MANUAL_MODE[fan]); - manual &= ~INVERT_MASK; - manual |= th->pwm_inv[fan]; write_reg(th, MANUAL_MODE[fan], manual&(~AUTO_MASK)); } } @@ -392,7 +387,7 @@ static int probe_thermostat(struct i2c_client *client, i2c_set_clientdata(client, th); th->clt = client; - rc = read_reg(th, CONFIG_REG); + rc = read_reg(th, 0); if (rc < 0) { dev_err(&client->dev, "Thermostat failed to read config!\n"); kfree(th); @@ -423,10 +418,6 @@ static int probe_thermostat(struct i2c_client *client, thermostat = th; - /* record invert bit status because fw can corrupt it after suspend */ - th->pwm_inv[0] = read_reg(th, MANUAL_MODE[0]) & INVERT_MASK; - th->pwm_inv[1] = read_reg(th, MANUAL_MODE[1]) & INVERT_MASK; - /* be sure to really write fan speed the first time */ th->last_speed[0] = -2; th->last_speed[1] = -2; diff --git a/trunk/drivers/macintosh/via-pmu.c b/trunk/drivers/macintosh/via-pmu.c index db379c381432..6f308a4757ee 100644 --- a/trunk/drivers/macintosh/via-pmu.c +++ b/trunk/drivers/macintosh/via-pmu.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -187,11 +186,17 @@ static int init_pmu(void); static void pmu_start(void); static irqreturn_t via_pmu_interrupt(int irq, void *arg); static irqreturn_t gpio1_interrupt(int irq, void *arg); -static const struct file_operations pmu_info_proc_fops; -static const struct file_operations pmu_irqstats_proc_fops; +static int proc_get_info(char *page, char **start, off_t off, + int count, int *eof, void *data); +static int proc_get_irqstats(char *page, char **start, off_t off, + int count, int *eof, void *data); static void pmu_pass_intr(unsigned char *data, int len); -static const struct file_operations pmu_battery_proc_fops; -static const struct file_operations pmu_options_proc_fops; +static int proc_get_batt(char *page, char **start, off_t off, + int count, int *eof, void *data); +static int proc_read_options(char *page, char **start, off_t off, + int count, int *eof, void *data); +static int proc_write_options(struct file *file, const char __user *buffer, + unsigned long count, void *data); #ifdef CONFIG_ADB struct adb_driver via_pmu_driver = { @@ -502,15 +507,19 @@ static int __init via_pmu_dev_init(void) for (i=0; iread_proc = proc_read_options; + proc_pmu_options->write_proc = proc_write_options; + } } return 0; } @@ -790,33 +799,27 @@ query_battery_state(void) 2, PMU_SMART_BATTERY_STATE, pmu_cur_battery+1); } -static int pmu_info_proc_show(struct seq_file *m, void *v) +static int +proc_get_info(char *page, char **start, off_t off, + int count, int *eof, void *data) { - seq_printf(m, "PMU driver version : %d\n", PMU_DRIVER_VERSION); - seq_printf(m, "PMU firmware version : %02x\n", pmu_version); - seq_printf(m, "AC Power : %d\n", - ((pmu_power_flags & PMU_PWR_AC_PRESENT) != 0) || pmu_battery_count == 0); - seq_printf(m, "Battery count : %d\n", pmu_battery_count); + char* p = page; - return 0; -} + p += sprintf(p, "PMU driver version : %d\n", PMU_DRIVER_VERSION); + p += sprintf(p, "PMU firmware version : %02x\n", pmu_version); + p += sprintf(p, "AC Power : %d\n", + ((pmu_power_flags & PMU_PWR_AC_PRESENT) != 0) || pmu_battery_count == 0); + p += sprintf(p, "Battery count : %d\n", pmu_battery_count); -static int pmu_info_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, pmu_info_proc_show, NULL); + return p - page; } -static const struct file_operations pmu_info_proc_fops = { - .owner = THIS_MODULE, - .open = pmu_info_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int pmu_irqstats_proc_show(struct seq_file *m, void *v) +static int +proc_get_irqstats(char *page, char **start, off_t off, + int count, int *eof, void *data) { int i; + char* p = page; static const char *irq_names[] = { "Total CB1 triggered events", "Total GPIO1 triggered events", @@ -832,76 +835,60 @@ static int pmu_irqstats_proc_show(struct seq_file *m, void *v) }; for (i=0; i<11; i++) { - seq_printf(m, " %2u: %10u (%s)\n", + p += sprintf(p, " %2u: %10u (%s)\n", i, pmu_irq_stats[i], irq_names[i]); } - return 0; -} - -static int pmu_irqstats_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, pmu_irqstats_proc_show, NULL); + return p - page; } -static const struct file_operations pmu_irqstats_proc_fops = { - .owner = THIS_MODULE, - .open = pmu_irqstats_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int pmu_battery_proc_show(struct seq_file *m, void *v) +static int +proc_get_batt(char *page, char **start, off_t off, + int count, int *eof, void *data) { - long batnum = (long)m->private; + long batnum = (long)data; + char *p = page; - seq_putc(m, '\n'); - seq_printf(m, "flags : %08x\n", pmu_batteries[batnum].flags); - seq_printf(m, "charge : %d\n", pmu_batteries[batnum].charge); - seq_printf(m, "max_charge : %d\n", pmu_batteries[batnum].max_charge); - seq_printf(m, "current : %d\n", pmu_batteries[batnum].amperage); - seq_printf(m, "voltage : %d\n", pmu_batteries[batnum].voltage); - seq_printf(m, "time rem. : %d\n", pmu_batteries[batnum].time_remaining); - return 0; + p += sprintf(p, "\n"); + p += sprintf(p, "flags : %08x\n", + pmu_batteries[batnum].flags); + p += sprintf(p, "charge : %d\n", + pmu_batteries[batnum].charge); + p += sprintf(p, "max_charge : %d\n", + pmu_batteries[batnum].max_charge); + p += sprintf(p, "current : %d\n", + pmu_batteries[batnum].amperage); + p += sprintf(p, "voltage : %d\n", + pmu_batteries[batnum].voltage); + p += sprintf(p, "time rem. : %d\n", + pmu_batteries[batnum].time_remaining); + + return p - page; } -static int pmu_battery_proc_open(struct inode *inode, struct file *file) +static int +proc_read_options(char *page, char **start, off_t off, + int count, int *eof, void *data) { - return single_open(file, pmu_battery_proc_show, PDE(inode)->data); -} + char *p = page; -static const struct file_operations pmu_battery_proc_fops = { - .owner = THIS_MODULE, - .open = pmu_battery_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int pmu_options_proc_show(struct seq_file *m, void *v) -{ #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32) if (pmu_kind == PMU_KEYLARGO_BASED && pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,0,-1) >= 0) - seq_printf(m, "lid_wakeup=%d\n", option_lid_wakeup); + p += sprintf(p, "lid_wakeup=%d\n", option_lid_wakeup); #endif if (pmu_kind == PMU_KEYLARGO_BASED) - seq_printf(m, "server_mode=%d\n", option_server_mode); + p += sprintf(p, "server_mode=%d\n", option_server_mode); - return 0; + return p - page; } - -static int pmu_options_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, pmu_options_proc_show, NULL); -} - -static ssize_t pmu_options_proc_write(struct file *file, - const char __user *buffer, size_t count, loff_t *pos) + +static int +proc_write_options(struct file *file, const char __user *buffer, + unsigned long count, void *data) { char tmp[33]; char *label, *val; - size_t fcount = count; + unsigned long fcount = count; if (!count) return -EINVAL; @@ -940,15 +927,6 @@ static ssize_t pmu_options_proc_write(struct file *file, return fcount; } -static const struct file_operations pmu_options_proc_fops = { - .owner = THIS_MODULE, - .open = pmu_options_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .write = pmu_options_proc_write, -}; - #ifdef CONFIG_ADB /* Send an ADB command */ static int pmu_send_request(struct adb_request *req, int sync) diff --git a/trunk/drivers/macintosh/windfarm_smu_controls.c b/trunk/drivers/macintosh/windfarm_smu_controls.c index 6c68b9e5f5c4..961fa0e7c2cf 100644 --- a/trunk/drivers/macintosh/windfarm_smu_controls.c +++ b/trunk/drivers/macintosh/windfarm_smu_controls.c @@ -202,8 +202,6 @@ static struct smu_fan_control *smu_fan_create(struct device_node *node, fct->ctrl.name = "cpu-front-fan-1"; else if (!strcmp(l, "CPU A PUMP")) fct->ctrl.name = "cpu-pump-0"; - else if (!strcmp(l, "CPU B PUMP")) - fct->ctrl.name = "cpu-pump-1"; else if (!strcmp(l, "Slots Fan") || !strcmp(l, "Slots fan") || !strcmp(l, "EXPANSION SLOTS INTAKE")) fct->ctrl.name = "slots-fan"; diff --git a/trunk/drivers/mmc/host/of_mmc_spi.c b/trunk/drivers/mmc/host/of_mmc_spi.c index 0c7a63c1f12f..0c44d560bf1a 100644 --- a/trunk/drivers/mmc/host/of_mmc_spi.c +++ b/trunk/drivers/mmc/host/of_mmc_spi.c @@ -22,8 +22,6 @@ #include #include -MODULE_LICENSE("GPL"); - enum { CD_GPIO = 0, WP_GPIO, diff --git a/trunk/drivers/net/arm/ixp4xx_eth.c b/trunk/drivers/net/arm/ixp4xx_eth.c index c3dfbdd2cdcf..691b81eb0f46 100644 --- a/trunk/drivers/net/arm/ixp4xx_eth.c +++ b/trunk/drivers/net/arm/ixp4xx_eth.c @@ -322,7 +322,7 @@ static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); spin_unlock_irqrestore(&mdio_lock, flags); #if DEBUG_MDIO - printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", + printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n", bus->name, phy_id, location, val, ret); #endif return ret; diff --git a/trunk/drivers/net/benet/be_main.c b/trunk/drivers/net/benet/be_main.c index 3a1f7902c16d..24c7d9900baa 100644 --- a/trunk/drivers/net/benet/be_main.c +++ b/trunk/drivers/net/benet/be_main.c @@ -759,7 +759,7 @@ static void be_rx_compl_process(struct be_adapter *adapter, /* vlanf could be wrongly set in some cards. * ignore if vtm is not set */ - if ((adapter->cap & 0x400) && !vtm) + if ((adapter->cap == 0x400) && !vtm) vlanf = 0; skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN); @@ -816,7 +816,7 @@ static void be_rx_compl_process_gro(struct be_adapter *adapter, /* vlanf could be wrongly set in some cards. * ignore if vtm is not set */ - if ((adapter->cap & 0x400) && !vtm) + if ((adapter->cap == 0x400) && !vtm) vlanf = 0; skb = napi_get_frags(&eq_obj->napi); diff --git a/trunk/drivers/net/ehea/ehea_hcall.h b/trunk/drivers/net/ehea/ehea_hcall.h new file mode 100644 index 000000000000..8e7d1c3edc60 --- /dev/null +++ b/trunk/drivers/net/ehea/ehea_hcall.h @@ -0,0 +1,51 @@ +/* + * linux/drivers/net/ehea/ehea_hcall.h + * + * eHEA ethernet device driver for IBM eServer System p + * + * (C) Copyright IBM Corp. 2006 + * + * Authors: + * Christoph Raisch + * Jan-Bernd Themann + * Thomas Klein + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EHEA_HCALL_H__ +#define __EHEA_HCALL_H__ + +/** + * This file contains HCALL defines that are to be included in the appropriate + * kernel files later + */ + +#define H_ALLOC_HEA_RESOURCE 0x278 +#define H_MODIFY_HEA_QP 0x250 +#define H_QUERY_HEA_QP 0x254 +#define H_QUERY_HEA 0x258 +#define H_QUERY_HEA_PORT 0x25C +#define H_MODIFY_HEA_PORT 0x260 +#define H_REG_BCMC 0x264 +#define H_DEREG_BCMC 0x268 +#define H_REGISTER_HEA_RPAGES 0x26C +#define H_DISABLE_AND_GET_HEA 0x270 +#define H_GET_HEA_INFO 0x274 +#define H_ADD_CONN 0x284 +#define H_DEL_CONN 0x288 + +#endif /* __EHEA_HCALL_H__ */ diff --git a/trunk/drivers/net/ehea/ehea_phyp.h b/trunk/drivers/net/ehea/ehea_phyp.h index 2f8174c248bc..f3628c803567 100644 --- a/trunk/drivers/net/ehea/ehea_phyp.h +++ b/trunk/drivers/net/ehea/ehea_phyp.h @@ -33,6 +33,7 @@ #include #include "ehea.h" #include "ehea_hw.h" +#include "ehea_hcall.h" /* Some abbreviations used here: * diff --git a/trunk/drivers/net/igb/igb_main.c b/trunk/drivers/net/igb/igb_main.c index 78963a0e128d..16349ba68736 100644 --- a/trunk/drivers/net/igb/igb_main.c +++ b/trunk/drivers/net/igb/igb_main.c @@ -4608,14 +4608,8 @@ static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); - if (retval) { - /* if receive failed revoke VF CTS stats and restart init */ + if (retval) dev_err(&pdev->dev, "Error receiving message from VF\n"); - vf_data->flags &= ~IGB_VF_FLAG_CTS; - if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) - return; - goto out; - } /* this is a message we already processed, do nothing */ if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) @@ -4632,10 +4626,12 @@ static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) } if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { - if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) - return; - retval = -1; - goto out; + msgbuf[0] = E1000_VT_MSGTYPE_NACK; + if (time_after(jiffies, vf_data->last_nack + (2 * HZ))) { + igb_write_mbx(hw, msgbuf, 1, vf); + vf_data->last_nack = jiffies; + } + return; } switch ((msgbuf[0] & 0xFFFF)) { @@ -4660,14 +4656,14 @@ static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) break; } - msgbuf[0] |= E1000_VT_MSGTYPE_CTS; -out: /* notify the VF of the results of what it sent us */ if (retval) msgbuf[0] |= E1000_VT_MSGTYPE_NACK; else msgbuf[0] |= E1000_VT_MSGTYPE_ACK; + msgbuf[0] |= E1000_VT_MSGTYPE_CTS; + igb_write_mbx(hw, msgbuf, 1, vf); } diff --git a/trunk/drivers/net/igbvf/igbvf.h b/trunk/drivers/net/igbvf/igbvf.h index a1774b29d222..3d1ee7a8478e 100644 --- a/trunk/drivers/net/igbvf/igbvf.h +++ b/trunk/drivers/net/igbvf/igbvf.h @@ -276,7 +276,6 @@ struct igbvf_adapter { unsigned long led_status; unsigned int flags; - unsigned long last_reset; }; struct igbvf_info { diff --git a/trunk/drivers/net/igbvf/netdev.c b/trunk/drivers/net/igbvf/netdev.c index e9dd95f136aa..a127620dc653 100644 --- a/trunk/drivers/net/igbvf/netdev.c +++ b/trunk/drivers/net/igbvf/netdev.c @@ -1469,8 +1469,6 @@ static void igbvf_reset(struct igbvf_adapter *adapter) memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); } - - adapter->last_reset = jiffies; } int igbvf_up(struct igbvf_adapter *adapter) @@ -1814,15 +1812,11 @@ static bool igbvf_has_link(struct igbvf_adapter *adapter) s32 ret_val = E1000_SUCCESS; bool link_active; - /* If interface is down, stay link down */ - if (test_bit(__IGBVF_DOWN, &adapter->state)) - return false; - ret_val = hw->mac.ops.check_for_link(hw); link_active = !hw->mac.get_link_status; /* if check for link returns error we will need to reset */ - if (ret_val && time_after(jiffies, adapter->last_reset + (10 * HZ))) + if (ret_val) schedule_work(&adapter->reset_task); return link_active; diff --git a/trunk/drivers/net/smc91x.h b/trunk/drivers/net/smc91x.h index 54799544bda3..7815bfc300f5 100644 --- a/trunk/drivers/net/smc91x.h +++ b/trunk/drivers/net/smc91x.h @@ -206,6 +206,21 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) } } +#elif defined(CONFIG_ARCH_OMAP) + +/* We can only do 16-bit reads and writes in the static memory space. */ +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) +#define SMC_IRQ_FLAGS (-1) /* from resource */ + #elif defined(CONFIG_SH_SH4202_MICRODEV) #define SMC_CAN_USE_8BIT 0 diff --git a/trunk/drivers/net/usb/kaweth.c b/trunk/drivers/net/usb/kaweth.c index f1d64ef67efa..3b80e8d2d621 100644 --- a/trunk/drivers/net/usb/kaweth.c +++ b/trunk/drivers/net/usb/kaweth.c @@ -716,7 +716,7 @@ static int kaweth_open(struct net_device *net) return 0; err_out: - usb_autopm_put_interface(kaweth->intf); + usb_autopm_enable(kaweth->intf); return -EIO; } @@ -753,7 +753,7 @@ static int kaweth_close(struct net_device *net) kaweth->status &= ~KAWETH_STATUS_CLOSING; - usb_autopm_put_interface(kaweth->intf); + usb_autopm_enable(kaweth->intf); return 0; } diff --git a/trunk/drivers/of/platform.c b/trunk/drivers/of/platform.c index d58ade170c4b..298de0f95d70 100644 --- a/trunk/drivers/of/platform.c +++ b/trunk/drivers/of/platform.c @@ -65,322 +65,47 @@ static int of_platform_device_remove(struct device *dev) return 0; } -static void of_platform_device_shutdown(struct device *dev) +static int of_platform_device_suspend(struct device *dev, pm_message_t state) { struct of_device *of_dev = to_of_device(dev); struct of_platform_driver *drv = to_of_platform_driver(dev->driver); - - if (dev->driver && drv->shutdown) - drv->shutdown(of_dev); -} - -#ifdef CONFIG_PM_SLEEP - -static int of_platform_legacy_suspend(struct device *dev, pm_message_t mesg) -{ - struct of_device *of_dev = to_of_device(dev); - struct of_platform_driver *drv = to_of_platform_driver(dev->driver); - int ret = 0; + int error = 0; if (dev->driver && drv->suspend) - ret = drv->suspend(of_dev, mesg); - return ret; + error = drv->suspend(of_dev, state); + return error; } -static int of_platform_legacy_resume(struct device *dev) +static int of_platform_device_resume(struct device * dev) { struct of_device *of_dev = to_of_device(dev); struct of_platform_driver *drv = to_of_platform_driver(dev->driver); - int ret = 0; + int error = 0; if (dev->driver && drv->resume) - ret = drv->resume(of_dev); - return ret; -} - -static int of_platform_pm_prepare(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (drv && drv->pm && drv->pm->prepare) - ret = drv->pm->prepare(dev); - - return ret; -} - -static void of_platform_pm_complete(struct device *dev) -{ - struct device_driver *drv = dev->driver; - - if (drv && drv->pm && drv->pm->complete) - drv->pm->complete(dev); -} - -#ifdef CONFIG_SUSPEND - -static int of_platform_pm_suspend(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->suspend) - ret = drv->pm->suspend(dev); - } else { - ret = of_platform_legacy_suspend(dev, PMSG_SUSPEND); - } - - return ret; -} - -static int of_platform_pm_suspend_noirq(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->suspend_noirq) - ret = drv->pm->suspend_noirq(dev); - } - - return ret; -} - -static int of_platform_pm_resume(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->resume) - ret = drv->pm->resume(dev); - } else { - ret = of_platform_legacy_resume(dev); - } - - return ret; -} - -static int of_platform_pm_resume_noirq(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->resume_noirq) - ret = drv->pm->resume_noirq(dev); - } - - return ret; -} - -#else /* !CONFIG_SUSPEND */ - -#define of_platform_pm_suspend NULL -#define of_platform_pm_resume NULL -#define of_platform_pm_suspend_noirq NULL -#define of_platform_pm_resume_noirq NULL - -#endif /* !CONFIG_SUSPEND */ - -#ifdef CONFIG_HIBERNATION - -static int of_platform_pm_freeze(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->freeze) - ret = drv->pm->freeze(dev); - } else { - ret = of_platform_legacy_suspend(dev, PMSG_FREEZE); - } - - return ret; -} - -static int of_platform_pm_freeze_noirq(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->freeze_noirq) - ret = drv->pm->freeze_noirq(dev); - } - - return ret; -} - -static int of_platform_pm_thaw(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->thaw) - ret = drv->pm->thaw(dev); - } else { - ret = of_platform_legacy_resume(dev); - } - - return ret; -} - -static int of_platform_pm_thaw_noirq(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->thaw_noirq) - ret = drv->pm->thaw_noirq(dev); - } - - return ret; -} - -static int of_platform_pm_poweroff(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->poweroff) - ret = drv->pm->poweroff(dev); - } else { - ret = of_platform_legacy_suspend(dev, PMSG_HIBERNATE); - } - - return ret; -} - -static int of_platform_pm_poweroff_noirq(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->poweroff_noirq) - ret = drv->pm->poweroff_noirq(dev); - } - - return ret; -} - -static int of_platform_pm_restore(struct device *dev) -{ - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->restore) - ret = drv->pm->restore(dev); - } else { - ret = of_platform_legacy_resume(dev); - } - - return ret; + error = drv->resume(of_dev); + return error; } -static int of_platform_pm_restore_noirq(struct device *dev) +static void of_platform_device_shutdown(struct device *dev) { - struct device_driver *drv = dev->driver; - int ret = 0; - - if (!drv) - return 0; - - if (drv->pm) { - if (drv->pm->restore_noirq) - ret = drv->pm->restore_noirq(dev); - } + struct of_device *of_dev = to_of_device(dev); + struct of_platform_driver *drv = to_of_platform_driver(dev->driver); - return ret; + if (dev->driver && drv->shutdown) + drv->shutdown(of_dev); } -#else /* !CONFIG_HIBERNATION */ - -#define of_platform_pm_freeze NULL -#define of_platform_pm_thaw NULL -#define of_platform_pm_poweroff NULL -#define of_platform_pm_restore NULL -#define of_platform_pm_freeze_noirq NULL -#define of_platform_pm_thaw_noirq NULL -#define of_platform_pm_poweroff_noirq NULL -#define of_platform_pm_restore_noirq NULL - -#endif /* !CONFIG_HIBERNATION */ - -static struct dev_pm_ops of_platform_dev_pm_ops = { - .prepare = of_platform_pm_prepare, - .complete = of_platform_pm_complete, - .suspend = of_platform_pm_suspend, - .resume = of_platform_pm_resume, - .freeze = of_platform_pm_freeze, - .thaw = of_platform_pm_thaw, - .poweroff = of_platform_pm_poweroff, - .restore = of_platform_pm_restore, - .suspend_noirq = of_platform_pm_suspend_noirq, - .resume_noirq = of_platform_pm_resume_noirq, - .freeze_noirq = of_platform_pm_freeze_noirq, - .thaw_noirq = of_platform_pm_thaw_noirq, - .poweroff_noirq = of_platform_pm_poweroff_noirq, - .restore_noirq = of_platform_pm_restore_noirq, -}; - -#define OF_PLATFORM_PM_OPS_PTR (&of_platform_dev_pm_ops) - -#else /* !CONFIG_PM_SLEEP */ - -#define OF_PLATFORM_PM_OPS_PTR NULL - -#endif /* !CONFIG_PM_SLEEP */ - int of_bus_type_init(struct bus_type *bus, const char *name) { bus->name = name; bus->match = of_platform_bus_match; bus->probe = of_platform_device_probe; bus->remove = of_platform_device_remove; + bus->suspend = of_platform_device_suspend; + bus->resume = of_platform_device_resume; bus->shutdown = of_platform_device_shutdown; bus->dev_attrs = of_platform_device_attrs; - bus->pm = OF_PLATFORM_PM_OPS_PTR; return bus_register(bus); } diff --git a/trunk/drivers/pcmcia/Kconfig b/trunk/drivers/pcmcia/Kconfig index 58bee55a3dd3..cd5082d3ca19 100644 --- a/trunk/drivers/pcmcia/Kconfig +++ b/trunk/drivers/pcmcia/Kconfig @@ -208,7 +208,7 @@ config PCMCIA_PXA2XX depends on ARM && ARCH_PXA && PCMCIA depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \ || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \ - || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2) + || ARCH_VIPER || ARCH_PXA_ESERIES || MACH_STARGATE2) select PCMCIA_SOC_COMMON help Say Y here to include support for the PXA2xx PCMCIA controller diff --git a/trunk/drivers/pcmcia/Makefile b/trunk/drivers/pcmcia/Makefile index 83ff802de544..382938313991 100644 --- a/trunk/drivers/pcmcia/Makefile +++ b/trunk/drivers/pcmcia/Makefile @@ -67,7 +67,7 @@ pxa2xx-obj-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock_cs.o pxa2xx-obj-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o pxa2xx-obj-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o pxa2xx-obj-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x2xx_cs.o -pxa2xx-obj-$(CONFIG_ARCOM_PCMCIA) += pxa2xx_viper.o +pxa2xx-obj-$(CONFIG_ARCH_VIPER) += pxa2xx_viper.o pxa2xx-obj-$(CONFIG_TRIZEPS_PCMCIA) += pxa2xx_trizeps4.o pxa2xx-obj-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o pxa2xx-obj-$(CONFIG_MACH_PALMTC) += pxa2xx_palmtc.o diff --git a/trunk/drivers/pcmcia/pxa2xx_base.c b/trunk/drivers/pcmcia/pxa2xx_base.c index 87481ce60dfb..bae8e6e2d48c 100644 --- a/trunk/drivers/pcmcia/pxa2xx_base.c +++ b/trunk/drivers/pcmcia/pxa2xx_base.c @@ -214,8 +214,7 @@ static void pxa2xx_configure_sockets(struct device *dev) MECR |= MECR_CIT; /* Set MECR:NOS (Number Of Sockets) */ - if ((ops->first + ops->nr) > 1 || - machine_is_viper() || machine_is_arcom_zeus()) + if ((ops->first + ops->nr) > 1 || machine_is_viper()) MECR |= MECR_NOS; else MECR &= ~MECR_NOS; @@ -253,6 +252,7 @@ int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt) return soc_pcmcia_add_one(skt); } +EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one); void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops) { @@ -262,19 +262,19 @@ void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops) ops->frequency_change = pxa2xx_pcmcia_frequency_change; #endif } +EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops); -int __pxa2xx_drv_pcmcia_probe(struct device *dev) +static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) { int i, ret = 0; struct pcmcia_low_level *ops; struct skt_dev_info *sinfo; struct soc_pcmcia_socket *skt; - if (!dev || !dev->platform_data) + ops = (struct pcmcia_low_level *)dev->dev.platform_data; + if (!ops) return -ENODEV; - ops = (struct pcmcia_low_level *)dev->platform_data; - pxa2xx_drv_pcmcia_ops(ops); sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); @@ -309,13 +309,6 @@ int __pxa2xx_drv_pcmcia_probe(struct device *dev) return ret; } -EXPORT_SYMBOL(__pxa2xx_drv_pcmcia_probe); - - -static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) -{ - return __pxa2xx_drv_pcmcia_probe(&dev->dev); -} static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) { diff --git a/trunk/drivers/pcmcia/pxa2xx_base.h b/trunk/drivers/pcmcia/pxa2xx_base.h index cb5efaec886f..bb62ea87b8f9 100644 --- a/trunk/drivers/pcmcia/pxa2xx_base.h +++ b/trunk/drivers/pcmcia/pxa2xx_base.h @@ -1,6 +1,3 @@ -/* temporary measure */ -extern int __pxa2xx_drv_pcmcia_probe(struct device *); - int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt); void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops); diff --git a/trunk/drivers/pcmcia/pxa2xx_viper.c b/trunk/drivers/pcmcia/pxa2xx_viper.c index a51f2077644a..27be2e154df2 100644 --- a/trunk/drivers/pcmcia/pxa2xx_viper.c +++ b/trunk/drivers/pcmcia/pxa2xx_viper.c @@ -1,8 +1,9 @@ /* - * Viper/Zeus PCMCIA support + * VIPER PCMCIA support * Copyright 2004 Arcom Control Systems * * Maintained by Marc Zyngier + * * * Based on: * iPAQ h2200 PCMCIA support @@ -25,47 +26,37 @@ #include -#include +#include +#include #include "soc_common.h" #include "pxa2xx_base.h" -static struct platform_device *arcom_pcmcia_dev; - static struct pcmcia_irqs irqs[] = { - { - .sock = 0, - .str = "PCMCIA_CD", - }, + { 0, gpio_to_irq(VIPER_CF_CD_GPIO), "PCMCIA_CD" } }; -static inline struct arcom_pcmcia_pdata *viper_get_pdata(void) -{ - return arcom_pcmcia_dev->dev.platform_data; -} - static int viper_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { - struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); unsigned long flags; - skt->socket.pci_irq = gpio_to_irq(pdata->rdy_gpio); - irqs[0].irq = gpio_to_irq(pdata->cd_gpio); + skt->socket.pci_irq = gpio_to_irq(VIPER_CF_RDY_GPIO); - if (gpio_request(pdata->cd_gpio, "CF detect")) + if (gpio_request(VIPER_CF_CD_GPIO, "CF detect")) goto err_request_cd; - if (gpio_request(pdata->rdy_gpio, "CF ready")) + if (gpio_request(VIPER_CF_RDY_GPIO, "CF ready")) goto err_request_rdy; - if (gpio_request(pdata->pwr_gpio, "CF power")) + if (gpio_request(VIPER_CF_POWER_GPIO, "CF power")) goto err_request_pwr; local_irq_save(flags); - if (gpio_direction_output(pdata->pwr_gpio, 0) || - gpio_direction_input(pdata->cd_gpio) || - gpio_direction_input(pdata->rdy_gpio)) { + /* GPIO 82 is the CF power enable line. initially off */ + if (gpio_direction_output(VIPER_CF_POWER_GPIO, 0) || + gpio_direction_input(VIPER_CF_CD_GPIO) || + gpio_direction_input(VIPER_CF_RDY_GPIO)) { local_irq_restore(flags); goto err_dir; } @@ -75,13 +66,13 @@ static int viper_pcmcia_hw_init(struct soc_pcmcia_socket *skt) return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); err_dir: - gpio_free(pdata->pwr_gpio); + gpio_free(VIPER_CF_POWER_GPIO); err_request_pwr: - gpio_free(pdata->rdy_gpio); + gpio_free(VIPER_CF_RDY_GPIO); err_request_rdy: - gpio_free(pdata->cd_gpio); + gpio_free(VIPER_CF_CD_GPIO); err_request_cd: - dev_err(&arcom_pcmcia_dev->dev, "Failed to setup PCMCIA GPIOs\n"); + printk(KERN_ERR "viper: Failed to setup PCMCIA GPIOs\n"); return -1; } @@ -90,21 +81,17 @@ static int viper_pcmcia_hw_init(struct soc_pcmcia_socket *skt) */ static void viper_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) { - struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); - soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); - gpio_free(pdata->pwr_gpio); - gpio_free(pdata->rdy_gpio); - gpio_free(pdata->cd_gpio); + gpio_free(VIPER_CF_POWER_GPIO); + gpio_free(VIPER_CF_RDY_GPIO); + gpio_free(VIPER_CF_CD_GPIO); } static void viper_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); - - state->detect = !gpio_get_value(pdata->cd_gpio); - state->ready = !!gpio_get_value(pdata->rdy_gpio); + state->detect = gpio_get_value(VIPER_CF_CD_GPIO) ? 0 : 1; + state->ready = gpio_get_value(VIPER_CF_RDY_GPIO) ? 1 : 0; state->bvd1 = 1; state->bvd2 = 1; state->wrprot = 0; @@ -115,21 +102,20 @@ static void viper_pcmcia_socket_state(struct soc_pcmcia_socket *skt, static int viper_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) { - struct arcom_pcmcia_pdata *pdata = viper_get_pdata(); - /* Silently ignore Vpp, output enable, speaker enable. */ - pdata->reset(state->flags & SS_RESET); + viper_cf_rst(state->flags & SS_RESET); /* Apply socket voltage */ switch (state->Vcc) { case 0: - gpio_set_value(pdata->pwr_gpio, 0); + gpio_set_value(VIPER_CF_POWER_GPIO, 0); break; case 33: - gpio_set_value(pdata->pwr_gpio, 1); + gpio_set_value(VIPER_CF_POWER_GPIO, 1); break; default: - dev_err(&arcom_pcmcia_dev->dev, "Unsupported Vcc:%d\n", state->Vcc); + printk(KERN_ERR "%s: Unsupported Vcc:%d\n", + __func__, state->Vcc); return -1; } @@ -144,7 +130,7 @@ static void viper_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) { } -static struct pcmcia_low_level viper_pcmcia_ops = { +static struct pcmcia_low_level viper_pcmcia_ops __initdata = { .owner = THIS_MODULE, .hw_init = viper_pcmcia_hw_init, .hw_shutdown = viper_pcmcia_hw_shutdown, @@ -157,25 +143,17 @@ static struct pcmcia_low_level viper_pcmcia_ops = { static struct platform_device *viper_pcmcia_device; -static int viper_pcmcia_probe(struct platform_device *pdev) +static int __init viper_pcmcia_init(void) { int ret; - /* I can't imagine more than one device, but you never know... */ - if (arcom_pcmcia_dev) - return -EEXIST; - - if (!pdev->dev.platform_data) - return -EINVAL; + if (!machine_is_viper()) + return -ENODEV; viper_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); if (!viper_pcmcia_device) return -ENOMEM; - arcom_pcmcia_dev = pdev; - - viper_pcmcia_device->dev.parent = &pdev->dev; - ret = platform_device_add_data(viper_pcmcia_device, &viper_pcmcia_ops, sizeof(viper_pcmcia_ops)); @@ -183,49 +161,18 @@ static int viper_pcmcia_probe(struct platform_device *pdev) if (!ret) ret = platform_device_add(viper_pcmcia_device); - if (ret) { + if (ret) platform_device_put(viper_pcmcia_device); - arcom_pcmcia_dev = NULL; - } return ret; } -static int viper_pcmcia_remove(struct platform_device *pdev) -{ - platform_device_unregister(viper_pcmcia_device); - arcom_pcmcia_dev = NULL; - return 0; -} - -static struct platform_device_id viper_pcmcia_id_table[] = { - { .name = "viper-pcmcia", }, - { .name = "zeus-pcmcia", }, - { }, -}; - -static struct platform_driver viper_pcmcia_driver = { - .probe = viper_pcmcia_probe, - .remove = viper_pcmcia_remove, - .driver = { - .name = "arcom-pcmcia", - .owner = THIS_MODULE, - }, - .id_table = viper_pcmcia_id_table, -}; - -static int __init viper_pcmcia_init(void) -{ - return platform_driver_register(&viper_pcmcia_driver); -} - static void __exit viper_pcmcia_exit(void) { - return platform_driver_unregister(&viper_pcmcia_driver); + platform_device_unregister(viper_pcmcia_device); } module_init(viper_pcmcia_init); module_exit(viper_pcmcia_exit); -MODULE_DEVICE_TABLE(platform, viper_pcmcia_id_table); MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/spi/Kconfig b/trunk/drivers/spi/Kconfig index 28fce65b8594..4b6f7cba3b3d 100644 --- a/trunk/drivers/spi/Kconfig +++ b/trunk/drivers/spi/Kconfig @@ -133,14 +133,6 @@ config SPI_LM70_LLP which interfaces to an LM70 temperature sensor using a parallel port. -config SPI_MPC52xx - tristate "Freescale MPC52xx SPI (non-PSC) controller support" - depends on PPC_MPC52xx && SPI - select SPI_MASTER_OF - help - This drivers supports the MPC52xx SPI controller in master SPI - mode. - config SPI_MPC52xx_PSC tristate "Freescale MPC52xx PSC SPI controller" depends on PPC_MPC52xx && EXPERIMENTAL @@ -155,6 +147,9 @@ config SPI_MPC8xxx This enables using the Freescale MPC8xxx SPI controllers in master mode. + This driver uses a simple set of shift registers for data (opposed + to the CPM based descriptor model). + config SPI_OMAP_UWIRE tristate "OMAP1 MicroWire" depends on ARCH_OMAP1 diff --git a/trunk/drivers/spi/Makefile b/trunk/drivers/spi/Makefile index e3f092a9afa5..21a118269cac 100644 --- a/trunk/drivers/spi/Makefile +++ b/trunk/drivers/spi/Makefile @@ -25,7 +25,6 @@ obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o obj-$(CONFIG_SPI_ORION) += orion_spi.o obj-$(CONFIG_SPI_PL022) += amba-pl022.o obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o -obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o diff --git a/trunk/drivers/spi/mpc52xx_psc_spi.c b/trunk/drivers/spi/mpc52xx_psc_spi.c index f50c81df336a..1b74d5ca03f3 100644 --- a/trunk/drivers/spi/mpc52xx_psc_spi.c +++ b/trunk/drivers/spi/mpc52xx_psc_spi.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -314,13 +313,11 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) struct mpc52xx_psc __iomem *psc = mps->psc; struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; u32 mclken_div; - int ret; + int ret = 0; /* default sysclk is 512MHz */ mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; - ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div); - if (ret) - return ret; + mpc52xx_set_psc_clkdiv(psc_id, mclken_div); /* Reset the PSC into a known state */ out_8(&psc->command, MPC52xx_PSC_RST_RX); @@ -344,7 +341,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) mps->bits_per_word = 8; - return 0; + return ret; } static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) @@ -413,10 +410,8 @@ static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, goto free_master; ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); - if (ret < 0) { - dev_err(dev, "can't configure PSC! Is it capable of SPI?\n"); + if (ret < 0) goto free_irq; - } spin_lock_init(&mps->lock); init_completion(&mps->done); @@ -469,11 +464,10 @@ static int __init mpc52xx_psc_spi_of_probe(struct of_device *op, const u32 *regaddr_p; u64 regaddr64, size64; s16 id = -1; - int rc; regaddr_p = of_get_address(op->node, 0, &size64, NULL); if (!regaddr_p) { - dev_err(&op->dev, "Invalid PSC address\n"); + printk(KERN_ERR "Invalid PSC address\n"); return -EINVAL; } regaddr64 = of_translate_address(op->node, regaddr_p); @@ -484,18 +478,15 @@ static int __init mpc52xx_psc_spi_of_probe(struct of_device *op, psc_nump = of_get_property(op->node, "cell-index", NULL); if (!psc_nump || *psc_nump > 5) { - dev_err(&op->dev, "Invalid cell-index property\n"); + printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid " + "cell-index property\n", op->node->full_name); return -EINVAL; } id = *psc_nump + 1; } - rc = mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, + return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, irq_of_parse_and_map(op->node, 0), id); - if (rc == 0) - of_register_spi_devices(dev_get_drvdata(&op->dev), op->node); - - return rc; } static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op) diff --git a/trunk/drivers/spi/mpc52xx_spi.c b/trunk/drivers/spi/mpc52xx_spi.c deleted file mode 100644 index ef8379b2c172..000000000000 --- a/trunk/drivers/spi/mpc52xx_spi.c +++ /dev/null @@ -1,520 +0,0 @@ -/* - * MPC52xx SPI bus driver. - * - * Copyright (C) 2008 Secret Lab Technologies Ltd. - * - * This file is released under the GPLv2 - * - * This is the driver for the MPC5200's dedicated SPI controller. - * - * Note: this driver does not support the MPC5200 PSC in SPI mode. For - * that driver see drivers/spi/mpc52xx_psc_spi.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -MODULE_AUTHOR("Grant Likely "); -MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver"); -MODULE_LICENSE("GPL"); - -/* Register offsets */ -#define SPI_CTRL1 0x00 -#define SPI_CTRL1_SPIE (1 << 7) -#define SPI_CTRL1_SPE (1 << 6) -#define SPI_CTRL1_MSTR (1 << 4) -#define SPI_CTRL1_CPOL (1 << 3) -#define SPI_CTRL1_CPHA (1 << 2) -#define SPI_CTRL1_SSOE (1 << 1) -#define SPI_CTRL1_LSBFE (1 << 0) - -#define SPI_CTRL2 0x01 -#define SPI_BRR 0x04 - -#define SPI_STATUS 0x05 -#define SPI_STATUS_SPIF (1 << 7) -#define SPI_STATUS_WCOL (1 << 6) -#define SPI_STATUS_MODF (1 << 4) - -#define SPI_DATA 0x09 -#define SPI_PORTDATA 0x0d -#define SPI_DATADIR 0x10 - -/* FSM state return values */ -#define FSM_STOP 0 /* Nothing more for the state machine to */ - /* do. If something interesting happens */ - /* then and IRQ will be received */ -#define FSM_POLL 1 /* need to poll for completion, an IRQ is */ - /* not expected */ -#define FSM_CONTINUE 2 /* Keep iterating the state machine */ - -/* Driver internal data */ -struct mpc52xx_spi { - struct spi_master *master; - u32 sysclk; - void __iomem *regs; - int irq0; /* MODF irq */ - int irq1; /* SPIF irq */ - int ipb_freq; - - /* Statistics */ - int msg_count; - int wcol_count; - int wcol_ticks; - u32 wcol_tx_timestamp; - int modf_count; - int byte_count; - - struct list_head queue; /* queue of pending messages */ - spinlock_t lock; - struct work_struct work; - - - /* Details of current transfer (length, and buffer pointers) */ - struct spi_message *message; /* current message */ - struct spi_transfer *transfer; /* current transfer */ - int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data); - int len; - int timestamp; - u8 *rx_buf; - const u8 *tx_buf; - int cs_change; -}; - -/* - * CS control function - */ -static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) -{ - out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); -} - -/* - * Start a new transfer. This is called both by the idle state - * for the first transfer in a message, and by the wait state when the - * previous transfer in a message is complete. - */ -static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms) -{ - ms->rx_buf = ms->transfer->rx_buf; - ms->tx_buf = ms->transfer->tx_buf; - ms->len = ms->transfer->len; - - /* Activate the chip select */ - if (ms->cs_change) - mpc52xx_spi_chipsel(ms, 1); - ms->cs_change = ms->transfer->cs_change; - - /* Write out the first byte */ - ms->wcol_tx_timestamp = get_tbl(); - if (ms->tx_buf) - out_8(ms->regs + SPI_DATA, *ms->tx_buf++); - else - out_8(ms->regs + SPI_DATA, 0); -} - -/* Forward declaration of state handlers */ -static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, - u8 status, u8 data); -static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, - u8 status, u8 data); - -/* - * IDLE state - * - * No transfers are in progress; if another transfer is pending then retrieve - * it and kick it off. Otherwise, stop processing the state machine - */ -static int -mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) -{ - struct spi_device *spi; - int spr, sppr; - u8 ctrl1; - - if (status && (irq != NO_IRQ)) - dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", - status); - - /* Check if there is another transfer waiting. */ - if (list_empty(&ms->queue)) - return FSM_STOP; - - /* get the head of the queue */ - ms->message = list_first_entry(&ms->queue, struct spi_message, queue); - list_del_init(&ms->message->queue); - - /* Setup the controller parameters */ - ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; - spi = ms->message->spi; - if (spi->mode & SPI_CPHA) - ctrl1 |= SPI_CTRL1_CPHA; - if (spi->mode & SPI_CPOL) - ctrl1 |= SPI_CTRL1_CPOL; - if (spi->mode & SPI_LSB_FIRST) - ctrl1 |= SPI_CTRL1_LSBFE; - out_8(ms->regs + SPI_CTRL1, ctrl1); - - /* Setup the controller speed */ - /* minimum divider is '2'. Also, add '1' to force rounding the - * divider up. */ - sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1; - spr = 0; - if (sppr < 1) - sppr = 1; - while (((sppr - 1) & ~0x7) != 0) { - sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */ - spr++; - } - sppr--; /* sppr quantity in register is offset by 1 */ - if (spr > 7) { - /* Don't overrun limits of SPI baudrate register */ - spr = 7; - sppr = 7; - } - out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ - - ms->cs_change = 1; - ms->transfer = container_of(ms->message->transfers.next, - struct spi_transfer, transfer_list); - - mpc52xx_spi_start_transfer(ms); - ms->state = mpc52xx_spi_fsmstate_transfer; - - return FSM_CONTINUE; -} - -/* - * TRANSFER state - * - * In the middle of a transfer. If the SPI core has completed processing - * a byte, then read out the received data and write out the next byte - * (unless this transfer is finished; in which case go on to the wait - * state) - */ -static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, - u8 status, u8 data) -{ - if (!status) - return ms->irq0 ? FSM_STOP : FSM_POLL; - - if (status & SPI_STATUS_WCOL) { - /* The SPI controller is stoopid. At slower speeds, it may - * raise the SPIF flag before the state machine is actually - * finished, which causes a collision (internal to the state - * machine only). The manual recommends inserting a delay - * between receiving the interrupt and sending the next byte, - * but it can also be worked around simply by retrying the - * transfer which is what we do here. */ - ms->wcol_count++; - ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp; - ms->wcol_tx_timestamp = get_tbl(); - data = 0; - if (ms->tx_buf) - data = *(ms->tx_buf-1); - out_8(ms->regs + SPI_DATA, data); /* try again */ - return FSM_CONTINUE; - } else if (status & SPI_STATUS_MODF) { - ms->modf_count++; - dev_err(&ms->master->dev, "mode fault\n"); - mpc52xx_spi_chipsel(ms, 0); - ms->message->status = -EIO; - ms->message->complete(ms->message->context); - ms->state = mpc52xx_spi_fsmstate_idle; - return FSM_CONTINUE; - } - - /* Read data out of the spi device */ - ms->byte_count++; - if (ms->rx_buf) - *ms->rx_buf++ = data; - - /* Is the transfer complete? */ - ms->len--; - if (ms->len == 0) { - ms->timestamp = get_tbl(); - ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec; - ms->state = mpc52xx_spi_fsmstate_wait; - return FSM_CONTINUE; - } - - /* Write out the next byte */ - ms->wcol_tx_timestamp = get_tbl(); - if (ms->tx_buf) - out_8(ms->regs + SPI_DATA, *ms->tx_buf++); - else - out_8(ms->regs + SPI_DATA, 0); - - return FSM_CONTINUE; -} - -/* - * WAIT state - * - * A transfer has completed; need to wait for the delay period to complete - * before starting the next transfer - */ -static int -mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) -{ - if (status && irq) - dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", - status); - - if (((int)get_tbl()) - ms->timestamp < 0) - return FSM_POLL; - - ms->message->actual_length += ms->transfer->len; - - /* Check if there is another transfer in this message. If there - * aren't then deactivate CS, notify sender, and drop back to idle - * to start the next message. */ - if (ms->transfer->transfer_list.next == &ms->message->transfers) { - ms->msg_count++; - mpc52xx_spi_chipsel(ms, 0); - ms->message->status = 0; - ms->message->complete(ms->message->context); - ms->state = mpc52xx_spi_fsmstate_idle; - return FSM_CONTINUE; - } - - /* There is another transfer; kick it off */ - - if (ms->cs_change) - mpc52xx_spi_chipsel(ms, 0); - - ms->transfer = container_of(ms->transfer->transfer_list.next, - struct spi_transfer, transfer_list); - mpc52xx_spi_start_transfer(ms); - ms->state = mpc52xx_spi_fsmstate_transfer; - return FSM_CONTINUE; -} - -/** - * mpc52xx_spi_fsm_process - Finite State Machine iteration function - * @irq: irq number that triggered the FSM or 0 for polling - * @ms: pointer to mpc52xx_spi driver data - */ -static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms) -{ - int rc = FSM_CONTINUE; - u8 status, data; - - while (rc == FSM_CONTINUE) { - /* Interrupt cleared by read of STATUS followed by - * read of DATA registers */ - status = in_8(ms->regs + SPI_STATUS); - data = in_8(ms->regs + SPI_DATA); - rc = ms->state(irq, ms, status, data); - } - - if (rc == FSM_POLL) - schedule_work(&ms->work); -} - -/** - * mpc52xx_spi_irq - IRQ handler - */ -static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms) -{ - struct mpc52xx_spi *ms = _ms; - spin_lock(&ms->lock); - mpc52xx_spi_fsm_process(irq, ms); - spin_unlock(&ms->lock); - return IRQ_HANDLED; -} - -/** - * mpc52xx_spi_wq - Workqueue function for polling the state machine - */ -static void mpc52xx_spi_wq(struct work_struct *work) -{ - struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work); - unsigned long flags; - - spin_lock_irqsave(&ms->lock, flags); - mpc52xx_spi_fsm_process(0, ms); - spin_unlock_irqrestore(&ms->lock, flags); -} - -/* - * spi_master ops - */ - -static int mpc52xx_spi_setup(struct spi_device *spi) -{ - if (spi->bits_per_word % 8) - return -EINVAL; - - if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) - return -EINVAL; - - if (spi->chip_select >= spi->master->num_chipselect) - return -EINVAL; - - return 0; -} - -static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) -{ - struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); - unsigned long flags; - - m->actual_length = 0; - m->status = -EINPROGRESS; - - spin_lock_irqsave(&ms->lock, flags); - list_add_tail(&m->queue, &ms->queue); - spin_unlock_irqrestore(&ms->lock, flags); - schedule_work(&ms->work); - - return 0; -} - -/* - * OF Platform Bus Binding - */ -static int __devinit mpc52xx_spi_probe(struct of_device *op, - const struct of_device_id *match) -{ - struct spi_master *master; - struct mpc52xx_spi *ms; - void __iomem *regs; - int rc; - - /* MMIO registers */ - dev_dbg(&op->dev, "probing mpc5200 SPI device\n"); - regs = of_iomap(op->node, 0); - if (!regs) - return -ENODEV; - - /* initialize the device */ - out_8(regs+SPI_CTRL1, SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR); - out_8(regs + SPI_CTRL2, 0x0); - out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */ - out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ - - /* Clear the status register and re-read it to check for a MODF - * failure. This driver cannot currently handle multiple masters - * on the SPI bus. This fault will also occur if the SPI signals - * are not connected to any pins (port_config setting) */ - in_8(regs + SPI_STATUS); - in_8(regs + SPI_DATA); - if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) { - dev_err(&op->dev, "mode fault; is port_config correct?\n"); - rc = -EIO; - goto err_init; - } - - dev_dbg(&op->dev, "allocating spi_master struct\n"); - master = spi_alloc_master(&op->dev, sizeof *ms); - if (!master) { - rc = -ENOMEM; - goto err_alloc; - } - master->bus_num = -1; - master->num_chipselect = 1; - master->setup = mpc52xx_spi_setup; - master->transfer = mpc52xx_spi_transfer; - dev_set_drvdata(&op->dev, master); - - ms = spi_master_get_devdata(master); - ms->master = master; - ms->regs = regs; - ms->irq0 = irq_of_parse_and_map(op->node, 0); - ms->irq1 = irq_of_parse_and_map(op->node, 1); - ms->state = mpc52xx_spi_fsmstate_idle; - ms->ipb_freq = mpc5xxx_get_bus_frequency(op->node); - spin_lock_init(&ms->lock); - INIT_LIST_HEAD(&ms->queue); - INIT_WORK(&ms->work, mpc52xx_spi_wq); - - /* Decide if interrupts can be used */ - if (ms->irq0 && ms->irq1) { - rc = request_irq(ms->irq0, mpc52xx_spi_irq, IRQF_SAMPLE_RANDOM, - "mpc5200-spi-modf", ms); - rc |= request_irq(ms->irq1, mpc52xx_spi_irq, IRQF_SAMPLE_RANDOM, - "mpc5200-spi-spiF", ms); - if (rc) { - free_irq(ms->irq0, ms); - free_irq(ms->irq1, ms); - ms->irq0 = ms->irq1 = 0; - } - } else { - /* operate in polled mode */ - ms->irq0 = ms->irq1 = 0; - } - - if (!ms->irq0) - dev_info(&op->dev, "using polled mode\n"); - - dev_dbg(&op->dev, "registering spi_master struct\n"); - rc = spi_register_master(master); - if (rc) - goto err_register; - - of_register_spi_devices(master, op->node); - dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); - - return rc; - - err_register: - dev_err(&ms->master->dev, "initialization failed\n"); - spi_master_put(master); - err_alloc: - err_init: - iounmap(regs); - return rc; -} - -static int __devexit mpc52xx_spi_remove(struct of_device *op) -{ - struct spi_master *master = dev_get_drvdata(&op->dev); - struct mpc52xx_spi *ms = spi_master_get_devdata(master); - - free_irq(ms->irq0, ms); - free_irq(ms->irq1, ms); - - spi_unregister_master(master); - spi_master_put(master); - iounmap(ms->regs); - - return 0; -} - -static struct of_device_id mpc52xx_spi_match[] __devinitdata = { - { .compatible = "fsl,mpc5200-spi", }, - {} -}; -MODULE_DEVICE_TABLE(of, mpc52xx_spi_match); - -static struct of_platform_driver mpc52xx_spi_of_driver = { - .owner = THIS_MODULE, - .name = "mpc52xx-spi", - .match_table = mpc52xx_spi_match, - .probe = mpc52xx_spi_probe, - .remove = __exit_p(mpc52xx_spi_remove), -}; - -static int __init mpc52xx_spi_init(void) -{ - return of_register_platform_driver(&mpc52xx_spi_of_driver); -} -module_init(mpc52xx_spi_init); - -static void __exit mpc52xx_spi_exit(void) -{ - of_unregister_platform_driver(&mpc52xx_spi_of_driver); -} -module_exit(mpc52xx_spi_exit); - diff --git a/trunk/drivers/spi/spi_mpc8xxx.c b/trunk/drivers/spi/spi_mpc8xxx.c index 930135dc73ba..0fd0ec4d3a7d 100644 --- a/trunk/drivers/spi/spi_mpc8xxx.c +++ b/trunk/drivers/spi/spi_mpc8xxx.c @@ -5,10 +5,6 @@ * * Copyright (C) 2006 Polycom, Inc. * - * CPM SPI and QE buffer descriptors mode support: - * Copyright (c) 2009 MontaVista Software, Inc. - * Author: Anton Vorontsov - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -31,9 +27,6 @@ #include #include #include -#include -#include -#include #include #include #include @@ -41,19 +34,8 @@ #include #include -#include -#include #include -/* CPM1 and CPM2 are mutually exclusive. */ -#ifdef CONFIG_CPM1 -#include -#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0) -#else -#include -#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0) -#endif - /* SPI Controller registers */ struct mpc8xxx_spi_reg { u8 res1[0x20]; @@ -65,28 +47,6 @@ struct mpc8xxx_spi_reg { __be32 receive; }; -/* SPI Parameter RAM */ -struct spi_pram { - __be16 rbase; /* Rx Buffer descriptor base address */ - __be16 tbase; /* Tx Buffer descriptor base address */ - u8 rfcr; /* Rx function code */ - u8 tfcr; /* Tx function code */ - __be16 mrblr; /* Max receive buffer length */ - __be32 rstate; /* Internal */ - __be32 rdp; /* Internal */ - __be16 rbptr; /* Internal */ - __be16 rbc; /* Internal */ - __be32 rxtmp; /* Internal */ - __be32 tstate; /* Internal */ - __be32 tdp; /* Internal */ - __be16 tbptr; /* Internal */ - __be16 tbc; /* Internal */ - __be32 txtmp; /* Internal */ - __be32 res; /* Tx temp. */ - __be16 rpbase; /* Relocation pointer (CPM1 only) */ - __be16 res1; /* Reserved */ -}; - /* SPI Controller mode register definitions */ #define SPMODE_LOOP (1 << 30) #define SPMODE_CI_INACTIVEHIGH (1 << 29) @@ -115,40 +75,14 @@ struct spi_pram { #define SPIM_NE 0x00000200 /* Not empty */ #define SPIM_NF 0x00000100 /* Not full */ -#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */ -#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */ - -/* SPCOM register values */ -#define SPCOM_STR (1 << 23) /* Start transmit */ - -#define SPI_PRAM_SIZE 0x100 -#define SPI_MRBLR ((unsigned int)PAGE_SIZE) - /* SPI Controller driver's private data. */ struct mpc8xxx_spi { - struct device *dev; struct mpc8xxx_spi_reg __iomem *base; /* rx & tx bufs from the spi_transfer */ const void *tx; void *rx; - int subblock; - struct spi_pram __iomem *pram; - struct cpm_buf_desc __iomem *tx_bd; - struct cpm_buf_desc __iomem *rx_bd; - - struct spi_transfer *xfer_in_progress; - - /* dma addresses for CPM transfers */ - dma_addr_t tx_dma; - dma_addr_t rx_dma; - bool map_tx_dma; - bool map_rx_dma; - - dma_addr_t dma_dummy_tx; - dma_addr_t dma_dummy_rx; - /* functions to deal with different sized buffers */ void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); u32(*get_tx) (struct mpc8xxx_spi *); @@ -162,7 +96,7 @@ struct mpc8xxx_spi { u32 rx_shift; /* RX data reg shift when in qe mode */ u32 tx_shift; /* TX data reg shift when in qe mode */ - unsigned int flags; + bool qe_mode; struct workqueue_struct *workqueue; struct work_struct work; @@ -173,10 +107,6 @@ struct mpc8xxx_spi { struct completion done; }; -static void *mpc8xxx_dummy_rx; -static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock); -static int mpc8xxx_dummy_rx_refcnt; - struct spi_mpc8xxx_cs { /* functions to deal with different sized buffers */ void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *); @@ -225,42 +155,6 @@ MPC83XX_SPI_TX_BUF(u8) MPC83XX_SPI_TX_BUF(u16) MPC83XX_SPI_TX_BUF(u32) -static void mpc8xxx_spi_change_mode(struct spi_device *spi) -{ - struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); - struct spi_mpc8xxx_cs *cs = spi->controller_state; - __be32 __iomem *mode = &mspi->base->mode; - unsigned long flags; - - if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) - return; - - /* Turn off IRQs locally to minimize time that SPI is disabled. */ - local_irq_save(flags); - - /* Turn off SPI unit prior changing mode */ - mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); - mpc8xxx_spi_write_reg(mode, cs->hw_mode); - - /* When in CPM mode, we need to reinit tx and rx. */ - if (mspi->flags & SPI_CPM_MODE) { - if (mspi->flags & SPI_QE) { - qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock, - QE_CR_PROTOCOL_UNSPECIFIED, 0); - } else { - cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX); - if (mspi->flags & SPI_CPM1) { - out_be16(&mspi->pram->rbptr, - in_be16(&mspi->pram->rbase)); - out_be16(&mspi->pram->tbptr, - in_be16(&mspi->pram->tbase)); - } - } - } - - local_irq_restore(flags); -} - static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value) { struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); @@ -274,13 +168,27 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value) } if (value == BITBANG_CS_ACTIVE) { + u32 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode); + mpc8xxx_spi->rx_shift = cs->rx_shift; mpc8xxx_spi->tx_shift = cs->tx_shift; mpc8xxx_spi->get_rx = cs->get_rx; mpc8xxx_spi->get_tx = cs->get_tx; - mpc8xxx_spi_change_mode(spi); - + if (cs->hw_mode != regval) { + unsigned long flags; + __be32 __iomem *mode = &mpc8xxx_spi->base->mode; + + regval = cs->hw_mode; + /* Turn off IRQs locally to minimize time that + * SPI is disabled + */ + local_irq_save(flags); + /* Turn off SPI unit prior changing mode */ + mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE); + mpc8xxx_spi_write_reg(mode, regval); + local_irq_restore(flags); + } if (pdata->cs_control) pdata->cs_control(spi, pol); } @@ -290,6 +198,7 @@ static int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { struct mpc8xxx_spi *mpc8xxx_spi; + u32 regval; u8 bits_per_word, pm; u32 hz; struct spi_mpc8xxx_cs *cs = spi->controller_state; @@ -321,14 +230,14 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) if (bits_per_word <= 8) { cs->get_rx = mpc8xxx_spi_rx_buf_u8; cs->get_tx = mpc8xxx_spi_tx_buf_u8; - if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { + if (mpc8xxx_spi->qe_mode) { cs->rx_shift = 16; cs->tx_shift = 24; } } else if (bits_per_word <= 16) { cs->get_rx = mpc8xxx_spi_rx_buf_u16; cs->get_tx = mpc8xxx_spi_tx_buf_u16; - if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { + if (mpc8xxx_spi->qe_mode) { cs->rx_shift = 16; cs->tx_shift = 16; } @@ -338,8 +247,7 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) } else return -EINVAL; - if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE && - spi->mode & SPI_LSB_FIRST) { + if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) { cs->tx_shift = 0; if (bits_per_word <= 8) cs->rx_shift = 8; @@ -378,138 +286,37 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) pm--; cs->hw_mode |= SPMODE_PM(pm); - - mpc8xxx_spi_change_mode(spi); - return 0; -} - -static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi) -{ - struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd; - struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd; - unsigned int xfer_len = min(mspi->count, SPI_MRBLR); - unsigned int xfer_ofs; - - xfer_ofs = mspi->xfer_in_progress->len - mspi->count; - - out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs); - out_be16(&rx_bd->cbd_datlen, 0); - out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP); - - out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs); - out_be16(&tx_bd->cbd_datlen, xfer_len); - out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP | - BD_SC_LAST); - - /* start transfer */ - mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR); -} - -static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi, - struct spi_transfer *t, bool is_dma_mapped) -{ - struct device *dev = mspi->dev; - - if (is_dma_mapped) { - mspi->map_tx_dma = 0; - mspi->map_rx_dma = 0; - } else { - mspi->map_tx_dma = 1; - mspi->map_rx_dma = 1; - } - - if (!t->tx_buf) { - mspi->tx_dma = mspi->dma_dummy_tx; - mspi->map_tx_dma = 0; - } - - if (!t->rx_buf) { - mspi->rx_dma = mspi->dma_dummy_rx; - mspi->map_rx_dma = 0; - } - - if (mspi->map_tx_dma) { - void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ - - mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, mspi->tx_dma)) { - dev_err(dev, "unable to map tx dma\n"); - return -ENOMEM; - } - } else { - mspi->tx_dma = t->tx_dma; - } - - if (mspi->map_rx_dma) { - mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, mspi->rx_dma)) { - dev_err(dev, "unable to map rx dma\n"); - goto err_rx_dma; - } - } else { - mspi->rx_dma = t->rx_dma; + regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode); + if (cs->hw_mode != regval) { + unsigned long flags; + __be32 __iomem *mode = &mpc8xxx_spi->base->mode; + + regval = cs->hw_mode; + /* Turn off IRQs locally to minimize time + * that SPI is disabled + */ + local_irq_save(flags); + /* Turn off SPI unit prior changing mode */ + mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE); + mpc8xxx_spi_write_reg(mode, regval); + local_irq_restore(flags); } - - /* enable rx ints */ - mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB); - - mspi->xfer_in_progress = t; - mspi->count = t->len; - - /* start CPM transfers */ - mpc8xxx_spi_cpm_bufs_start(mspi); - return 0; - -err_rx_dma: - if (mspi->map_tx_dma) - dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); - return -ENOMEM; } -static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) +static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) { - struct device *dev = mspi->dev; - struct spi_transfer *t = mspi->xfer_in_progress; - - if (mspi->map_tx_dma) - dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); - if (mspi->map_tx_dma) - dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); - mspi->xfer_in_progress = NULL; -} - -static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi, - struct spi_transfer *t, unsigned int len) -{ - u32 word; - - mspi->count = len; - - /* enable rx ints */ - mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE); - - /* transmit word */ - word = mspi->get_tx(mspi); - mpc8xxx_spi_write_reg(&mspi->base->transmit, word); - - return 0; -} + struct mpc8xxx_spi *mpc8xxx_spi; + u32 word, len, bits_per_word; -static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t, - bool is_dma_mapped) -{ - struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); - unsigned int len = t->len; - u8 bits_per_word; - int ret; + mpc8xxx_spi = spi_master_get_devdata(spi->master); + mpc8xxx_spi->tx = t->tx_buf; + mpc8xxx_spi->rx = t->rx_buf; bits_per_word = spi->bits_per_word; if (t->bits_per_word) bits_per_word = t->bits_per_word; - + len = t->len; if (bits_per_word > 8) { /* invalid length? */ if (len & 1) @@ -522,27 +329,22 @@ static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t, return -EINVAL; len /= 2; } - - mpc8xxx_spi->tx = t->tx_buf; - mpc8xxx_spi->rx = t->rx_buf; + mpc8xxx_spi->count = len; INIT_COMPLETION(mpc8xxx_spi->done); - if (mpc8xxx_spi->flags & SPI_CPM_MODE) - ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); - else - ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len); - if (ret) - return ret; + /* enable rx ints */ + mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE); + + /* transmit word */ + word = mpc8xxx_spi->get_tx(mpc8xxx_spi); + mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); wait_for_completion(&mpc8xxx_spi->done); /* disable rx ints */ mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0); - if (mpc8xxx_spi->flags & SPI_CPM_MODE) - mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi); - return mpc8xxx_spi->count; } @@ -573,7 +375,7 @@ static void mpc8xxx_spi_do_one_msg(struct spi_message *m) } cs_change = t->cs_change; if (t->len) - status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped); + status = mpc8xxx_spi_bufs(spi, t); if (status) { status = -EMSGSIZE; break; @@ -662,80 +464,45 @@ static int mpc8xxx_spi_setup(struct spi_device *spi) return 0; } -static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) +static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data) { - u16 len; - - dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__, - in_be16(&mspi->rx_bd->cbd_datlen), mspi->count); - - len = in_be16(&mspi->rx_bd->cbd_datlen); - if (len > mspi->count) { - WARN_ON(1); - len = mspi->count; - } - - /* Clear the events */ - mpc8xxx_spi_write_reg(&mspi->base->event, events); + struct mpc8xxx_spi *mpc8xxx_spi = context_data; + u32 event; + irqreturn_t ret = IRQ_NONE; - mspi->count -= len; - if (mspi->count) - mpc8xxx_spi_cpm_bufs_start(mspi); - else - complete(&mspi->done); -} + /* Get interrupt events(tx/rx) */ + event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event); -static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) -{ /* We need handle RX first */ - if (events & SPIE_NE) { - u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive); + if (event & SPIE_NE) { + u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive); + + if (mpc8xxx_spi->rx) + mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi); - if (mspi->rx) - mspi->get_rx(rx_data, mspi); + ret = IRQ_HANDLED; } - if ((events & SPIE_NF) == 0) + if ((event & SPIE_NF) == 0) /* spin until TX is done */ - while (((events = - mpc8xxx_spi_read_reg(&mspi->base->event)) & + while (((event = + mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) & SPIE_NF) == 0) cpu_relax(); - /* Clear the events */ - mpc8xxx_spi_write_reg(&mspi->base->event, events); - - mspi->count -= 1; - if (mspi->count) { - u32 word = mspi->get_tx(mspi); - - mpc8xxx_spi_write_reg(&mspi->base->transmit, word); + mpc8xxx_spi->count -= 1; + if (mpc8xxx_spi->count) { + u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi); + mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word); } else { - complete(&mspi->done); + complete(&mpc8xxx_spi->done); } -} - -static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data) -{ - struct mpc8xxx_spi *mspi = context_data; - irqreturn_t ret = IRQ_NONE; - u32 events; - - /* Get interrupt events(tx/rx) */ - events = mpc8xxx_spi_read_reg(&mspi->base->event); - if (events) - ret = IRQ_HANDLED; - dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); - - if (mspi->flags & SPI_CPM_MODE) - mpc8xxx_spi_cpm_irq(mspi, events); - else - mpc8xxx_spi_cpu_irq(mspi, events); + /* Clear the events */ + mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event); return ret; } - static int mpc8xxx_spi_transfer(struct spi_device *spi, struct spi_message *m) { @@ -759,215 +526,6 @@ static void mpc8xxx_spi_cleanup(struct spi_device *spi) kfree(spi->controller_state); } -static void *mpc8xxx_spi_alloc_dummy_rx(void) -{ - mutex_lock(&mpc8xxx_dummy_rx_lock); - - if (!mpc8xxx_dummy_rx) - mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL); - if (mpc8xxx_dummy_rx) - mpc8xxx_dummy_rx_refcnt++; - - mutex_unlock(&mpc8xxx_dummy_rx_lock); - - return mpc8xxx_dummy_rx; -} - -static void mpc8xxx_spi_free_dummy_rx(void) -{ - mutex_lock(&mpc8xxx_dummy_rx_lock); - - switch (mpc8xxx_dummy_rx_refcnt) { - case 0: - WARN_ON(1); - break; - case 1: - kfree(mpc8xxx_dummy_rx); - mpc8xxx_dummy_rx = NULL; - /* fall through */ - default: - mpc8xxx_dummy_rx_refcnt--; - break; - } - - mutex_unlock(&mpc8xxx_dummy_rx_lock); -} - -static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi) -{ - struct device *dev = mspi->dev; - struct device_node *np = dev_archdata_get_node(&dev->archdata); - const u32 *iprop; - int size; - unsigned long spi_base_ofs; - unsigned long pram_ofs = -ENOMEM; - - /* Can't use of_address_to_resource(), QE muram isn't at 0. */ - iprop = of_get_property(np, "reg", &size); - - /* QE with a fixed pram location? */ - if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4) - return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE); - - /* QE but with a dynamic pram location? */ - if (mspi->flags & SPI_QE) { - pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); - qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock, - QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs); - return pram_ofs; - } - - /* CPM1 and CPM2 pram must be at a fixed addr. */ - if (!iprop || size != sizeof(*iprop) * 4) - return -ENOMEM; - - spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2); - if (IS_ERR_VALUE(spi_base_ofs)) - return -ENOMEM; - - if (mspi->flags & SPI_CPM2) { - pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); - if (!IS_ERR_VALUE(pram_ofs)) { - u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs); - - out_be16(spi_base, pram_ofs); - } - } else { - struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs); - u16 rpbase = in_be16(&pram->rpbase); - - /* Microcode relocation patch applied? */ - if (rpbase) - pram_ofs = rpbase; - else - return spi_base_ofs; - } - - cpm_muram_free(spi_base_ofs); - return pram_ofs; -} - -static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi) -{ - struct device *dev = mspi->dev; - struct device_node *np = dev_archdata_get_node(&dev->archdata); - const u32 *iprop; - int size; - unsigned long pram_ofs; - unsigned long bds_ofs; - - if (!(mspi->flags & SPI_CPM_MODE)) - return 0; - - if (!mpc8xxx_spi_alloc_dummy_rx()) - return -ENOMEM; - - if (mspi->flags & SPI_QE) { - iprop = of_get_property(np, "cell-index", &size); - if (iprop && size == sizeof(*iprop)) - mspi->subblock = *iprop; - - switch (mspi->subblock) { - default: - dev_warn(dev, "cell-index unspecified, assuming SPI1"); - /* fall through */ - case 0: - mspi->subblock = QE_CR_SUBBLOCK_SPI1; - break; - case 1: - mspi->subblock = QE_CR_SUBBLOCK_SPI2; - break; - } - } - - pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi); - if (IS_ERR_VALUE(pram_ofs)) { - dev_err(dev, "can't allocate spi parameter ram\n"); - goto err_pram; - } - - bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) + - sizeof(*mspi->rx_bd), 8); - if (IS_ERR_VALUE(bds_ofs)) { - dev_err(dev, "can't allocate bds\n"); - goto err_bds; - } - - mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, mspi->dma_dummy_tx)) { - dev_err(dev, "unable to map dummy tx buffer\n"); - goto err_dummy_tx; - } - - mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR, - DMA_FROM_DEVICE); - if (dma_mapping_error(dev, mspi->dma_dummy_rx)) { - dev_err(dev, "unable to map dummy rx buffer\n"); - goto err_dummy_rx; - } - - mspi->pram = cpm_muram_addr(pram_ofs); - - mspi->tx_bd = cpm_muram_addr(bds_ofs); - mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd)); - - /* Initialize parameter ram. */ - out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd)); - out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd)); - out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL); - out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL); - out_be16(&mspi->pram->mrblr, SPI_MRBLR); - out_be32(&mspi->pram->rstate, 0); - out_be32(&mspi->pram->rdp, 0); - out_be16(&mspi->pram->rbptr, 0); - out_be16(&mspi->pram->rbc, 0); - out_be32(&mspi->pram->rxtmp, 0); - out_be32(&mspi->pram->tstate, 0); - out_be32(&mspi->pram->tdp, 0); - out_be16(&mspi->pram->tbptr, 0); - out_be16(&mspi->pram->tbc, 0); - out_be32(&mspi->pram->txtmp, 0); - - return 0; - -err_dummy_rx: - dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); -err_dummy_tx: - cpm_muram_free(bds_ofs); -err_bds: - cpm_muram_free(pram_ofs); -err_pram: - mpc8xxx_spi_free_dummy_rx(); - return -ENOMEM; -} - -static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi) -{ - struct device *dev = mspi->dev; - - dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE); - dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); - cpm_muram_free(cpm_muram_offset(mspi->tx_bd)); - cpm_muram_free(cpm_muram_offset(mspi->pram)); - mpc8xxx_spi_free_dummy_rx(); -} - -static const char *mpc8xxx_spi_strmode(unsigned int flags) -{ - if (flags & SPI_QE_CPU_MODE) { - return "QE CPU"; - } else if (flags & SPI_CPM_MODE) { - if (flags & SPI_QE) - return "QE"; - else if (flags & SPI_CPM2) - return "CPM2"; - else - return "CPM1"; - } - return "CPU"; -} - static struct spi_master * __devinit mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) { @@ -994,19 +552,14 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) master->cleanup = mpc8xxx_spi_cleanup; mpc8xxx_spi = spi_master_get_devdata(master); - mpc8xxx_spi->dev = dev; + mpc8xxx_spi->qe_mode = pdata->qe_mode; mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; - mpc8xxx_spi->flags = pdata->flags; mpc8xxx_spi->spibrg = pdata->sysclk; - ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi); - if (ret) - goto err_cpm_init; - mpc8xxx_spi->rx_shift = 0; mpc8xxx_spi->tx_shift = 0; - if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { + if (mpc8xxx_spi->qe_mode) { mpc8xxx_spi->rx_shift = 16; mpc8xxx_spi->tx_shift = 24; } @@ -1016,7 +569,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1); if (mpc8xxx_spi->base == NULL) { ret = -ENOMEM; - goto err_ioremap; + goto put_master; } mpc8xxx_spi->irq = irq; @@ -1039,7 +592,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) /* Enable SPI interface */ regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; - if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) + if (pdata->qe_mode) regval |= SPMODE_OP; mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval); @@ -1059,8 +612,9 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) if (ret < 0) goto unreg_master; - dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base, - mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); + printk(KERN_INFO + "%s: MPC8xxx SPI Controller driver at 0x%p (irq = %d)\n", + dev_name(dev), mpc8xxx_spi->base, mpc8xxx_spi->irq); return master; @@ -1070,9 +624,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq) free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); unmap_io: iounmap(mpc8xxx_spi->base); -err_ioremap: - mpc8xxx_spi_cpm_free(mpc8xxx_spi); -err_cpm_init: +put_master: spi_master_put(master); err: return ERR_PTR(ret); @@ -1092,7 +644,6 @@ static int __devexit mpc8xxx_spi_remove(struct device *dev) free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); iounmap(mpc8xxx_spi->base); - mpc8xxx_spi_cpm_free(mpc8xxx_spi); return 0; } @@ -1158,7 +709,6 @@ static int of_mpc8xxx_spi_get_chipselects(struct device *dev) gpio = of_get_gpio_flags(np, i, &flags); if (!gpio_is_valid(gpio)) { dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); - ret = gpio; goto err_loop; } @@ -1254,13 +804,7 @@ static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev, prop = of_get_property(np, "mode", NULL); if (prop && !strcmp(prop, "cpu-qe")) - pdata->flags = SPI_QE_CPU_MODE; - else if (prop && !strcmp(prop, "qe")) - pdata->flags = SPI_CPM_MODE | SPI_QE; - else if (of_device_is_compatible(np, "fsl,cpm2-spi")) - pdata->flags = SPI_CPM_MODE | SPI_CPM2; - else if (of_device_is_compatible(np, "fsl,cpm1-spi")) - pdata->flags = SPI_CPM_MODE | SPI_CPM1; + pdata->qe_mode = 1; ret = of_mpc8xxx_spi_get_chipselects(dev); if (ret) diff --git a/trunk/drivers/spi/xilinx_spi.c b/trunk/drivers/spi/xilinx_spi.c index 5a143b9f6361..46b8c5c2f45e 100644 --- a/trunk/drivers/spi/xilinx_spi.c +++ b/trunk/drivers/spi/xilinx_spi.c @@ -148,8 +148,7 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi, { u8 bits_per_word; - bits_per_word = (t && t->bits_per_word) - ? t->bits_per_word : spi->bits_per_word; + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; if (bits_per_word != 8) { dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", __func__, bits_per_word); diff --git a/trunk/drivers/usb/gadget/fsl_qe_udc.h b/trunk/drivers/usb/gadget/fsl_qe_udc.h index bea5b827bebe..31b2710882e4 100644 --- a/trunk/drivers/usb/gadget/fsl_qe_udc.h +++ b/trunk/drivers/usb/gadget/fsl_qe_udc.h @@ -419,4 +419,19 @@ struct qe_udc { #define CPM_USB_RESTART_TX_OPCODE 0x0b #define CPM_USB_EP_SHIFT 5 +#ifndef CONFIG_CPM +inline int cpm_command(u32 command, u8 opcode) +{ + return -EOPNOTSUPP; +} +#endif + +#ifndef CONFIG_QUICC_ENGINE +inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, + u32 cmd_input) +{ + return -EOPNOTSUPP; +} +#endif + #endif /* __FSL_QE_UDC_H */ diff --git a/trunk/drivers/video/offb.c b/trunk/drivers/video/offb.c index b043ac83c412..4d8c54c23dd7 100644 --- a/trunk/drivers/video/offb.c +++ b/trunk/drivers/video/offb.c @@ -282,17 +282,8 @@ static int offb_set_par(struct fb_info *info) return 0; } -static void offb_destroy(struct fb_info *info) -{ - if (info->screen_base) - iounmap(info->screen_base); - release_mem_region(info->aperture_base, info->aperture_size); - framebuffer_release(info); -} - static struct fb_ops offb_ops = { .owner = THIS_MODULE, - .fb_destroy = offb_destroy, .fb_setcolreg = offb_setcolreg, .fb_set_par = offb_set_par, .fb_blank = offb_blank, @@ -491,14 +482,10 @@ static void __init offb_init_fb(const char *name, const char *full_name, var->sync = 0; var->vmode = FB_VMODE_NONINTERLACED; - /* set offb aperture size for generic probing */ - info->aperture_base = address; - info->aperture_size = fix->smem_len; - info->fbops = &offb_ops; info->screen_base = ioremap(address, fix->smem_len); info->pseudo_palette = (void *) (info + 1); - info->flags = FBINFO_DEFAULT | FBINFO_MISC_FIRMWARE | foreign_endian; + info->flags = FBINFO_DEFAULT | foreign_endian; fb_alloc_cmap(&info->cmap, 256, 0); diff --git a/trunk/drivers/video/omap/lcdc.c b/trunk/drivers/video/omap/lcdc.c index a33483910dc8..b831e1df629e 100644 --- a/trunk/drivers/video/omap/lcdc.c +++ b/trunk/drivers/video/omap/lcdc.c @@ -29,7 +29,6 @@ #include #include -#include #include #include @@ -40,6 +39,38 @@ #define MODULE_NAME "lcdc" +#define OMAP_LCDC_BASE 0xfffec000 +#define OMAP_LCDC_SIZE 256 +#define OMAP_LCDC_IRQ INT_LCD_CTRL + +#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00) +#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04) +#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08) +#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c) +#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10) +#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14) +#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18) +#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c) + +#define OMAP_LCDC_STAT_DONE (1 << 0) +#define OMAP_LCDC_STAT_VSYNC (1 << 1) +#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2) +#define OMAP_LCDC_STAT_ABC (1 << 3) +#define OMAP_LCDC_STAT_LINE_INT (1 << 4) +#define OMAP_LCDC_STAT_FUF (1 << 5) +#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6) + +#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) +#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7) +#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10) + +#define OMAP_LCDC_IRQ_VSYNC (1 << 2) +#define OMAP_LCDC_IRQ_DONE (1 << 3) +#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4) +#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5) +#define OMAP_LCDC_IRQ_LINE (1 << 6) +#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2) + #define MAX_PALETTE_SIZE PAGE_SIZE enum lcdc_load_mode { diff --git a/trunk/drivers/watchdog/Kconfig b/trunk/drivers/watchdog/Kconfig index d958b76430a2..3711b888d482 100644 --- a/trunk/drivers/watchdog/Kconfig +++ b/trunk/drivers/watchdog/Kconfig @@ -861,10 +861,8 @@ config GEF_WDT Watchdog timer found in a number of GE Fanuc single board computers. config MPC5200_WDT - bool "MPC52xx Watchdog Timer" + tristate "MPC5200 Watchdog Timer" depends on PPC_MPC52xx - help - Use General Purpose Timer (GPT) 0 on the MPC5200 as Watchdog. config 8xxx_WDT tristate "MPC8xxx Platform Watchdog Timer" diff --git a/trunk/drivers/watchdog/Makefile b/trunk/drivers/watchdog/Makefile index 89c045dc468e..699199b1baa6 100644 --- a/trunk/drivers/watchdog/Makefile +++ b/trunk/drivers/watchdog/Makefile @@ -118,6 +118,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o # POWERPC Architecture obj-$(CONFIG_GEF_WDT) += gef_wdt.o +obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o obj-$(CONFIG_PIKA_WDT) += pika_wdt.o diff --git a/trunk/drivers/watchdog/mpc5200_wdt.c b/trunk/drivers/watchdog/mpc5200_wdt.c new file mode 100644 index 000000000000..fa9c47ce0ae7 --- /dev/null +++ b/trunk/drivers/watchdog/mpc5200_wdt.c @@ -0,0 +1,293 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define GPT_MODE_WDT (1 << 15) +#define GPT_MODE_CE (1 << 12) +#define GPT_MODE_MS_TIMER (0x4) + + +struct mpc5200_wdt { + unsigned count; /* timer ticks before watchdog kicks in */ + long ipb_freq; + struct miscdevice miscdev; + struct resource mem; + struct mpc52xx_gpt __iomem *regs; + spinlock_t io_lock; +}; + +/* is_active stores wether or not the /dev/watchdog device is opened */ +static unsigned long is_active; + +/* misc devices don't provide a way, to get back to 'dev' or 'miscdev' from + * file operations, which sucks. But there can be max 1 watchdog anyway, so... + */ +static struct mpc5200_wdt *wdt_global; + + +/* helper to calculate timeout in timer counts */ +static void mpc5200_wdt_set_timeout(struct mpc5200_wdt *wdt, int timeout) +{ + /* use biggest prescaler of 64k */ + wdt->count = (wdt->ipb_freq + 0xffff) / 0x10000 * timeout; + + if (wdt->count > 0xffff) + wdt->count = 0xffff; +} +/* return timeout in seconds (calculated from timer count) */ +static int mpc5200_wdt_get_timeout(struct mpc5200_wdt *wdt) +{ + return wdt->count * 0x10000 / wdt->ipb_freq; +} + + +/* watchdog operations */ +static int mpc5200_wdt_start(struct mpc5200_wdt *wdt) +{ + spin_lock(&wdt->io_lock); + /* disable */ + out_be32(&wdt->regs->mode, 0); + /* set timeout, with maximum prescaler */ + out_be32(&wdt->regs->count, 0x0 | wdt->count); + /* enable watchdog */ + out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | + GPT_MODE_MS_TIMER); + spin_unlock(&wdt->io_lock); + + return 0; +} +static int mpc5200_wdt_ping(struct mpc5200_wdt *wdt) +{ + spin_lock(&wdt->io_lock); + /* writing A5 to OCPW resets the watchdog */ + out_be32(&wdt->regs->mode, 0xA5000000 | + (0xffffff & in_be32(&wdt->regs->mode))); + spin_unlock(&wdt->io_lock); + return 0; +} +static int mpc5200_wdt_stop(struct mpc5200_wdt *wdt) +{ + spin_lock(&wdt->io_lock); + /* disable */ + out_be32(&wdt->regs->mode, 0); + spin_unlock(&wdt->io_lock); + return 0; +} + + +/* file operations */ +static ssize_t mpc5200_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + struct mpc5200_wdt *wdt = file->private_data; + mpc5200_wdt_ping(wdt); + return 0; +} +static struct watchdog_info mpc5200_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, + .identity = "mpc5200 watchdog on GPT0", +}; +static long mpc5200_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct mpc5200_wdt *wdt = file->private_data; + int __user *data = (int __user *)arg; + int timeout; + int ret = 0; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user(data, &mpc5200_wdt_info, + sizeof(mpc5200_wdt_info)); + if (ret) + ret = -EFAULT; + break; + + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + ret = put_user(0, data); + break; + + case WDIOC_KEEPALIVE: + mpc5200_wdt_ping(wdt); + break; + + case WDIOC_SETTIMEOUT: + ret = get_user(timeout, data); + if (ret) + break; + mpc5200_wdt_set_timeout(wdt, timeout); + mpc5200_wdt_start(wdt); + /* fall through and return the timeout */ + + case WDIOC_GETTIMEOUT: + timeout = mpc5200_wdt_get_timeout(wdt); + ret = put_user(timeout, data); + break; + + default: + ret = -ENOTTY; + } + return ret; +} + +static int mpc5200_wdt_open(struct inode *inode, struct file *file) +{ + /* /dev/watchdog can only be opened once */ + if (test_and_set_bit(0, &is_active)) + return -EBUSY; + + /* Set and activate the watchdog */ + mpc5200_wdt_set_timeout(wdt_global, 30); + mpc5200_wdt_start(wdt_global); + file->private_data = wdt_global; + return nonseekable_open(inode, file); +} +static int mpc5200_wdt_release(struct inode *inode, struct file *file) +{ +#if WATCHDOG_NOWAYOUT == 0 + struct mpc5200_wdt *wdt = file->private_data; + mpc5200_wdt_stop(wdt); + wdt->count = 0; /* == disabled */ +#endif + clear_bit(0, &is_active); + return 0; +} + +static const struct file_operations mpc5200_wdt_fops = { + .owner = THIS_MODULE, + .write = mpc5200_wdt_write, + .unlocked_ioctl = mpc5200_wdt_ioctl, + .open = mpc5200_wdt_open, + .release = mpc5200_wdt_release, +}; + +/* module operations */ +static int mpc5200_wdt_probe(struct of_device *op, + const struct of_device_id *match) +{ + struct mpc5200_wdt *wdt; + int err; + const void *has_wdt; + int size; + + has_wdt = of_get_property(op->node, "has-wdt", NULL); + if (!has_wdt) + has_wdt = of_get_property(op->node, "fsl,has-wdt", NULL); + if (!has_wdt) + return -ENODEV; + + wdt = kzalloc(sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + wdt->ipb_freq = mpc5xxx_get_bus_frequency(op->node); + + err = of_address_to_resource(op->node, 0, &wdt->mem); + if (err) + goto out_free; + size = wdt->mem.end - wdt->mem.start + 1; + if (!request_mem_region(wdt->mem.start, size, "mpc5200_wdt")) { + err = -ENODEV; + goto out_free; + } + wdt->regs = ioremap(wdt->mem.start, size); + if (!wdt->regs) { + err = -ENODEV; + goto out_release; + } + + dev_set_drvdata(&op->dev, wdt); + spin_lock_init(&wdt->io_lock); + + wdt->miscdev = (struct miscdevice) { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &mpc5200_wdt_fops, + .parent = &op->dev, + }; + wdt_global = wdt; + err = misc_register(&wdt->miscdev); + if (!err) + return 0; + + iounmap(wdt->regs); +out_release: + release_mem_region(wdt->mem.start, size); +out_free: + kfree(wdt); + return err; +} + +static int mpc5200_wdt_remove(struct of_device *op) +{ + struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev); + + mpc5200_wdt_stop(wdt); + misc_deregister(&wdt->miscdev); + iounmap(wdt->regs); + release_mem_region(wdt->mem.start, wdt->mem.end - wdt->mem.start + 1); + kfree(wdt); + + return 0; +} +static int mpc5200_wdt_suspend(struct of_device *op, pm_message_t state) +{ + struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev); + mpc5200_wdt_stop(wdt); + return 0; +} +static int mpc5200_wdt_resume(struct of_device *op) +{ + struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev); + if (wdt->count) + mpc5200_wdt_start(wdt); + return 0; +} +static int mpc5200_wdt_shutdown(struct of_device *op) +{ + struct mpc5200_wdt *wdt = dev_get_drvdata(&op->dev); + mpc5200_wdt_stop(wdt); + return 0; +} + +static struct of_device_id mpc5200_wdt_match[] = { + { .compatible = "mpc5200-gpt", }, + { .compatible = "fsl,mpc5200-gpt", }, + {}, +}; +static struct of_platform_driver mpc5200_wdt_driver = { + .owner = THIS_MODULE, + .name = "mpc5200-gpt-wdt", + .match_table = mpc5200_wdt_match, + .probe = mpc5200_wdt_probe, + .remove = mpc5200_wdt_remove, + .suspend = mpc5200_wdt_suspend, + .resume = mpc5200_wdt_resume, + .shutdown = mpc5200_wdt_shutdown, +}; + + +static int __init mpc5200_wdt_init(void) +{ + return of_register_platform_driver(&mpc5200_wdt_driver); +} + +static void __exit mpc5200_wdt_exit(void) +{ + of_unregister_platform_driver(&mpc5200_wdt_driver); +} + +module_init(mpc5200_wdt_init); +module_exit(mpc5200_wdt_exit); + +MODULE_AUTHOR("Domen Puncer "); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/trunk/fs/proc/proc_devtree.c b/trunk/fs/proc/proc_devtree.c index 123257bb356b..7ba79a54948c 100644 --- a/trunk/fs/proc/proc_devtree.c +++ b/trunk/fs/proc/proc_devtree.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -26,27 +25,26 @@ static struct proc_dir_entry *proc_device_tree; /* * Supply data on a read from /proc/device-tree/node/property. */ -static int property_proc_show(struct seq_file *m, void *v) +static int property_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) { - struct property *pp = m->private; + struct property *pp = data; + int n; - seq_write(m, pp->value, pp->length); - return 0; -} - -static int property_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, property_proc_show, PDE(inode)->data); + if (off >= pp->length) { + *eof = 1; + return 0; + } + n = pp->length - off; + if (n > count) + n = count; + else + *eof = 1; + memcpy(page, (char *)pp->value + off, n); + *start = page; + return n; } -static const struct file_operations property_proc_fops = { - .owner = THIS_MODULE, - .open = property_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - /* * For a node with a name like "gc@10", we make symlinks called "gc" * and "@10" to it. @@ -65,9 +63,10 @@ __proc_device_tree_add_prop(struct proc_dir_entry *de, struct property *pp, * Unfortunately proc_register puts each new entry * at the beginning of the list. So we rearrange them. */ - ent = proc_create_data(name, - strncmp(name, "security-", 9) ? S_IRUGO : S_IRUSR, - de, &property_proc_fops, pp); + ent = create_proc_read_entry(name, + strncmp(name, "security-", 9) + ? S_IRUGO : S_IRUSR, de, + property_read_proc, pp); if (ent == NULL) return NULL; diff --git a/trunk/include/linux/cpu.h b/trunk/include/linux/cpu.h index e287863ac053..47536197ffdd 100644 --- a/trunk/include/linux/cpu.h +++ b/trunk/include/linux/cpu.h @@ -43,8 +43,6 @@ extern int sched_create_sysfs_power_savings_entries(struct sysdev_class *cls); #ifdef CONFIG_HOTPLUG_CPU extern void unregister_cpu(struct cpu *cpu); -extern ssize_t arch_cpu_probe(const char *, size_t); -extern ssize_t arch_cpu_release(const char *, size_t); #endif struct notifier_block; @@ -117,19 +115,6 @@ extern void put_online_cpus(void); #define unregister_hotcpu_notifier(nb) unregister_cpu_notifier(nb) int cpu_down(unsigned int cpu); -#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE -extern void cpu_hotplug_driver_lock(void); -extern void cpu_hotplug_driver_unlock(void); -#else -static inline void cpu_hotplug_driver_lock(void) -{ -} - -static inline void cpu_hotplug_driver_unlock(void) -{ -} -#endif - #else /* CONFIG_HOTPLUG_CPU */ #define get_online_cpus() do { } while (0) diff --git a/trunk/include/linux/cpumask.h b/trunk/include/linux/cpumask.h index d77b54733c5b..789cf5f920ce 100644 --- a/trunk/include/linux/cpumask.h +++ b/trunk/include/linux/cpumask.h @@ -84,7 +84,6 @@ extern const struct cpumask *const cpu_active_mask; #define num_online_cpus() cpumask_weight(cpu_online_mask) #define num_possible_cpus() cpumask_weight(cpu_possible_mask) #define num_present_cpus() cpumask_weight(cpu_present_mask) -#define num_active_cpus() cpumask_weight(cpu_active_mask) #define cpu_online(cpu) cpumask_test_cpu((cpu), cpu_online_mask) #define cpu_possible(cpu) cpumask_test_cpu((cpu), cpu_possible_mask) #define cpu_present(cpu) cpumask_test_cpu((cpu), cpu_present_mask) @@ -93,7 +92,6 @@ extern const struct cpumask *const cpu_active_mask; #define num_online_cpus() 1 #define num_possible_cpus() 1 #define num_present_cpus() 1 -#define num_active_cpus() 1 #define cpu_online(cpu) ((cpu) == 0) #define cpu_possible(cpu) ((cpu) == 0) #define cpu_present(cpu) ((cpu) == 0) diff --git a/trunk/include/linux/fsl_devices.h b/trunk/include/linux/fsl_devices.h index 28e33fea5107..43fc95d822d5 100644 --- a/trunk/include/linux/fsl_devices.h +++ b/trunk/include/linux/fsl_devices.h @@ -74,12 +74,7 @@ struct spi_device; struct fsl_spi_platform_data { u32 initial_spmode; /* initial SPMODE value */ s16 bus_num; - unsigned int flags; -#define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */ -#define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */ -#define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */ -#define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */ -#define SPI_QE (1 << 4) /* SPI unit is in QE block */ + bool qe_mode; /* board specific information */ u16 max_chipselect; void (*cs_control)(struct spi_device *spi, bool on); @@ -95,10 +90,6 @@ struct mpc8xx_pcmcia_ops { * lead to a deep sleep (i.e. power removed from the core, * instead of just the clock). */ -#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND) int fsl_deep_sleep(void); -#else -static inline int fsl_deep_sleep(void) { return 0; } -#endif #endif /* _FSL_DEVICE_H_ */ diff --git a/trunk/include/linux/kvm.h b/trunk/include/linux/kvm.h index a24de0b1858e..2d241da07236 100644 --- a/trunk/include/linux/kvm.h +++ b/trunk/include/linux/kvm.h @@ -496,7 +496,6 @@ struct kvm_ioeventfd { #define KVM_CAP_VCPU_EVENTS 41 #endif #define KVM_CAP_S390_PSW 42 -#define KVM_CAP_PPC_SEGSTATE 43 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/trunk/include/linux/pci_ids.h b/trunk/include/linux/pci_ids.h index cca8a044e2b6..eae1f864c934 100644 --- a/trunk/include/linux/pci_ids.h +++ b/trunk/include/linux/pci_ids.h @@ -2295,20 +2295,6 @@ #define PCI_DEVICE_ID_MPC8536 0x0051 #define PCI_DEVICE_ID_P2020E 0x0070 #define PCI_DEVICE_ID_P2020 0x0071 -#define PCI_DEVICE_ID_P2010E 0x0078 -#define PCI_DEVICE_ID_P2010 0x0079 -#define PCI_DEVICE_ID_P1020E 0x0100 -#define PCI_DEVICE_ID_P1020 0x0101 -#define PCI_DEVICE_ID_P1011E 0x0108 -#define PCI_DEVICE_ID_P1011 0x0109 -#define PCI_DEVICE_ID_P1022E 0x0110 -#define PCI_DEVICE_ID_P1022 0x0111 -#define PCI_DEVICE_ID_P1013E 0x0118 -#define PCI_DEVICE_ID_P1013 0x0119 -#define PCI_DEVICE_ID_P4080E 0x0400 -#define PCI_DEVICE_ID_P4080 0x0401 -#define PCI_DEVICE_ID_P4040E 0x0408 -#define PCI_DEVICE_ID_P4040 0x0409 #define PCI_DEVICE_ID_MPC8641 0x7010 #define PCI_DEVICE_ID_MPC8641D 0x7011 #define PCI_DEVICE_ID_MPC8610 0x7018 diff --git a/trunk/include/linux/sched.h b/trunk/include/linux/sched.h index 294eb2f80144..3f4fa73b512a 100644 --- a/trunk/include/linux/sched.h +++ b/trunk/include/linux/sched.h @@ -1102,7 +1102,7 @@ struct sched_class { void (*set_curr_task) (struct rq *rq); void (*task_tick) (struct rq *rq, struct task_struct *p, int queued); - void (*task_fork) (struct task_struct *p); + void (*task_new) (struct rq *rq, struct task_struct *p); void (*switched_from) (struct rq *this_rq, struct task_struct *task, int running); @@ -1111,8 +1111,7 @@ struct sched_class { void (*prio_changed) (struct rq *this_rq, struct task_struct *task, int oldprio, int running); - unsigned int (*get_rr_interval) (struct rq *rq, - struct task_struct *task); + unsigned int (*get_rr_interval) (struct task_struct *task); #ifdef CONFIG_FAIR_GROUP_SCHED void (*moved_group) (struct task_struct *p); @@ -1152,6 +1151,8 @@ struct sched_entity { u64 start_runtime; u64 avg_wakeup; + u64 avg_running; + #ifdef CONFIG_SCHEDSTATS u64 wait_start; u64 wait_max; @@ -1174,6 +1175,7 @@ struct sched_entity { u64 nr_failed_migrations_running; u64 nr_failed_migrations_hot; u64 nr_forced_migrations; + u64 nr_forced2_migrations; u64 nr_wakeups; u64 nr_wakeups_sync; @@ -1902,22 +1904,14 @@ extern unsigned int sysctl_sched_wakeup_granularity; extern unsigned int sysctl_sched_shares_ratelimit; extern unsigned int sysctl_sched_shares_thresh; extern unsigned int sysctl_sched_child_runs_first; - -enum sched_tunable_scaling { - SCHED_TUNABLESCALING_NONE, - SCHED_TUNABLESCALING_LOG, - SCHED_TUNABLESCALING_LINEAR, - SCHED_TUNABLESCALING_END, -}; -extern enum sched_tunable_scaling sysctl_sched_tunable_scaling; - #ifdef CONFIG_SCHED_DEBUG +extern unsigned int sysctl_sched_features; extern unsigned int sysctl_sched_migration_cost; extern unsigned int sysctl_sched_nr_migrate; extern unsigned int sysctl_sched_time_avg; extern unsigned int sysctl_timer_migration; -int sched_proc_update_handler(struct ctl_table *table, int write, +int sched_nr_latency_handler(struct ctl_table *table, int write, void __user *buffer, size_t *length, loff_t *ppos); #endif diff --git a/trunk/include/linux/spi/mpc52xx_spi.h b/trunk/include/linux/spi/mpc52xx_spi.h deleted file mode 100644 index d1004cf09241..000000000000 --- a/trunk/include/linux/spi/mpc52xx_spi.h +++ /dev/null @@ -1,10 +0,0 @@ - -#ifndef INCLUDE_MPC5200_SPI_H -#define INCLUDE_MPC5200_SPI_H - -extern void mpc52xx_spi_set_premessage_hook(struct spi_master *master, - void (*hook)(struct spi_message *m, - void *context), - void *hook_context); - -#endif diff --git a/trunk/kernel/cpu.c b/trunk/kernel/cpu.c index 291ac586f37f..7c4e2713df0a 100644 --- a/trunk/kernel/cpu.c +++ b/trunk/kernel/cpu.c @@ -212,8 +212,6 @@ static int __ref _cpu_down(unsigned int cpu, int tasks_frozen) err = __raw_notifier_call_chain(&cpu_chain, CPU_DOWN_PREPARE | mod, hcpu, -1, &nr_calls); if (err == NOTIFY_BAD) { - set_cpu_active(cpu, true); - nr_calls--; __raw_notifier_call_chain(&cpu_chain, CPU_DOWN_FAILED | mod, hcpu, nr_calls, NULL); @@ -225,11 +223,11 @@ static int __ref _cpu_down(unsigned int cpu, int tasks_frozen) /* Ensure that we are not runnable on dying cpu */ cpumask_copy(old_allowed, ¤t->cpus_allowed); - set_cpus_allowed_ptr(current, cpu_active_mask); + set_cpus_allowed_ptr(current, + cpumask_of(cpumask_any_but(cpu_online_mask, cpu))); err = __stop_machine(take_cpu_down, &tcd_param, cpumask_of(cpu)); if (err) { - set_cpu_active(cpu, true); /* CPU didn't die: tell everyone. Can't complain. */ if (raw_notifier_call_chain(&cpu_chain, CPU_DOWN_FAILED | mod, hcpu) == NOTIFY_BAD) @@ -294,6 +292,9 @@ int __ref cpu_down(unsigned int cpu) err = _cpu_down(cpu, 0); + if (cpu_online(cpu)) + set_cpu_active(cpu, true); + out: cpu_maps_update_done(); stop_machine_destroy(); @@ -386,15 +387,6 @@ int disable_nonboot_cpus(void) * with the userspace trying to use the CPU hotplug at the same time */ cpumask_clear(frozen_cpus); - - for_each_online_cpu(cpu) { - if (cpu == first_cpu) - continue; - set_cpu_active(cpu, false); - } - - synchronize_sched(); - printk("Disabling non-boot CPUs ...\n"); for_each_online_cpu(cpu) { if (cpu == first_cpu) diff --git a/trunk/kernel/cpuset.c b/trunk/kernel/cpuset.c index ba401fab459f..3cf2183b472d 100644 --- a/trunk/kernel/cpuset.c +++ b/trunk/kernel/cpuset.c @@ -737,7 +737,7 @@ static void do_rebuild_sched_domains(struct work_struct *unused) { } -static int generate_sched_domains(cpumask_var_t **domains, +static int generate_sched_domains(struct cpumask **domains, struct sched_domain_attr **attributes) { *domains = NULL; @@ -872,7 +872,7 @@ static int update_cpumask(struct cpuset *cs, struct cpuset *trialcs, if (retval < 0) return retval; - if (!cpumask_subset(trialcs->cpus_allowed, cpu_active_mask)) + if (!cpumask_subset(trialcs->cpus_allowed, cpu_online_mask)) return -EINVAL; } retval = validate_change(cs, trialcs); @@ -2010,7 +2010,7 @@ static void scan_for_empty_cpusets(struct cpuset *root) } /* Continue past cpusets with all cpus, mems online */ - if (cpumask_subset(cp->cpus_allowed, cpu_active_mask) && + if (cpumask_subset(cp->cpus_allowed, cpu_online_mask) && nodes_subset(cp->mems_allowed, node_states[N_HIGH_MEMORY])) continue; @@ -2019,7 +2019,7 @@ static void scan_for_empty_cpusets(struct cpuset *root) /* Remove offline cpus and mems from this cpuset. */ mutex_lock(&callback_mutex); cpumask_and(cp->cpus_allowed, cp->cpus_allowed, - cpu_active_mask); + cpu_online_mask); nodes_and(cp->mems_allowed, cp->mems_allowed, node_states[N_HIGH_MEMORY]); mutex_unlock(&callback_mutex); @@ -2057,10 +2057,8 @@ static int cpuset_track_online_cpus(struct notifier_block *unused_nb, switch (phase) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: - case CPU_DOWN_PREPARE: - case CPU_DOWN_PREPARE_FROZEN: - case CPU_DOWN_FAILED: - case CPU_DOWN_FAILED_FROZEN: + case CPU_DEAD: + case CPU_DEAD_FROZEN: break; default: @@ -2069,7 +2067,7 @@ static int cpuset_track_online_cpus(struct notifier_block *unused_nb, cgroup_lock(); mutex_lock(&callback_mutex); - cpumask_copy(top_cpuset.cpus_allowed, cpu_active_mask); + cpumask_copy(top_cpuset.cpus_allowed, cpu_online_mask); mutex_unlock(&callback_mutex); scan_for_empty_cpusets(&top_cpuset); ndoms = generate_sched_domains(&doms, &attr); @@ -2116,7 +2114,7 @@ static int cpuset_track_online_nodes(struct notifier_block *self, void __init cpuset_init_smp(void) { - cpumask_copy(top_cpuset.cpus_allowed, cpu_active_mask); + cpumask_copy(top_cpuset.cpus_allowed, cpu_online_mask); top_cpuset.mems_allowed = node_states[N_HIGH_MEMORY]; hotcpu_notifier(cpuset_track_online_cpus, 0); diff --git a/trunk/kernel/sched.c b/trunk/kernel/sched.c index ff39cadf621e..e7f2cfa6a257 100644 --- a/trunk/kernel/sched.c +++ b/trunk/kernel/sched.c @@ -814,7 +814,6 @@ const_debug unsigned int sysctl_sched_nr_migrate = 32; * default: 0.25ms */ unsigned int sysctl_sched_shares_ratelimit = 250000; -unsigned int normalized_sysctl_sched_shares_ratelimit = 250000; /* * Inject some fuzzyness into changing the per-cpu group shares @@ -1615,7 +1614,7 @@ static void update_group_shares_cpu(struct task_group *tg, int cpu, */ static int tg_shares_up(struct task_group *tg, void *data) { - unsigned long weight, rq_weight = 0, sum_weight = 0, shares = 0; + unsigned long weight, rq_weight = 0, shares = 0; unsigned long *usd_rq_weight; struct sched_domain *sd = data; unsigned long flags; @@ -1631,7 +1630,6 @@ static int tg_shares_up(struct task_group *tg, void *data) weight = tg->cfs_rq[i]->load.weight; usd_rq_weight[i] = weight; - rq_weight += weight; /* * If there are currently no tasks on the cpu pretend there * is one of average load so that when a new task gets to @@ -1640,13 +1638,10 @@ static int tg_shares_up(struct task_group *tg, void *data) if (!weight) weight = NICE_0_LOAD; - sum_weight += weight; + rq_weight += weight; shares += tg->cfs_rq[i]->shares; } - if (!rq_weight) - rq_weight = sum_weight; - if ((!shares && rq_weight) || shares > tg->shares) shares = tg->shares; @@ -1815,22 +1810,6 @@ static void cfs_rq_set_shares(struct cfs_rq *cfs_rq, unsigned long shares) #endif static void calc_load_account_active(struct rq *this_rq); -static void update_sysctl(void); -static int get_update_sysctl_factor(void); - -static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu) -{ - set_task_rq(p, cpu); -#ifdef CONFIG_SMP - /* - * After ->cpu is set up to a new value, task_rq_lock(p, ...) can be - * successfuly executed on another CPU. We must ensure that updates of - * per-task data have been completed by this moment. - */ - smp_wmb(); - task_thread_info(p)->cpu = cpu; -#endif -} #include "sched_stats.h" #include "sched_idletask.c" @@ -1988,6 +1967,20 @@ inline int task_curr(const struct task_struct *p) return cpu_curr(task_cpu(p)) == p; } +static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu) +{ + set_task_rq(p, cpu); +#ifdef CONFIG_SMP + /* + * After ->cpu is set up to a new value, task_rq_lock(p, ...) can be + * successfuly executed on another CPU. We must ensure that updates of + * per-task data have been completed by this moment. + */ + smp_wmb(); + task_thread_info(p)->cpu = cpu; +#endif +} + static inline void check_class_changed(struct rq *rq, struct task_struct *p, const struct sched_class *prev_class, int oldprio, int running) @@ -2067,13 +2060,29 @@ task_hot(struct task_struct *p, u64 now, struct sched_domain *sd) void set_task_cpu(struct task_struct *p, unsigned int new_cpu) { int old_cpu = task_cpu(p); + struct rq *old_rq = cpu_rq(old_cpu), *new_rq = cpu_rq(new_cpu); struct cfs_rq *old_cfsrq = task_cfs_rq(p), *new_cfsrq = cpu_cfs_rq(old_cfsrq, new_cpu); + u64 clock_offset; + + clock_offset = old_rq->clock - new_rq->clock; trace_sched_migrate_task(p, new_cpu); +#ifdef CONFIG_SCHEDSTATS + if (p->se.wait_start) + p->se.wait_start -= clock_offset; + if (p->se.sleep_start) + p->se.sleep_start -= clock_offset; + if (p->se.block_start) + p->se.block_start -= clock_offset; +#endif if (old_cpu != new_cpu) { p->se.nr_migrations++; +#ifdef CONFIG_SCHEDSTATS + if (task_hot(p, old_rq->clock, NULL)) + schedstat_inc(p, se.nr_forced2_migrations); +#endif perf_sw_event(PERF_COUNT_SW_CPU_MIGRATIONS, 1, 1, NULL, 0); } @@ -2314,14 +2323,6 @@ void task_oncpu_function_call(struct task_struct *p, preempt_enable(); } -#ifdef CONFIG_SMP -static inline -int select_task_rq(struct task_struct *p, int sd_flags, int wake_flags) -{ - return p->sched_class->select_task_rq(p, sd_flags, wake_flags); -} -#endif - /*** * try_to_wake_up - wake up a thread * @p: the to-be-woken-up thread @@ -2373,14 +2374,17 @@ static int try_to_wake_up(struct task_struct *p, unsigned int state, if (task_contributes_to_load(p)) rq->nr_uninterruptible--; p->state = TASK_WAKING; - __task_rq_unlock(rq); + task_rq_unlock(rq, &flags); - cpu = select_task_rq(p, SD_BALANCE_WAKE, wake_flags); - if (cpu != orig_cpu) + cpu = p->sched_class->select_task_rq(p, SD_BALANCE_WAKE, wake_flags); + if (cpu != orig_cpu) { + local_irq_save(flags); + rq = cpu_rq(cpu); + update_rq_clock(rq); set_task_cpu(p, cpu); - - rq = __task_rq_lock(p); - update_rq_clock(rq); + local_irq_restore(flags); + } + rq = task_rq_lock(p, &flags); WARN_ON(p->state != TASK_WAKING); cpu = task_cpu(p); @@ -2495,6 +2499,7 @@ static void __sched_fork(struct task_struct *p) p->se.avg_overlap = 0; p->se.start_runtime = 0; p->se.avg_wakeup = sysctl_sched_wakeup_granularity; + p->se.avg_running = 0; #ifdef CONFIG_SCHEDSTATS p->se.wait_start = 0; @@ -2516,6 +2521,7 @@ static void __sched_fork(struct task_struct *p) p->se.nr_failed_migrations_running = 0; p->se.nr_failed_migrations_hot = 0; p->se.nr_forced_migrations = 0; + p->se.nr_forced2_migrations = 0; p->se.nr_wakeups = 0; p->se.nr_wakeups_sync = 0; @@ -2552,6 +2558,7 @@ static void __sched_fork(struct task_struct *p) void sched_fork(struct task_struct *p, int clone_flags) { int cpu = get_cpu(); + unsigned long flags; __sched_fork(p); @@ -2585,13 +2592,13 @@ void sched_fork(struct task_struct *p, int clone_flags) if (!rt_prio(p->prio)) p->sched_class = &fair_sched_class; - if (p->sched_class->task_fork) - p->sched_class->task_fork(p); - #ifdef CONFIG_SMP - cpu = select_task_rq(p, SD_BALANCE_FORK, 0); + cpu = p->sched_class->select_task_rq(p, SD_BALANCE_FORK, 0); #endif + local_irq_save(flags); + update_rq_clock(cpu_rq(cpu)); set_task_cpu(p, cpu); + local_irq_restore(flags); #if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) if (likely(sched_info_on())) @@ -2624,7 +2631,17 @@ void wake_up_new_task(struct task_struct *p, unsigned long clone_flags) rq = task_rq_lock(p, &flags); BUG_ON(p->state != TASK_RUNNING); update_rq_clock(rq); - activate_task(rq, p, 0); + + if (!p->sched_class->task_new || !current->se.on_rq) { + activate_task(rq, p, 0); + } else { + /* + * Let the scheduling class do new task startup + * management (if any): + */ + p->sched_class->task_new(rq, p); + inc_nr_running(rq); + } trace_sched_wakeup_new(rq, p, 1); check_preempt_curr(rq, p, WF_FORK); #ifdef CONFIG_SMP @@ -3139,7 +3156,7 @@ static void sched_migrate_task(struct task_struct *p, int dest_cpu) void sched_exec(void) { int new_cpu, this_cpu = get_cpu(); - new_cpu = select_task_rq(current, SD_BALANCE_EXEC, 0); + new_cpu = current->sched_class->select_task_rq(current, SD_BALANCE_EXEC, 0); put_cpu(); if (new_cpu != this_cpu) sched_migrate_task(current, new_cpu); @@ -3155,6 +3172,10 @@ static void pull_task(struct rq *src_rq, struct task_struct *p, deactivate_task(src_rq, p, 0); set_task_cpu(p, this_cpu); activate_task(this_rq, p, 0); + /* + * Note that idle threads have a prio of MAX_PRIO, for this test + * to be always true for them. + */ check_preempt_curr(this_rq, p, 0); } @@ -4113,7 +4134,7 @@ static int load_balance(int this_cpu, struct rq *this_rq, unsigned long flags; struct cpumask *cpus = __get_cpu_var(load_balance_tmpmask); - cpumask_copy(cpus, cpu_active_mask); + cpumask_copy(cpus, cpu_online_mask); /* * When power savings policy is enabled for the parent domain, idle @@ -4276,7 +4297,7 @@ load_balance_newidle(int this_cpu, struct rq *this_rq, struct sched_domain *sd) int all_pinned = 0; struct cpumask *cpus = __get_cpu_var(load_balance_tmpmask); - cpumask_copy(cpus, cpu_active_mask); + cpumask_copy(cpus, cpu_online_mask); /* * When power savings policy is enabled for the parent domain, idle @@ -4673,7 +4694,7 @@ int select_nohz_load_balancer(int stop_tick) cpumask_set_cpu(cpu, nohz.cpu_mask); /* time for ilb owner also to sleep */ - if (cpumask_weight(nohz.cpu_mask) == num_active_cpus()) { + if (cpumask_weight(nohz.cpu_mask) == num_online_cpus()) { if (atomic_read(&nohz.load_balancer) == cpu) atomic_set(&nohz.load_balancer, -1); return 0; @@ -5375,14 +5396,13 @@ static inline void schedule_debug(struct task_struct *prev) #endif } -static void put_prev_task(struct rq *rq, struct task_struct *prev) +static void put_prev_task(struct rq *rq, struct task_struct *p) { - if (prev->state == TASK_RUNNING) { - u64 runtime = prev->se.sum_exec_runtime; + u64 runtime = p->se.sum_exec_runtime - p->se.prev_sum_exec_runtime; - runtime -= prev->se.prev_sum_exec_runtime; - runtime = min_t(u64, runtime, 2*sysctl_sched_migration_cost); + update_avg(&p->se.avg_running, runtime); + if (p->state == TASK_RUNNING) { /* * In order to avoid avg_overlap growing stale when we are * indeed overlapping and hence not getting put to sleep, grow @@ -5392,9 +5412,12 @@ static void put_prev_task(struct rq *rq, struct task_struct *prev) * correlates to the amount of cache footprint a task can * build up. */ - update_avg(&prev->se.avg_overlap, runtime); + runtime = min_t(u64, runtime, 2*sysctl_sched_migration_cost); + update_avg(&p->se.avg_overlap, runtime); + } else { + update_avg(&p->se.avg_running, 0); } - prev->sched_class->put_prev_task(rq, prev); + p->sched_class->put_prev_task(rq, p); } /* @@ -6608,8 +6631,6 @@ SYSCALL_DEFINE3(sched_setaffinity, pid_t, pid, unsigned int, len, long sched_getaffinity(pid_t pid, struct cpumask *mask) { struct task_struct *p; - unsigned long flags; - struct rq *rq; int retval; get_online_cpus(); @@ -6624,9 +6645,7 @@ long sched_getaffinity(pid_t pid, struct cpumask *mask) if (retval) goto out_unlock; - rq = task_rq_lock(p, &flags); cpumask_and(mask, &p->cpus_allowed, cpu_online_mask); - task_rq_unlock(rq, &flags); out_unlock: read_unlock(&tasklist_lock); @@ -6864,8 +6883,6 @@ SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid, { struct task_struct *p; unsigned int time_slice; - unsigned long flags; - struct rq *rq; int retval; struct timespec t; @@ -6882,9 +6899,7 @@ SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid, if (retval) goto out_unlock; - rq = task_rq_lock(p, &flags); - time_slice = p->sched_class->get_rr_interval(rq, p); - task_rq_unlock(rq, &flags); + time_slice = p->sched_class->get_rr_interval(p); read_unlock(&tasklist_lock); jiffies_to_timespec(time_slice, &t); @@ -6985,6 +7000,7 @@ void __cpuinit init_idle(struct task_struct *idle, int cpu) __sched_fork(idle); idle->se.exec_start = sched_clock(); + idle->prio = idle->normal_prio = MAX_PRIO; cpumask_copy(&idle->cpus_allowed, cpumask_of(cpu)); __set_task_cpu(idle, cpu); @@ -7025,43 +7041,22 @@ cpumask_var_t nohz_cpu_mask; * * This idea comes from the SD scheduler of Con Kolivas: */ -static int get_update_sysctl_factor(void) +static inline void sched_init_granularity(void) { - unsigned int cpus = min_t(int, num_online_cpus(), 8); - unsigned int factor; - - switch (sysctl_sched_tunable_scaling) { - case SCHED_TUNABLESCALING_NONE: - factor = 1; - break; - case SCHED_TUNABLESCALING_LINEAR: - factor = cpus; - break; - case SCHED_TUNABLESCALING_LOG: - default: - factor = 1 + ilog2(cpus); - break; - } + unsigned int factor = 1 + ilog2(num_online_cpus()); + const unsigned long limit = 200000000; - return factor; -} + sysctl_sched_min_granularity *= factor; + if (sysctl_sched_min_granularity > limit) + sysctl_sched_min_granularity = limit; -static void update_sysctl(void) -{ - unsigned int factor = get_update_sysctl_factor(); + sysctl_sched_latency *= factor; + if (sysctl_sched_latency > limit) + sysctl_sched_latency = limit; -#define SET_SYSCTL(name) \ - (sysctl_##name = (factor) * normalized_sysctl_##name) - SET_SYSCTL(sched_min_granularity); - SET_SYSCTL(sched_latency); - SET_SYSCTL(sched_wakeup_granularity); - SET_SYSCTL(sched_shares_ratelimit); -#undef SET_SYSCTL -} + sysctl_sched_wakeup_granularity *= factor; -static inline void sched_init_granularity(void) -{ - update_sysctl(); + sysctl_sched_shares_ratelimit *= factor; } #ifdef CONFIG_SMP @@ -7098,7 +7093,7 @@ int set_cpus_allowed_ptr(struct task_struct *p, const struct cpumask *new_mask) int ret = 0; rq = task_rq_lock(p, &flags); - if (!cpumask_intersects(new_mask, cpu_active_mask)) { + if (!cpumask_intersects(new_mask, cpu_online_mask)) { ret = -EINVAL; goto out; } @@ -7120,7 +7115,7 @@ int set_cpus_allowed_ptr(struct task_struct *p, const struct cpumask *new_mask) if (cpumask_test_cpu(task_cpu(p), new_mask)) goto out; - if (migrate_task(p, cpumask_any_and(cpu_active_mask, new_mask), &req)) { + if (migrate_task(p, cpumask_any_and(cpu_online_mask, new_mask), &req)) { /* Need help from migration thread: drop lock and wait. */ struct task_struct *mt = rq->migration_thread; @@ -7274,19 +7269,19 @@ static void move_task_off_dead_cpu(int dead_cpu, struct task_struct *p) again: /* Look for allowed, online CPU in same node. */ - for_each_cpu_and(dest_cpu, nodemask, cpu_active_mask) + for_each_cpu_and(dest_cpu, nodemask, cpu_online_mask) if (cpumask_test_cpu(dest_cpu, &p->cpus_allowed)) goto move; /* Any allowed, online CPU? */ - dest_cpu = cpumask_any_and(&p->cpus_allowed, cpu_active_mask); + dest_cpu = cpumask_any_and(&p->cpus_allowed, cpu_online_mask); if (dest_cpu < nr_cpu_ids) goto move; /* No more Mr. Nice Guy. */ if (dest_cpu >= nr_cpu_ids) { cpuset_cpus_allowed_locked(p, &p->cpus_allowed); - dest_cpu = cpumask_any_and(cpu_active_mask, &p->cpus_allowed); + dest_cpu = cpumask_any_and(cpu_online_mask, &p->cpus_allowed); /* * Don't tell them about moving exiting tasks or @@ -7315,7 +7310,7 @@ static void move_task_off_dead_cpu(int dead_cpu, struct task_struct *p) */ static void migrate_nr_uninterruptible(struct rq *rq_src) { - struct rq *rq_dest = cpu_rq(cpumask_any(cpu_active_mask)); + struct rq *rq_dest = cpu_rq(cpumask_any(cpu_online_mask)); unsigned long flags; local_irq_save(flags); @@ -7568,7 +7563,7 @@ static ctl_table *sd_alloc_ctl_cpu_table(int cpu) static struct ctl_table_header *sd_sysctl_header; static void register_sched_domain_sysctl(void) { - int i, cpu_num = num_possible_cpus(); + int i, cpu_num = num_online_cpus(); struct ctl_table *entry = sd_alloc_ctl_entry(cpu_num + 1); char buf[32]; @@ -7578,7 +7573,7 @@ static void register_sched_domain_sysctl(void) if (entry == NULL) return; - for_each_possible_cpu(i) { + for_each_online_cpu(i) { snprintf(buf, 32, "cpu%d", i); entry->procname = kstrdup(buf, GFP_KERNEL); entry->mode = 0555; @@ -7708,6 +7703,7 @@ migration_call(struct notifier_block *nfb, unsigned long action, void *hcpu) spin_lock_irq(&rq->lock); update_rq_clock(rq); deactivate_task(rq, rq->idle, 0); + rq->idle->static_prio = MAX_PRIO; __setscheduler(rq, rq->idle, SCHED_NORMAL, 0); rq->idle->sched_class = &idle_sched_class; migrate_dead_tasks(cpu); @@ -9103,7 +9099,7 @@ void partition_sched_domains(int ndoms_new, cpumask_var_t doms_new[], if (doms_new == NULL) { ndoms_cur = 0; doms_new = &fallback_doms; - cpumask_andnot(doms_new[0], cpu_active_mask, cpu_isolated_map); + cpumask_andnot(doms_new[0], cpu_online_mask, cpu_isolated_map); WARN_ON_ONCE(dattr_new); } @@ -9234,10 +9230,8 @@ static int update_sched_domains(struct notifier_block *nfb, switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: - case CPU_DOWN_PREPARE: - case CPU_DOWN_PREPARE_FROZEN: - case CPU_DOWN_FAILED: - case CPU_DOWN_FAILED_FROZEN: + case CPU_DEAD: + case CPU_DEAD_FROZEN: partition_sched_domains(1, NULL, NULL); return NOTIFY_OK; @@ -9284,7 +9278,7 @@ void __init sched_init_smp(void) #endif get_online_cpus(); mutex_lock(&sched_domains_mutex); - arch_init_sched_domains(cpu_active_mask); + arch_init_sched_domains(cpu_online_mask); cpumask_andnot(non_isolated_cpus, cpu_possible_mask, cpu_isolated_map); if (cpumask_empty(non_isolated_cpus)) cpumask_set_cpu(smp_processor_id(), non_isolated_cpus); @@ -9848,15 +9842,13 @@ int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent) se = kzalloc_node(sizeof(struct sched_entity), GFP_KERNEL, cpu_to_node(i)); if (!se) - goto err_free_rq; + goto err; init_tg_cfs_entry(tg, cfs_rq, se, i, 0, parent->se[i]); } return 1; - err_free_rq: - kfree(cfs_rq); err: return 0; } @@ -9938,15 +9930,13 @@ int alloc_rt_sched_group(struct task_group *tg, struct task_group *parent) rt_se = kzalloc_node(sizeof(struct sched_rt_entity), GFP_KERNEL, cpu_to_node(i)); if (!rt_se) - goto err_free_rq; + goto err; init_tg_rt_entry(tg, rt_rq, rt_se, i, 0, parent->rt_se[i]); } return 1; - err_free_rq: - kfree(rt_rq); err: return 0; } diff --git a/trunk/kernel/sched_debug.c b/trunk/kernel/sched_debug.c index 5ae24fc65d75..6988cf08f705 100644 --- a/trunk/kernel/sched_debug.c +++ b/trunk/kernel/sched_debug.c @@ -309,12 +309,6 @@ static void print_cpu(struct seq_file *m, int cpu) print_rq(m, rq, cpu); } -static const char *sched_tunable_scaling_names[] = { - "none", - "logaritmic", - "linear" -}; - static int sched_debug_show(struct seq_file *m, void *v) { u64 now = ktime_to_ns(ktime_get()); @@ -340,10 +334,6 @@ static int sched_debug_show(struct seq_file *m, void *v) #undef PN #undef P - SEQ_printf(m, " .%-40s: %d (%s)\n", "sysctl_sched_tunable_scaling", - sysctl_sched_tunable_scaling, - sched_tunable_scaling_names[sysctl_sched_tunable_scaling]); - for_each_online_cpu(cpu) print_cpu(m, cpu); @@ -409,6 +399,7 @@ void proc_sched_show_task(struct task_struct *p, struct seq_file *m) PN(se.sum_exec_runtime); PN(se.avg_overlap); PN(se.avg_wakeup); + PN(se.avg_running); nr_switches = p->nvcsw + p->nivcsw; @@ -432,6 +423,7 @@ void proc_sched_show_task(struct task_struct *p, struct seq_file *m) P(se.nr_failed_migrations_running); P(se.nr_failed_migrations_hot); P(se.nr_forced_migrations); + P(se.nr_forced2_migrations); P(se.nr_wakeups); P(se.nr_wakeups_sync); P(se.nr_wakeups_migrate); @@ -507,6 +499,7 @@ void proc_sched_set_task(struct task_struct *p) p->se.nr_failed_migrations_running = 0; p->se.nr_failed_migrations_hot = 0; p->se.nr_forced_migrations = 0; + p->se.nr_forced2_migrations = 0; p->se.nr_wakeups = 0; p->se.nr_wakeups_sync = 0; p->se.nr_wakeups_migrate = 0; diff --git a/trunk/kernel/sched_fair.c b/trunk/kernel/sched_fair.c index 804a411838f1..f61837ad336d 100644 --- a/trunk/kernel/sched_fair.c +++ b/trunk/kernel/sched_fair.c @@ -21,7 +21,6 @@ */ #include -#include /* * Targeted preemption latency for CPU-bound tasks: @@ -36,26 +35,12 @@ * run vmstat and monitor the context-switches (cs) field) */ unsigned int sysctl_sched_latency = 5000000ULL; -unsigned int normalized_sysctl_sched_latency = 5000000ULL; - -/* - * The initial- and re-scaling of tunables is configurable - * (default SCHED_TUNABLESCALING_LOG = *(1+ilog(ncpus)) - * - * Options are: - * SCHED_TUNABLESCALING_NONE - unscaled, always *1 - * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus) - * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus - */ -enum sched_tunable_scaling sysctl_sched_tunable_scaling - = SCHED_TUNABLESCALING_LOG; /* * Minimal preemption granularity for CPU-bound tasks: * (default: 1 msec * (1 + ilog(ncpus)), units: nanoseconds) */ unsigned int sysctl_sched_min_granularity = 1000000ULL; -unsigned int normalized_sysctl_sched_min_granularity = 1000000ULL; /* * is kept at sysctl_sched_latency / sysctl_sched_min_granularity @@ -85,7 +70,6 @@ unsigned int __read_mostly sysctl_sched_compat_yield; * have immediate wakeup/sleep latencies. */ unsigned int sysctl_sched_wakeup_granularity = 1000000UL; -unsigned int normalized_sysctl_sched_wakeup_granularity = 1000000UL; const_debug unsigned int sysctl_sched_migration_cost = 500000UL; @@ -399,12 +383,11 @@ static struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) */ #ifdef CONFIG_SCHED_DEBUG -int sched_proc_update_handler(struct ctl_table *table, int write, +int sched_nr_latency_handler(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); - int factor = get_update_sysctl_factor(); if (ret || !write) return ret; @@ -412,14 +395,6 @@ int sched_proc_update_handler(struct ctl_table *table, int write, sched_nr_latency = DIV_ROUND_UP(sysctl_sched_latency, sysctl_sched_min_granularity); -#define WRT_SYSCTL(name) \ - (normalized_sysctl_##name = sysctl_##name / (factor)) - WRT_SYSCTL(sched_min_granularity); - WRT_SYSCTL(sched_latency); - WRT_SYSCTL(sched_wakeup_granularity); - WRT_SYSCTL(sched_shares_ratelimit); -#undef WRT_SYSCTL - return 0; } #endif @@ -1428,6 +1403,7 @@ static int select_task_rq_fair(struct task_struct *p, int sd_flag, int wake_flag new_cpu = prev_cpu; } + rcu_read_lock(); for_each_domain(cpu, tmp) { /* * If power savings logic is enabled for a domain, see if we @@ -1508,8 +1484,10 @@ static int select_task_rq_fair(struct task_struct *p, int sd_flag, int wake_flag update_shares(tmp); } - if (affine_sd && wake_affine(affine_sd, p, sync)) - return cpu; + if (affine_sd && wake_affine(affine_sd, p, sync)) { + new_cpu = cpu; + goto out; + } while (sd) { int load_idx = sd->forkexec_idx; @@ -1550,6 +1528,8 @@ static int select_task_rq_fair(struct task_struct *p, int sd_flag, int wake_flag /* while loop will break here if sd == NULL */ } +out: + rcu_read_unlock(); return new_cpu; } #endif /* CONFIG_SMP */ @@ -1671,8 +1651,12 @@ static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int wake_ int sync = wake_flags & WF_SYNC; int scale = cfs_rq->nr_running >= sched_nr_latency; - if (unlikely(rt_prio(p->prio))) - goto preempt; + update_curr(cfs_rq); + + if (unlikely(rt_prio(p->prio))) { + resched_task(curr); + return; + } if (unlikely(p->sched_class != &fair_sched_class)) return; @@ -1698,44 +1682,50 @@ static void check_preempt_wakeup(struct rq *rq, struct task_struct *p, int wake_ return; /* Idle tasks are by definition preempted by everybody. */ - if (unlikely(curr->policy == SCHED_IDLE)) - goto preempt; + if (unlikely(curr->policy == SCHED_IDLE)) { + resched_task(curr); + return; + } - if (sched_feat(WAKEUP_SYNC) && sync) - goto preempt; + if ((sched_feat(WAKEUP_SYNC) && sync) || + (sched_feat(WAKEUP_OVERLAP) && + (se->avg_overlap < sysctl_sched_migration_cost && + pse->avg_overlap < sysctl_sched_migration_cost))) { + resched_task(curr); + return; + } - if (sched_feat(WAKEUP_OVERLAP) && - se->avg_overlap < sysctl_sched_migration_cost && - pse->avg_overlap < sysctl_sched_migration_cost) - goto preempt; + if (sched_feat(WAKEUP_RUNNING)) { + if (pse->avg_running < se->avg_running) { + set_next_buddy(pse); + resched_task(curr); + return; + } + } if (!sched_feat(WAKEUP_PREEMPT)) return; - update_curr(cfs_rq); find_matching_se(&se, &pse); - BUG_ON(!pse); - if (wakeup_preempt_entity(se, pse) == 1) - goto preempt; - - return; -preempt: - resched_task(curr); - /* - * Only set the backward buddy when the current task is still - * on the rq. This can happen when a wakeup gets interleaved - * with schedule on the ->pre_schedule() or idle_balance() - * point, either of which can * drop the rq lock. - * - * Also, during early boot the idle thread is in the fair class, - * for obvious reasons its a bad idea to schedule back to it. - */ - if (unlikely(!se->on_rq || curr == rq->idle)) - return; + BUG_ON(!pse); - if (sched_feat(LAST_BUDDY) && scale && entity_is_task(se)) - set_last_buddy(se); + if (wakeup_preempt_entity(se, pse) == 1) { + resched_task(curr); + /* + * Only set the backward buddy when the current task is still + * on the rq. This can happen when a wakeup gets interleaved + * with schedule on the ->pre_schedule() or idle_balance() + * point, either of which can * drop the rq lock. + * + * Also, during early boot the idle thread is in the fair class, + * for obvious reasons its a bad idea to schedule back to it. + */ + if (unlikely(!se->on_rq || curr == rq->idle)) + return; + if (sched_feat(LAST_BUDDY) && scale && entity_is_task(se)) + set_last_buddy(se); + } } static struct task_struct *pick_next_task_fair(struct rq *rq) @@ -1915,17 +1905,6 @@ move_one_task_fair(struct rq *this_rq, int this_cpu, struct rq *busiest, return 0; } - -static void rq_online_fair(struct rq *rq) -{ - update_sysctl(); -} - -static void rq_offline_fair(struct rq *rq) -{ - update_sysctl(); -} - #endif /* CONFIG_SMP */ /* @@ -1943,30 +1922,28 @@ static void task_tick_fair(struct rq *rq, struct task_struct *curr, int queued) } /* - * called on fork with the child task as argument from the parent's context - * - child not yet on the tasklist - * - preemption disabled + * Share the fairness runtime between parent and child, thus the + * total amount of pressure for CPU stays equal - new tasks + * get a chance to run but frequent forkers are not allowed to + * monopolize the CPU. Note: the parent runqueue is locked, + * the child is not running yet. */ -static void task_fork_fair(struct task_struct *p) +static void task_new_fair(struct rq *rq, struct task_struct *p) { - struct cfs_rq *cfs_rq = task_cfs_rq(current); + struct cfs_rq *cfs_rq = task_cfs_rq(p); struct sched_entity *se = &p->se, *curr = cfs_rq->curr; int this_cpu = smp_processor_id(); - struct rq *rq = this_rq(); - unsigned long flags; - - spin_lock_irqsave(&rq->lock, flags); - if (unlikely(task_cpu(p) != this_cpu)) - __set_task_cpu(p, this_cpu); + sched_info_queued(p); update_curr(cfs_rq); - if (curr) se->vruntime = curr->vruntime; place_entity(cfs_rq, se, 1); - if (sysctl_sched_child_runs_first && curr && entity_before(curr, se)) { + /* 'curr' will be NULL if the child belongs to a different group */ + if (sysctl_sched_child_runs_first && this_cpu == task_cpu(p) && + curr && entity_before(curr, se)) { /* * Upon rescheduling, sched_class::put_prev_task() will place * 'current' within the tree based on its new key value. @@ -1975,7 +1952,7 @@ static void task_fork_fair(struct task_struct *p) resched_task(rq->curr); } - spin_unlock_irqrestore(&rq->lock, flags); + enqueue_task_fair(rq, p, 0); } /* @@ -2037,17 +2014,21 @@ static void moved_group_fair(struct task_struct *p) } #endif -unsigned int get_rr_interval_fair(struct rq *rq, struct task_struct *task) +unsigned int get_rr_interval_fair(struct task_struct *task) { struct sched_entity *se = &task->se; + unsigned long flags; + struct rq *rq; unsigned int rr_interval = 0; /* * Time slice is 0 for SCHED_OTHER tasks that are on an otherwise * idle runqueue: */ + rq = task_rq_lock(task, &flags); if (rq->cfs.load.weight) rr_interval = NS_TO_JIFFIES(sched_slice(&rq->cfs, se)); + task_rq_unlock(rq, &flags); return rr_interval; } @@ -2071,13 +2052,11 @@ static const struct sched_class fair_sched_class = { .load_balance = load_balance_fair, .move_one_task = move_one_task_fair, - .rq_online = rq_online_fair, - .rq_offline = rq_offline_fair, #endif .set_curr_task = set_curr_task_fair, .task_tick = task_tick_fair, - .task_fork = task_fork_fair, + .task_new = task_new_fair, .prio_changed = prio_changed_fair, .switched_to = switched_to_fair, diff --git a/trunk/kernel/sched_features.h b/trunk/kernel/sched_features.h index d5059fd761d9..0d94083582c7 100644 --- a/trunk/kernel/sched_features.h +++ b/trunk/kernel/sched_features.h @@ -53,6 +53,11 @@ SCHED_FEAT(WAKEUP_SYNC, 0) */ SCHED_FEAT(WAKEUP_OVERLAP, 0) +/* + * Wakeup preemption towards tasks that run short + */ +SCHED_FEAT(WAKEUP_RUNNING, 0) + /* * Use the SYNC wakeup hint, pipes and the likes use this to indicate * the remote end is likely to consume the data we just wrote, and diff --git a/trunk/kernel/sched_idletask.c b/trunk/kernel/sched_idletask.c index 33d5384a73a8..b133a28fcde3 100644 --- a/trunk/kernel/sched_idletask.c +++ b/trunk/kernel/sched_idletask.c @@ -97,7 +97,7 @@ static void prio_changed_idle(struct rq *rq, struct task_struct *p, check_preempt_curr(rq, p, 0); } -unsigned int get_rr_interval_idle(struct rq *rq, struct task_struct *task) +unsigned int get_rr_interval_idle(struct task_struct *task) { return 0; } diff --git a/trunk/kernel/sched_rt.c b/trunk/kernel/sched_rt.c index aecbd9c6b20c..5c5fef378415 100644 --- a/trunk/kernel/sched_rt.c +++ b/trunk/kernel/sched_rt.c @@ -1721,7 +1721,7 @@ static void set_curr_task_rt(struct rq *rq) dequeue_pushable_task(rq, p); } -unsigned int get_rr_interval_rt(struct rq *rq, struct task_struct *task) +unsigned int get_rr_interval_rt(struct task_struct *task) { /* * Time slice is 0 for SCHED_FIFO tasks diff --git a/trunk/kernel/sysctl.c b/trunk/kernel/sysctl.c index 554ac4894f0f..9327a26765c5 100644 --- a/trunk/kernel/sysctl.c +++ b/trunk/kernel/sysctl.c @@ -244,10 +244,6 @@ static int min_sched_granularity_ns = 100000; /* 100 usecs */ static int max_sched_granularity_ns = NSEC_PER_SEC; /* 1 second */ static int min_wakeup_granularity_ns; /* 0 usecs */ static int max_wakeup_granularity_ns = NSEC_PER_SEC; /* 1 second */ -static int min_sched_tunable_scaling = SCHED_TUNABLESCALING_NONE; -static int max_sched_tunable_scaling = SCHED_TUNABLESCALING_END-1; -static int min_sched_shares_ratelimit = 100000; /* 100 usec */ -static int max_sched_shares_ratelimit = NSEC_PER_SEC; /* 1 second */ #endif static struct ctl_table kern_table[] = { @@ -264,7 +260,7 @@ static struct ctl_table kern_table[] = { .data = &sysctl_sched_min_granularity, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = sched_proc_update_handler, + .proc_handler = sched_nr_latency_handler, .extra1 = &min_sched_granularity_ns, .extra2 = &max_sched_granularity_ns, }, @@ -273,7 +269,7 @@ static struct ctl_table kern_table[] = { .data = &sysctl_sched_latency, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = sched_proc_update_handler, + .proc_handler = sched_nr_latency_handler, .extra1 = &min_sched_granularity_ns, .extra2 = &max_sched_granularity_ns, }, @@ -282,7 +278,7 @@ static struct ctl_table kern_table[] = { .data = &sysctl_sched_wakeup_granularity, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = sched_proc_update_handler, + .proc_handler = proc_dointvec_minmax, .extra1 = &min_wakeup_granularity_ns, .extra2 = &max_wakeup_granularity_ns, }, @@ -291,18 +287,7 @@ static struct ctl_table kern_table[] = { .data = &sysctl_sched_shares_ratelimit, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = sched_proc_update_handler, - .extra1 = &min_sched_shares_ratelimit, - .extra2 = &max_sched_shares_ratelimit, - }, - { - .procname = "sched_tunable_scaling", - .data = &sysctl_sched_tunable_scaling, - .maxlen = sizeof(enum sched_tunable_scaling), - .mode = 0644, - .proc_handler = sched_proc_update_handler, - .extra1 = &min_sched_tunable_scaling, - .extra2 = &max_sched_tunable_scaling, + .proc_handler = proc_dointvec, }, { .procname = "sched_shares_thresh", @@ -312,6 +297,13 @@ static struct ctl_table kern_table[] = { .proc_handler = proc_dointvec_minmax, .extra1 = &zero, }, + { + .procname = "sched_features", + .data = &sysctl_sched_features, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, { .procname = "sched_migration_cost", .data = &sysctl_sched_migration_cost, diff --git a/trunk/lib/kernel_lock.c b/trunk/lib/kernel_lock.c index 5526b46aba94..4ebfa5a164d7 100644 --- a/trunk/lib/kernel_lock.c +++ b/trunk/lib/kernel_lock.c @@ -122,10 +122,8 @@ void __lockfunc _lock_kernel(const char *func, const char *file, int line) trace_lock_kernel(func, file, line); - if (likely(!depth)) { - might_sleep(); + if (likely(!depth)) __lock_kernel(); - } current->lock_depth = depth; } diff --git a/trunk/mm/slab.c b/trunk/mm/slab.c index a6c9166996a9..7dfa481c96ba 100644 --- a/trunk/mm/slab.c +++ b/trunk/mm/slab.c @@ -604,26 +604,6 @@ static struct kmem_cache cache_cache = { #define BAD_ALIEN_MAGIC 0x01020304ul -/* - * chicken and egg problem: delay the per-cpu array allocation - * until the general caches are up. - */ -static enum { - NONE, - PARTIAL_AC, - PARTIAL_L3, - EARLY, - FULL -} g_cpucache_up; - -/* - * used by boot code to determine if it can use slab based allocator - */ -int slab_is_available(void) -{ - return g_cpucache_up >= EARLY; -} - #ifdef CONFIG_LOCKDEP /* @@ -640,52 +620,40 @@ int slab_is_available(void) static struct lock_class_key on_slab_l3_key; static struct lock_class_key on_slab_alc_key; -static void init_node_lock_keys(int q) +static inline void init_lock_keys(void) + { + int q; struct cache_sizes *s = malloc_sizes; - if (g_cpucache_up != FULL) - return; - - for (s = malloc_sizes; s->cs_size != ULONG_MAX; s++) { - struct array_cache **alc; - struct kmem_list3 *l3; - int r; - - l3 = s->cs_cachep->nodelists[q]; - if (!l3 || OFF_SLAB(s->cs_cachep)) - return; - lockdep_set_class(&l3->list_lock, &on_slab_l3_key); - alc = l3->alien; - /* - * FIXME: This check for BAD_ALIEN_MAGIC - * should go away when common slab code is taught to - * work even without alien caches. - * Currently, non NUMA code returns BAD_ALIEN_MAGIC - * for alloc_alien_cache, - */ - if (!alc || (unsigned long)alc == BAD_ALIEN_MAGIC) - return; - for_each_node(r) { - if (alc[r]) - lockdep_set_class(&alc[r]->lock, - &on_slab_alc_key); + while (s->cs_size != ULONG_MAX) { + for_each_node(q) { + struct array_cache **alc; + int r; + struct kmem_list3 *l3 = s->cs_cachep->nodelists[q]; + if (!l3 || OFF_SLAB(s->cs_cachep)) + continue; + lockdep_set_class(&l3->list_lock, &on_slab_l3_key); + alc = l3->alien; + /* + * FIXME: This check for BAD_ALIEN_MAGIC + * should go away when common slab code is taught to + * work even without alien caches. + * Currently, non NUMA code returns BAD_ALIEN_MAGIC + * for alloc_alien_cache, + */ + if (!alc || (unsigned long)alc == BAD_ALIEN_MAGIC) + continue; + for_each_node(r) { + if (alc[r]) + lockdep_set_class(&alc[r]->lock, + &on_slab_alc_key); + } } + s++; } } - -static inline void init_lock_keys(void) -{ - int node; - - for_each_node(node) - init_node_lock_keys(node); -} #else -static void init_node_lock_keys(int q) -{ -} - static inline void init_lock_keys(void) { } @@ -697,6 +665,26 @@ static inline void init_lock_keys(void) static DEFINE_MUTEX(cache_chain_mutex); static struct list_head cache_chain; +/* + * chicken and egg problem: delay the per-cpu array allocation + * until the general caches are up. + */ +static enum { + NONE, + PARTIAL_AC, + PARTIAL_L3, + EARLY, + FULL +} g_cpucache_up; + +/* + * used by boot code to determine if it can use slab based allocator + */ +int slab_is_available(void) +{ + return g_cpucache_up >= EARLY; +} + static DEFINE_PER_CPU(struct delayed_work, reap_work); static inline struct array_cache *cpu_cache_get(struct kmem_cache *cachep) @@ -1266,8 +1254,6 @@ static int __cpuinit cpuup_prepare(long cpu) kfree(shared); free_alien_cache(alien); } - init_node_lock_keys(node); - return 0; bad: cpuup_canceled(cpu); @@ -3117,19 +3103,13 @@ static inline void *____cache_alloc(struct kmem_cache *cachep, gfp_t flags) } else { STATS_INC_ALLOCMISS(cachep); objp = cache_alloc_refill(cachep, flags); - /* - * the 'ac' may be updated by cache_alloc_refill(), - * and kmemleak_erase() requires its correct value. - */ - ac = cpu_cache_get(cachep); } /* * To avoid a false negative, if an object that is in one of the * per-CPU caches is leaked, we need to make sure kmemleak doesn't * treat the array pointers as a reference to the object. */ - if (objp) - kmemleak_erase(&ac->entry[ac->avail]); + kmemleak_erase(&ac->entry[ac->avail]); return objp; } @@ -3326,7 +3306,7 @@ __cache_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, cache_alloc_debugcheck_before(cachep, flags); local_irq_save(save_flags); - if (nodeid == -1) + if (unlikely(nodeid == -1)) nodeid = numa_node_id(); if (unlikely(!cachep->nodelists[nodeid])) { diff --git a/trunk/mm/slub.c b/trunk/mm/slub.c index da0ce55965dc..4996fc719552 100644 --- a/trunk/mm/slub.c +++ b/trunk/mm/slub.c @@ -1735,7 +1735,7 @@ static __always_inline void *slab_alloc(struct kmem_cache *s, } local_irq_restore(flags); - if (unlikely(gfpflags & __GFP_ZERO) && object) + if (unlikely((gfpflags & __GFP_ZERO) && object)) memset(object, 0, objsize); kmemcheck_slab_alloc(s, gfpflags, object, c->objsize); @@ -4371,28 +4371,12 @@ static int show_stat(struct kmem_cache *s, char *buf, enum stat_item si) return len + sprintf(buf + len, "\n"); } -static void clear_stat(struct kmem_cache *s, enum stat_item si) -{ - int cpu; - - for_each_online_cpu(cpu) - get_cpu_slab(s, cpu)->stat[si] = 0; -} - #define STAT_ATTR(si, text) \ static ssize_t text##_show(struct kmem_cache *s, char *buf) \ { \ return show_stat(s, buf, si); \ } \ -static ssize_t text##_store(struct kmem_cache *s, \ - const char *buf, size_t length) \ -{ \ - if (buf[0] != '0') \ - return -EINVAL; \ - clear_stat(s, si); \ - return length; \ -} \ -SLAB_ATTR(text); \ +SLAB_ATTR_RO(text); \ STAT_ATTR(ALLOC_FASTPATH, alloc_fastpath); STAT_ATTR(ALLOC_SLOWPATH, alloc_slowpath); diff --git a/trunk/sound/core/hrtimer.c b/trunk/sound/core/hrtimer.c index 7f4d744ae40a..34c7d48f5061 100644 --- a/trunk/sound/core/hrtimer.c +++ b/trunk/sound/core/hrtimer.c @@ -37,22 +37,14 @@ static unsigned int resolution; struct snd_hrtimer { struct snd_timer *timer; struct hrtimer hrt; - atomic_t running; }; static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt) { struct snd_hrtimer *stime = container_of(hrt, struct snd_hrtimer, hrt); struct snd_timer *t = stime->timer; - - if (!atomic_read(&stime->running)) - return HRTIMER_NORESTART; - hrtimer_forward_now(hrt, ns_to_ktime(t->sticks * resolution)); snd_timer_interrupt(stime->timer, t->sticks); - - if (!atomic_read(&stime->running)) - return HRTIMER_NORESTART; return HRTIMER_RESTART; } @@ -66,7 +58,6 @@ static int snd_hrtimer_open(struct snd_timer *t) hrtimer_init(&stime->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); stime->timer = t; stime->hrt.function = snd_hrtimer_callback; - atomic_set(&stime->running, 0); t->private_data = stime; return 0; } @@ -87,18 +78,16 @@ static int snd_hrtimer_start(struct snd_timer *t) { struct snd_hrtimer *stime = t->private_data; - atomic_set(&stime->running, 0); - hrtimer_cancel(&stime->hrt); hrtimer_start(&stime->hrt, ns_to_ktime(t->sticks * resolution), HRTIMER_MODE_REL); - atomic_set(&stime->running, 1); return 0; } static int snd_hrtimer_stop(struct snd_timer *t) { struct snd_hrtimer *stime = t->private_data; - atomic_set(&stime->running, 0); + + hrtimer_cancel(&stime->hrt); return 0; } diff --git a/trunk/sound/isa/opti9xx/opti92x-ad1848.c b/trunk/sound/isa/opti9xx/opti92x-ad1848.c index c8a8da0d4036..106be6e471f7 100644 --- a/trunk/sound/isa/opti9xx/opti92x-ad1848.c +++ b/trunk/sound/isa/opti9xx/opti92x-ad1848.c @@ -548,13 +548,10 @@ static int __devinit snd_opti9xx_configure(struct snd_opti9xx *chip, static irqreturn_t snd_opti93x_interrupt(int irq, void *dev_id) { - struct snd_opti9xx *chip = dev_id; - struct snd_wss *codec = chip->codec; + struct snd_wss *codec = dev_id; + struct snd_opti9xx *chip = codec->card->private_data; unsigned char status; - if (!codec) - return IRQ_HANDLED; - status = snd_opti9xx_read(chip, OPTi9XX_MC_REG(11)); if ((status & OPTi93X_IRQ_PLAYBACK) && codec->playback_substream) snd_pcm_period_elapsed(codec->playback_substream); @@ -694,9 +691,10 @@ static void snd_card_opti9xx_free(struct snd_card *card) if (chip) { #ifdef OPTi93X - if (chip->irq > 0) { - disable_irq(chip->irq); - free_irq(chip->irq, chip); + struct snd_wss *codec = chip->codec; + if (codec && codec->irq > 0) { + disable_irq(codec->irq); + free_irq(codec->irq, codec); } release_and_free_resource(chip->res_mc_indir); #endif @@ -761,9 +759,9 @@ static int __devinit snd_opti9xx_probe(struct snd_card *card) #endif #ifdef OPTi93X error = request_irq(irq, snd_opti93x_interrupt, - IRQF_DISABLED, DEV_NAME" - WSS", chip); + IRQF_DISABLED, DEV_NAME" - WSS", codec); if (error < 0) { - snd_printk(KERN_ERR "opti9xx: can't grab IRQ %d\n", irq); + snd_printk(KERN_ERR "opti9xx: can't grab IRQ %d\n", chip->irq); return error; } #endif diff --git a/trunk/sound/pci/hda/hda_codec.h b/trunk/sound/pci/hda/hda_codec.h index 1d541b7f5547..2d627613aea3 100644 --- a/trunk/sound/pci/hda/hda_codec.h +++ b/trunk/sound/pci/hda/hda_codec.h @@ -255,13 +255,9 @@ enum { * in HD-audio specification */ #define AC_PINCAP_HDMI (1<<7) /* HDMI pin */ -#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can - * coexist with AC_PINCAP_HDMI - */ #define AC_PINCAP_VREF (0x37<<8) #define AC_PINCAP_VREF_SHIFT 8 #define AC_PINCAP_EAPD (1<<16) /* EAPD capable */ -#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */ /* Vref status (used in pin cap) */ #define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */ #define AC_PINCAP_VREF_50 (1<<1) /* 50% */ @@ -639,7 +635,6 @@ struct hda_bus { unsigned int rirb_error:1; /* error in codec communication */ unsigned int response_reset:1; /* controller was reset */ unsigned int in_reset:1; /* during reset operation */ - unsigned int power_keep_link_on:1; /* don't power off HDA link */ }; /* diff --git a/trunk/sound/pci/hda/hda_intel.c b/trunk/sound/pci/hda/hda_intel.c index e54420e691ae..efcc4f7c57f2 100644 --- a/trunk/sound/pci/hda/hda_intel.c +++ b/trunk/sound/pci/hda/hda_intel.c @@ -2082,8 +2082,7 @@ static void azx_power_notify(struct hda_bus *bus) } if (power_on) azx_init_chip(chip); - else if (chip->running && power_save_controller && - !bus->power_keep_link_on) + else if (chip->running && power_save_controller) azx_stop_chip(chip); } #endif /* CONFIG_SND_HDA_POWER_SAVE */ diff --git a/trunk/sound/pci/hda/hda_proc.c b/trunk/sound/pci/hda/hda_proc.c index c9afc04adac8..09476fc1ab64 100644 --- a/trunk/sound/pci/hda/hda_proc.c +++ b/trunk/sound/pci/hda/hda_proc.c @@ -240,14 +240,9 @@ static void print_pin_caps(struct snd_info_buffer *buffer, /* Realtek uses this bit as a different meaning */ if ((codec->vendor_id >> 16) == 0x10ec) snd_iprintf(buffer, " R/L"); - else { - if (caps & AC_PINCAP_HBR) - snd_iprintf(buffer, " HBR"); + else snd_iprintf(buffer, " HDMI"); - } } - if (caps & AC_PINCAP_DP) - snd_iprintf(buffer, " DP"); if (caps & AC_PINCAP_TRIG_REQ) snd_iprintf(buffer, " Trigger"); if (caps & AC_PINCAP_IMP_SENSE) diff --git a/trunk/sound/pci/hda/patch_intelhdmi.c b/trunk/sound/pci/hda/patch_intelhdmi.c index 918f40378d52..928df59be5d8 100644 --- a/trunk/sound/pci/hda/patch_intelhdmi.c +++ b/trunk/sound/pci/hda/patch_intelhdmi.c @@ -145,42 +145,6 @@ struct cea_channel_speaker_allocation { int spk_mask; }; -/* - * ALSA sequence is: - * - * surround40 surround41 surround50 surround51 surround71 - * ch0 front left = = = = - * ch1 front right = = = = - * ch2 rear left = = = = - * ch3 rear right = = = = - * ch4 LFE center center center - * ch5 LFE LFE - * ch6 side left - * ch7 side right - * - * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} - */ -static int hdmi_channel_mapping[0x32][8] = { - /* stereo */ - [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, - /* 2.1 */ - [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, - /* Dolby Surround */ - [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, - /* surround40 */ - [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, - /* 4ch */ - [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, - /* surround41 */ - [0x09] = { 0x00, 0x11, 0x24, 0x34, 0x43, 0xf2, 0xf6, 0xf7 }, - /* surround50 */ - [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, - /* surround51 */ - [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, - /* 7.1 */ - [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, -}; - /* * This is an ordered list! * @@ -188,36 +152,32 @@ static int hdmi_channel_mapping[0x32][8] = { * hdmi_setup_channel_allocation(). */ static struct cea_channel_speaker_allocation channel_allocations[] = { -/* channel: 7 6 5 4 3 2 1 0 */ +/* channel: 8 7 6 5 4 3 2 1 */ { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, /* 2.1 */ { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, /* Dolby Surround */ { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, - /* surround40 */ -{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, - /* surround41 */ -{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, - /* surround50 */ -{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, - /* surround51 */ -{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, - /* 6.1 */ -{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, - /* surround71 */ -{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, - { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, +{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, + /* 5.1 */ +{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, + /* 6.1 */ +{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, + /* 7.1 */ +{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, @@ -250,6 +210,7 @@ static struct cea_channel_speaker_allocation channel_allocations[] = { { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, }; + /* * HDA/HDMI auto parsing */ @@ -383,7 +344,7 @@ static int intel_hdmi_parse_codec(struct hda_codec *codec) break; case AC_WID_PIN: caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP); - if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) + if (!(caps & AC_PINCAP_HDMI)) continue; if (intel_hdmi_add_pin(codec, nid) < 0) return -EINVAL; @@ -391,17 +352,6 @@ static int intel_hdmi_parse_codec(struct hda_codec *codec) } } - /* - * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event - * can be lost and presence sense verb will become inaccurate if the - * HDA link is powered off at hot plug or hw initialization time. - */ -#ifdef CONFIG_SND_HDA_POWER_SAVE - if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) & - AC_PWRST_EPSS)) - codec->bus->power_keep_link_on = 1; -#endif - return 0; } @@ -486,15 +436,14 @@ static void hdmi_set_channel_count(struct hda_codec *codec, AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); } -static void hdmi_debug_channel_mapping(struct hda_codec *codec, - hda_nid_t pin_nid) +static void hdmi_debug_channel_mapping(struct hda_codec *codec, hda_nid_t nid) { #ifdef CONFIG_SND_DEBUG_VERBOSE int i; int slot; for (i = 0; i < 8; i++) { - slot = snd_hda_codec_read(codec, pin_nid, 0, + slot = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_HDMI_CHAN_SLOT, i); printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n", slot >> 4, slot & 0xf); @@ -670,32 +619,25 @@ static int hdmi_setup_channel_allocation(struct hda_codec *codec, hda_nid_t nid, return ai->CA; } -static void hdmi_setup_channel_mapping(struct hda_codec *codec, - hda_nid_t pin_nid, +static void hdmi_setup_channel_mapping(struct hda_codec *codec, hda_nid_t nid, struct hdmi_audio_infoframe *ai) { int i; - int ca = ai->CA; - int err; - if (hdmi_channel_mapping[ca][1] == 0) { - for (i = 0; i < channel_allocations[ca].channels; i++) - hdmi_channel_mapping[ca][i] = i | (i << 4); - for (; i < 8; i++) - hdmi_channel_mapping[ca][i] = 0xf | (i << 4); - } + if (!ai->CA) + return; - for (i = 0; i < 8; i++) { - err = snd_hda_codec_write(codec, pin_nid, 0, - AC_VERB_SET_HDMI_CHAN_SLOT, - hdmi_channel_mapping[ca][i]); - if (err) { - snd_printdd(KERN_INFO "HDMI: channel mapping failed\n"); - break; - } - } + /* + * TODO: adjust channel mapping if necessary + * ALSA sequence is front/surr/clfe/side? + */ + + for (i = 0; i < 8; i++) + snd_hda_codec_write(codec, nid, 0, + AC_VERB_SET_HDMI_CHAN_SLOT, + (i << 4) | i); - hdmi_debug_channel_mapping(codec, pin_nid); + hdmi_debug_channel_mapping(codec, nid); } static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, @@ -734,6 +676,7 @@ static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, }; hdmi_setup_channel_allocation(codec, nid, &ai); + hdmi_setup_channel_mapping(codec, nid, &ai); for (i = 0; i < spec->num_pins; i++) { if (spec->pin_cvt[i] != nid) @@ -743,7 +686,6 @@ static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid, pin_nid = spec->pin[i]; if (!hdmi_infoframe_uptodate(codec, pin_nid, &ai)) { - hdmi_setup_channel_mapping(codec, pin_nid, &ai); hdmi_stop_infoframe_trans(codec, pin_nid); hdmi_fill_audio_infoframe(codec, pin_nid, &ai); hdmi_start_infoframe_trans(codec, pin_nid); diff --git a/trunk/sound/pci/hda/patch_sigmatel.c b/trunk/sound/pci/hda/patch_sigmatel.c index 3d59f8325848..6b0bc040c3b1 100644 --- a/trunk/sound/pci/hda/patch_sigmatel.c +++ b/trunk/sound/pci/hda/patch_sigmatel.c @@ -209,7 +209,6 @@ struct sigmatel_spec { unsigned int gpio_data; unsigned int gpio_mute; unsigned int gpio_led; - unsigned int gpio_led_polarity; /* stream */ unsigned int stream_delay; @@ -1539,13 +1538,6 @@ static unsigned int alienware_m17x_pin_configs[13] = { 0x904601b0, }; -static unsigned int intel_dg45id_pin_configs[14] = { - 0x02214230, 0x02A19240, 0x01013214, 0x01014210, - 0x01A19250, 0x01011212, 0x01016211, 0x40f000f0, - 0x40f000f0, 0x40f000f0, 0x40f000f0, 0x014510A0, - 0x074510B0, 0x40f000f0 -}; - static unsigned int *stac92hd73xx_brd_tbl[STAC_92HD73XX_MODELS] = { [STAC_92HD73XX_REF] = ref92hd73xx_pin_configs, [STAC_DELL_M6_AMIC] = dell_m6_pin_configs, @@ -1553,7 +1545,6 @@ static unsigned int *stac92hd73xx_brd_tbl[STAC_92HD73XX_MODELS] = { [STAC_DELL_M6_BOTH] = dell_m6_pin_configs, [STAC_DELL_EQ] = dell_m6_pin_configs, [STAC_ALIENWARE_M17X] = alienware_m17x_pin_configs, - [STAC_92HD73XX_INTEL] = intel_dg45id_pin_configs, }; static const char *stac92hd73xx_models[STAC_92HD73XX_MODELS] = { @@ -4733,61 +4724,13 @@ static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res) } } -/* - * This method searches for the mute LED GPIO configuration - * provided as OEM string in SMBIOS. The format of that string - * is HP_Mute_LED_P_G or HP_Mute_LED_P - * where P can be 0 or 1 and defines mute LED GPIO control state (low/high) - * that corresponds to the NOT muted state of the master volume - * and G is the index of the GPIO to use as the mute LED control (0..9) - * If _G portion is missing it is assigned based on the codec ID - * - * So, HP B-series like systems may have HP_Mute_LED_0 (current models) - * or HP_Mute_LED_0_3 (future models) OEM SMBIOS strings - */ -static int find_mute_led_gpio(struct hda_codec *codec) -{ - struct sigmatel_spec *spec = codec->spec; - const struct dmi_device *dev = NULL; - - if ((codec->subsystem_id >> 16) == PCI_VENDOR_ID_HP) { - while ((dev = dmi_find_device(DMI_DEV_TYPE_OEM_STRING, - NULL, dev))) { - if (sscanf(dev->name, "HP_Mute_LED_%d_%d", - &spec->gpio_led_polarity, - &spec->gpio_led) == 2) { - spec->gpio_led = 1 << spec->gpio_led; - return 1; - } - if (sscanf(dev->name, "HP_Mute_LED_%d", - &spec->gpio_led_polarity) == 1) { - switch (codec->vendor_id) { - case 0x111d7608: - /* GPIO 0 */ - spec->gpio_led = 0x01; - return 1; - case 0x111d7600: - case 0x111d7601: - case 0x111d7602: - case 0x111d7603: - /* GPIO 3 */ - spec->gpio_led = 0x08; - return 1; - } - } - } - } - return 0; -} - -static int hp_blike_system(u32 subsystem_id) +static int hp_bseries_system(u32 subsystem_id) { switch (subsystem_id) { - case 0x103c1520: - case 0x103c1521: - case 0x103c1523: - case 0x103c1524: - case 0x103c1525: + case 0x103c307e: + case 0x103c307f: + case 0x103c3080: + case 0x103c3081: case 0x103c1722: case 0x103c1723: case 0x103c1724: @@ -4796,14 +4739,6 @@ static int hp_blike_system(u32 subsystem_id) case 0x103c1727: case 0x103c1728: case 0x103c1729: - case 0x103c172a: - case 0x103c172b: - case 0x103c307e: - case 0x103c307f: - case 0x103c3080: - case 0x103c3081: - case 0x103c7007: - case 0x103c7008: return 1; } return 0; @@ -4898,7 +4833,7 @@ static int stac92xx_hp_check_power_status(struct hda_codec *codec, else spec->gpio_data |= spec->gpio_led; /* white */ - if (!spec->gpio_led_polarity) { + if (hp_bseries_system(codec->subsystem_id)) { /* LED state is inverted on these systems */ spec->gpio_data ^= spec->gpio_led; } @@ -5591,7 +5526,7 @@ static int patch_stac92hd71bxx(struct hda_codec *codec) break; } - if (hp_blike_system(codec->subsystem_id)) { + if (hp_bseries_system(codec->subsystem_id)) { pin_cfg = snd_hda_codec_get_pincfg(codec, 0x0f); if (get_defcfg_device(pin_cfg) == AC_JACK_LINE_OUT || get_defcfg_device(pin_cfg) == AC_JACK_SPEAKER || @@ -5609,10 +5544,26 @@ static int patch_stac92hd71bxx(struct hda_codec *codec) } } - if (find_mute_led_gpio(codec)) - snd_printd("mute LED gpio %d polarity %d\n", - spec->gpio_led, - spec->gpio_led_polarity); + if ((codec->subsystem_id >> 16) == PCI_VENDOR_ID_HP) { + const struct dmi_device *dev = NULL; + while ((dev = dmi_find_device(DMI_DEV_TYPE_OEM_STRING, + NULL, dev))) { + if (strcmp(dev->name, "HP_Mute_LED_1")) { + switch (codec->vendor_id) { + case 0x111d7608: + spec->gpio_led = 0x01; + break; + case 0x111d7600: + case 0x111d7601: + case 0x111d7602: + case 0x111d7603: + spec->gpio_led = 0x08; + break; + } + break; + } + } + } #ifdef CONFIG_SND_HDA_POWER_SAVE if (spec->gpio_led) { diff --git a/trunk/sound/soc/omap/Makefile b/trunk/sound/soc/omap/Makefile index 3db8a6c523f4..d49458a29bb7 100644 --- a/trunk/sound/soc/omap/Makefile +++ b/trunk/sound/soc/omap/Makefile @@ -23,9 +23,9 @@ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o obj-$(CONFIG_SND_OMAP_SOC_AMS_DELTA) += snd-soc-ams-delta.o obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o -obj-$(CONFIG_SND_OMAP_SOC_OMAP2EVM) += snd-soc-omap2evm.o -obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o -obj-$(CONFIG_SND_OMAP_SOC_OMAP3517EVM) += snd-soc-am3517evm.o +obj-$(CONFIG_MACH_OMAP2EVM) += snd-soc-omap2evm.o +obj-$(CONFIG_MACH_OMAP3EVM) += snd-soc-omap3evm.o +obj-$(CONFIG_MACH_OMAP3517EVM) += snd-soc-am3517evm.o obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o diff --git a/trunk/virt/kvm/kvm_main.c b/trunk/virt/kvm/kvm_main.c index e1f2bf8d7b1e..f92ba138007a 100644 --- a/trunk/virt/kvm/kvm_main.c +++ b/trunk/virt/kvm/kvm_main.c @@ -49,7 +49,6 @@ #include #include #include -#include #ifdef KVM_COALESCED_MMIO_PAGE_OFFSET #include "coalesced_mmio.h" @@ -1072,8 +1071,8 @@ void mark_page_dirty(struct kvm *kvm, gfn_t gfn) unsigned long rel_gfn = gfn - memslot->base_gfn; /* avoid RMW */ - if (!generic_test_le_bit(rel_gfn, memslot->dirty_bitmap)) - generic___set_le_bit(rel_gfn, memslot->dirty_bitmap); + if (!test_bit(rel_gfn, memslot->dirty_bitmap)) + set_bit(rel_gfn, memslot->dirty_bitmap); } }