From 4b14006f6bbcac859ca4fa99ae4fcb0dc89d1e97 Mon Sep 17 00:00:00 2001 From: Stefan Schmidt Date: Thu, 12 Jun 2008 07:07:22 +0100 Subject: [PATCH] --- yaml --- r: 98074 b: refs/heads/master c: 3692fd0aaef489b063518b5999c702bada5b6e22 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-arm/arch-pxa/regs-lcd.h | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 120c40467b10..235c7875d0b0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 62cfcf4f467733a8dc218691c791804a148da887 +refs/heads/master: 3692fd0aaef489b063518b5999c702bada5b6e22 diff --git a/trunk/include/asm-arm/arch-pxa/regs-lcd.h b/trunk/include/asm-arm/arch-pxa/regs-lcd.h index f762493f5141..3ba464c913a5 100644 --- a/trunk/include/asm-arm/arch-pxa/regs-lcd.h +++ b/trunk/include/asm-arm/arch-pxa/regs-lcd.h @@ -1,5 +1,8 @@ #ifndef __ASM_ARCH_REGS_LCD_H #define __ASM_ARCH_REGS_LCD_H + +#include + /* * LCD Controller Registers and Bits Definitions */ @@ -69,7 +72,7 @@ #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ #define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ #define LCCR0_LCDT (1 << 22) /* LCD panel type */ #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */