From 4b8bdd8686b818e908be71afaac779e3eeb72ee1 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Tue, 24 Mar 2009 14:02:42 +0800 Subject: [PATCH] --- yaml --- r: 139846 b: refs/heads/master c: e642c6f1d2ebea41b8d7ccc132734b74b5821034 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_sdvo.c | 3 +++ trunk/drivers/gpu/drm/i915/intel_sdvo_regs.h | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2ee27a4e4926..51a02b4402d0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 171a9e960ec820765e3b8e9dd1e3d8d81233d459 +refs/heads/master: e642c6f1d2ebea41b8d7ccc132734b74b5821034 diff --git a/trunk/drivers/gpu/drm/i915/intel_sdvo.c b/trunk/drivers/gpu/drm/i915/intel_sdvo.c index 31cd9b835aa4..ea311c7241c2 100644 --- a/trunk/drivers/gpu/drm/i915/intel_sdvo.c +++ b/trunk/drivers/gpu/drm/i915/intel_sdvo.c @@ -589,9 +589,12 @@ intel_sdvo_create_preferred_input_timing(struct intel_output *output, struct intel_sdvo_preferred_input_timing_args args; uint8_t status; + memset(&args, 0, sizeof(args)); args.clock = clock; args.width = width; args.height = height; + args.interlace = 0; + args.scaled = 0; intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, &args, sizeof(args)); status = intel_sdvo_read_response(output, NULL, 0); diff --git a/trunk/drivers/gpu/drm/i915/intel_sdvo_regs.h b/trunk/drivers/gpu/drm/i915/intel_sdvo_regs.h index 1117b9c151a6..193938b7d7f9 100644 --- a/trunk/drivers/gpu/drm/i915/intel_sdvo_regs.h +++ b/trunk/drivers/gpu/drm/i915/intel_sdvo_regs.h @@ -100,6 +100,9 @@ struct intel_sdvo_preferred_input_timing_args { u16 clock; u16 width; u16 height; + u8 interlace:1; + u8 scaled:1; + u8 pad:6; } __attribute__((packed)); /* I2C registers for SDVO */