From 4b8df57bbe4d1b46a37b5d3f4cfad21e08243e3a Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Mon, 15 Oct 2007 19:34:38 +1000 Subject: [PATCH] --- yaml --- r: 69331 b: refs/heads/master c: 2843e7f7d6ffd61da6fe1503eb42c25fa33fbfee h: refs/heads/master i: 69329: e0f19df9dd3e118940b5780fa9bd83f4140efe40 69327: a3323d21493dc002d6a6dc75c749aaca3489b28d v: v3 --- [refs] | 2 +- trunk/arch/powerpc/platforms/cell/axon_msi.c | 9 ++------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index d46e7ae952b7..bdf00e3872c3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: cdbd3865acc2e98a349b41d130985e6f5f2dfc19 +refs/heads/master: 2843e7f7d6ffd61da6fe1503eb42c25fa33fbfee diff --git a/trunk/arch/powerpc/platforms/cell/axon_msi.c b/trunk/arch/powerpc/platforms/cell/axon_msi.c index aca15007a01c..095988f13bf4 100644 --- a/trunk/arch/powerpc/platforms/cell/axon_msi.c +++ b/trunk/arch/powerpc/platforms/cell/axon_msi.c @@ -80,18 +80,13 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) dcr_write(msic->dcr_host, dcr_n, val); } -static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) -{ - return dcr_read(msic->dcr_host, dcr_n); -} - static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) { struct axon_msic *msic = get_irq_data(irq); u32 write_offset, msi; int idx; - write_offset = msic_dcr_read(msic, MSIC_WRITE_OFFSET_REG); + write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); /* write_offset doesn't wrap properly, so we have to mask it */ @@ -306,7 +301,7 @@ static int axon_msi_notify_reboot(struct notifier_block *nb, list_for_each_entry(msic, &axon_msic_list, list) { pr_debug("axon_msi: disabling %s\n", msic->irq_host->of_node->full_name); - tmp = msic_dcr_read(msic, MSIC_CTRL_REG); + tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; msic_dcr_write(msic, MSIC_CTRL_REG, tmp); }