From 4ba84402836ec9a0e36e1694c84d4b2e2a1d78c8 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Mon, 25 May 2009 16:50:10 +0000 Subject: [PATCH] --- yaml --- r: 145533 b: refs/heads/master c: d81e77f041881d8d91c767b8c84f9068290b10c6 h: refs/heads/master i: 145531: 32cd316c51790d5a3317deb44e9cc8616a5e13f0 v: v3 --- [refs] | 2 +- trunk/arch/arm/include/asm/cache.h | 16 ------------ trunk/arch/arm/include/asm/page.h | 7 ++++++ trunk/arch/arm/mach-mx2/clock_imx21.c | 2 +- trunk/arch/arm/mach-mx2/clock_imx27.c | 2 +- trunk/arch/arm/mach-mx3/clock-imx35.c | 2 +- trunk/arch/arm/mach-mx3/clock.c | 2 +- trunk/arch/arm/mach-pxa/imote2.c | 2 +- trunk/arch/arm/mm/proc-v7.S | 36 ++++++++------------------- trunk/drivers/serial/imx.c | 2 -- 10 files changed, 24 insertions(+), 49 deletions(-) diff --git a/[refs] b/[refs] index 1a123b670ee4..f9116749b38b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 947ca2e983c7f46b49dbfb5bf51d39941d39f000 +refs/heads/master: d81e77f041881d8d91c767b8c84f9068290b10c6 diff --git a/trunk/arch/arm/include/asm/cache.h b/trunk/arch/arm/include/asm/cache.h index feaa75f0013e..cb7a9e97fd7e 100644 --- a/trunk/arch/arm/include/asm/cache.h +++ b/trunk/arch/arm/include/asm/cache.h @@ -7,20 +7,4 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -/* - * Memory returned by kmalloc() may be used for DMA, so we must make - * sure that all such allocations are cache aligned. Otherwise, - * unrelated code may cause parts of the buffer to be read into the - * cache before the transfer is done, causing old data to be seen by - * the CPU. - */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES - -/* - * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. - */ -#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) -#define ARCH_SLAB_MINALIGN 8 -#endif - #endif diff --git a/trunk/arch/arm/include/asm/page.h b/trunk/arch/arm/include/asm/page.h index 7b522770f29d..e6eb8a67b807 100644 --- a/trunk/arch/arm/include/asm/page.h +++ b/trunk/arch/arm/include/asm/page.h @@ -202,6 +202,13 @@ typedef struct page *pgtable_t; (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +/* + * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. + */ +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define ARCH_SLAB_MINALIGN 8 +#endif + #include #endif diff --git a/trunk/arch/arm/mach-mx2/clock_imx21.c b/trunk/arch/arm/mach-mx2/clock_imx21.c index e4b08ca804ea..999d013e06e3 100644 --- a/trunk/arch/arm/mach-mx2/clock_imx21.c +++ b/trunk/arch/arm/mach-mx2/clock_imx21.c @@ -890,7 +890,7 @@ static struct clk clko_clk = { .con_id = n, \ .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup lookups[] __initdata = { /* It's unlikely that any driver wants one of them directly: _REGISTER_CLOCK(NULL, "ckih", ckih_clk) _REGISTER_CLOCK(NULL, "ckil", ckil_clk) diff --git a/trunk/arch/arm/mach-mx2/clock_imx27.c b/trunk/arch/arm/mach-mx2/clock_imx27.c index 2c971442f3f2..3f7280c490f0 100644 --- a/trunk/arch/arm/mach-mx2/clock_imx27.c +++ b/trunk/arch/arm/mach-mx2/clock_imx27.c @@ -621,7 +621,7 @@ DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) diff --git a/trunk/arch/arm/mach-mx3/clock-imx35.c b/trunk/arch/arm/mach-mx3/clock-imx35.c index 3c1e06f56dd6..53a112d4e04a 100644 --- a/trunk/arch/arm/mach-mx3/clock-imx35.c +++ b/trunk/arch/arm/mach-mx3/clock-imx35.c @@ -404,7 +404,7 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK(NULL, "asrc", asrc_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) diff --git a/trunk/arch/arm/mach-mx3/clock.c b/trunk/arch/arm/mach-mx3/clock.c index a68fcf981edf..9957a11533a4 100644 --- a/trunk/arch/arm/mach-mx3/clock.c +++ b/trunk/arch/arm/mach-mx3/clock.c @@ -516,7 +516,7 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK(NULL, "emi", emi_clk) _REGISTER_CLOCK(NULL, "cspi", cspi1_clk) _REGISTER_CLOCK(NULL, "cspi", cspi2_clk) diff --git a/trunk/arch/arm/mach-pxa/imote2.c b/trunk/arch/arm/mach-pxa/imote2.c index 2121309b2474..2b27336c29f1 100644 --- a/trunk/arch/arm/mach-pxa/imote2.c +++ b/trunk/arch/arm/mach-pxa/imote2.c @@ -412,7 +412,7 @@ static struct platform_device imote2_flash_device = { */ static struct i2c_board_info __initdata imote2_i2c_board_info[] = { { /* UCAM sensor board */ - .type = "max1238", + .type = "max1239", .addr = 0x35, }, { /* ITS400 Sensor board only */ .type = "max1363", diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index a08d9d2380d3..3397f1e64d76 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -184,37 +184,23 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} - - mrc p15, 0, r0, c0, c0, 0 @ read main ID register - and r10, r0, #0xff000000 @ ARM? - teq r10, #0x41000000 - bne 2f - and r5, r0, #0x00f00000 @ variant - and r6, r0, #0x0000000f @ revision - orr r0, r6, r5, lsr #20-4 @ combine variant and revision - #ifdef CONFIG_ARM_ERRATA_430973 - teq r5, #0x00100000 @ only present in r1p* - mrceq p15, 0, r10, c1, c0, 1 @ read aux control register - orreq r10, r10, #(1 << 6) @ set IBE to 1 - mcreq p15, 0, r10, c1, c0, 1 @ write aux control register + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 6) @ set IBE to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register #endif #ifdef CONFIG_ARM_ERRATA_458693 - teq r0, #0x20 @ only present in r2p0 - mrceq p15, 0, r10, c1, c0, 1 @ read aux control register - orreq r10, r10, #(1 << 5) @ set L1NEON to 1 - orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 - mcreq p15, 0, r10, c1, c0, 1 @ write aux control register + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 5) @ set L1NEON to 1 + orr r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register #endif #ifdef CONFIG_ARM_ERRATA_460075 - teq r0, #0x20 @ only present in r2p0 - mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register - tsteq r10, #1 << 22 - orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit - mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register + mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register #endif - -2: mov r10, #0 + mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #endif diff --git a/trunk/drivers/serial/imx.c b/trunk/drivers/serial/imx.c index 5f0be40dfdab..9f460b175c50 100644 --- a/trunk/drivers/serial/imx.c +++ b/trunk/drivers/serial/imx.c @@ -1031,8 +1031,6 @@ imx_console_setup(struct console *co, char *options) if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) co->index = 0; sport = imx_ports[co->index]; - if(sport == NULL) - return -ENODEV; if (options) uart_parse_options(options, &baud, &parity, &bits, &flow);