From 4cd201244d5f5f79ca11701090efcc397a48c3d7 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 11 Jul 2012 00:31:06 +0200 Subject: [PATCH] --- yaml --- r: 318757 b: refs/heads/master c: 4b4147c38f89dea536afc50a0a2d2ed005b49288 h: refs/heads/master i: 318755: 1b63cd0835e25cface2a859a5574aa9afab2300b v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 343b2a1a5016..a036e670c847 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 12f55818bac7b89c00e43504d12a45c47e49d282 +refs/heads/master: 4b4147c38f89dea536afc50a0a2d2ed005b49288 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 7aa6e97c2c72..acc99b21e0b6 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -1900,7 +1900,7 @@ /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ #define BLC_PWM_PCH_CTL1 0xc8250 -#define BLM_PCH_PWM_ENABLE (1 << 30) +#define BLM_PCH_PWM_ENABLE (1 << 31) #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254