From 4d70c297753778b0d8cba895ba90b07904f31bad Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 14 Dec 2011 13:57:15 +0100 Subject: [PATCH] --- yaml --- r: 293561 b: refs/heads/master c: c9c4b6f6c28354f1df9bd288dc33ba7ae0e66aaa h: refs/heads/master i: 293559: f0e53e1e48c9d9b99e79c241cb508db6ad85e239 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem_tiling.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index a8be98e9cecd..c824d8e5cbfc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 068c6ff1cbbfc09eed2b892dd7b0572dd6737785 +refs/heads/master: c9c4b6f6c28354f1df9bd288dc33ba7ae0e66aaa diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c index 31d334d9d9da..861223bf3944 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -107,10 +107,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (IS_MOBILE(dev)) { + } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { uint32_t dcc; - /* On mobile 9xx chipsets, channel interleave by the CPU is + /* On 9xx chipsets, channel interleave by the CPU is * determined by DCC. For single-channel, neither the CPU * nor the GPU do swizzling. For dual channel interleaved, * the GPU's interleave is bit 9 and 10 for X tiled, and bit