From 5052a5423b71154ff7daaf4ce4630db84512b1c7 Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Mon, 13 Feb 2012 11:23:10 +0100 Subject: [PATCH] --- yaml --- r: 290629 b: refs/heads/master c: 4e5ea2088b699ae86ffd96b53b916a3966535fcb h: refs/heads/master i: 290627: a7f661eb0e2e02392a8f79e747502f3cdf9bbaf7 v: v3 --- [refs] | 2 +- trunk/drivers/net/wireless/iwlegacy/common.c | 2 -- trunk/drivers/net/wireless/iwlegacy/common.h | 9 +++++++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index c83c3980fb63..a8c1c10fc7dc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1e0f32a43ae652eaa5b23dc06852938555cb8da1 +refs/heads/master: 4e5ea2088b699ae86ffd96b53b916a3966535fcb diff --git a/trunk/drivers/net/wireless/iwlegacy/common.c b/trunk/drivers/net/wireless/iwlegacy/common.c index 6dbd11f76f84..50308da8aee3 100644 --- a/trunk/drivers/net/wireless/iwlegacy/common.c +++ b/trunk/drivers/net/wireless/iwlegacy/common.c @@ -179,7 +179,6 @@ il_read_targ_mem(struct il_priv *il, u32 addr) _il_grab_nic_access(il); _il_wr(il, HBUS_TARG_MEM_RADDR, addr); - rmb(); value = _il_rd(il, HBUS_TARG_MEM_RDAT); _il_release_nic_access(il); @@ -196,7 +195,6 @@ il_write_targ_mem(struct il_priv *il, u32 addr, u32 val) spin_lock_irqsave(&il->reg_lock, reg_flags); if (likely(_il_grab_nic_access(il))) { _il_wr(il, HBUS_TARG_MEM_WADDR, addr); - wmb(); _il_wr(il, HBUS_TARG_MEM_WDAT, val); _il_release_nic_access(il); } diff --git a/trunk/drivers/net/wireless/iwlegacy/common.h b/trunk/drivers/net/wireless/iwlegacy/common.h index 1dfaa58acc45..df9b5b462839 100644 --- a/trunk/drivers/net/wireless/iwlegacy/common.h +++ b/trunk/drivers/net/wireless/iwlegacy/common.h @@ -2146,6 +2146,13 @@ static inline void _il_release_nic_access(struct il_priv *il) { _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + /* + * In above we are reading CSR_GP_CNTRL register, what will flush any + * previous writes, but still want write, which clear MAC_ACCESS_REQ + * bit, be performed on PCI bus before any other writes scheduled on + * different CPUs (after we drop reg_lock). + */ + mmiowb(); } static inline u32 @@ -2179,7 +2186,6 @@ static inline u32 _il_rd_prph(struct il_priv *il, u32 reg) { _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); - rmb(); return _il_rd(il, HBUS_TARG_PRPH_RDAT); } @@ -2187,7 +2193,6 @@ static inline void _il_wr_prph(struct il_priv *il, u32 addr, u32 val) { _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24))); - wmb(); _il_wr(il, HBUS_TARG_PRPH_WDAT, val); }