From 50a2a187754ac3a7af61f47102ae20a1df20d3a6 Mon Sep 17 00:00:00 2001
From: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Date: Sun, 30 Oct 2005 14:59:38 -0800
Subject: [PATCH] --- yaml --- r: 11763 b: refs/heads/master c:
 30037f66ce63b6b7ca1fbfb06605b831f4a60df6 h: refs/heads/master i:   11761:
 5d3e1ed65fb3a2e2659d8147c2b0d10523b1a736   11759:
 d77fb2d61537857b950157212600b8c7ebf5d399 v: v3

---
 [refs]                                       | 2 +-
 trunk/arch/i386/kernel/cpu/intel_cacheinfo.c | 8 +-------
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/[refs] b/[refs]
index 9ca6df50a88b..efdf059eb7a4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f014a556e714dfb02502e3be6146a39ca625f33c
+refs/heads/master: 30037f66ce63b6b7ca1fbfb06605b831f4a60df6
diff --git a/trunk/arch/i386/kernel/cpu/intel_cacheinfo.c b/trunk/arch/i386/kernel/cpu/intel_cacheinfo.c
index c802206274c2..7cc84a4a6df9 100644
--- a/trunk/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/trunk/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 		if ( l3 )
 			printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
 
-		/*
-		 * This assumes the L3 cache is shared; it typically lives in
-		 * the northbridge.  The L1 caches are included by the L2
-		 * cache, and so should not be included for the purpose of
-		 * SMP switching weights.
-		 */
-		c->x86_cache_size = l2 ? l2 : (l1i+l1d);
+		c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
 	}
 
 	return l2;