From 51e595adb0917206711e773515504cd1d2c946ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 10 Nov 2009 10:15:13 +0100 Subject: [PATCH] --- yaml --- r: 172475 b: refs/heads/master c: 27085f25184ee5a206706dd5f734ade1d15551fa h: refs/heads/master i: 172473: 8d8664d05e7166931e877c7aa3f1439d19ad8b9c 172471: d984dba953116642b5f62c2c33e8fedc6691086d v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-mxc/include/mach/mx21.h | 24 ++++++++++----------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/[refs] b/[refs] index c2da28306ac0..51af9eee1770 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 104071b6dcc66cd66db83231fd3bd58cd63e680d +refs/heads/master: 27085f25184ee5a206706dd5f734ade1d15551fa diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx21.h b/trunk/arch/arm/plat-mxc/include/mach/mx21.h index 21112c695ec5..2b1fccb748fb 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mx21.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mx21.h @@ -34,8 +34,8 @@ #define CS2_BASE_ADDR 0xD0000000 #define CS3_BASE_ADDR 0xD1000000 #define CS4_BASE_ADDR 0xD2000000 -#define CS5_BASE_ADDR 0xDD000000 #define PCMCIA_MEM_BASE_ADDR 0xD4000000 +#define CS5_BASE_ADDR 0xDD000000 /* NAND, SDRAM, WEIM etc controllers */ #define X_MEMC_BASE_ADDR 0xDF000000 @@ -50,21 +50,21 @@ #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ /* fixed interrupt numbers */ +#define MXC_INT_FIRI 9 +#define MXC_INT_BMI 30 +#define MXC_INT_EMMAENC 49 +#define MXC_INT_EMMADEC 50 +#define MXC_INT_USBWKUP 53 +#define MXC_INT_USBDMA 54 +#define MXC_INT_USBHOST 55 +#define MXC_INT_USBFUNC 56 +#define MXC_INT_USBMNP 57 #define MXC_INT_USBCTRL 58 #define MXC_INT_USBCTRL 58 -#define MXC_INT_USBMNP 57 -#define MXC_INT_USBFUNC 56 -#define MXC_INT_USBHOST 55 -#define MXC_INT_USBDMA 54 -#define MXC_INT_USBWKUP 53 -#define MXC_INT_EMMADEC 50 -#define MXC_INT_EMMAENC 49 -#define MXC_INT_BMI 30 -#define MXC_INT_FIRI 9 /* fixed DMA request numbers */ -#define DMA_REQ_BMI_RX 29 -#define DMA_REQ_BMI_TX 28 #define DMA_REQ_FIRI_RX 4 +#define DMA_REQ_BMI_TX 28 +#define DMA_REQ_BMI_RX 29 #endif /* __ASM_ARCH_MXC_MX21_H__ */