From 51e7a9f09fc0ba9654813a33fb8d24832f4d44c4 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 26 Apr 2010 22:23:42 +0200 Subject: [PATCH] --- yaml --- r: 196483 b: refs/heads/master c: a1e9ada3e148dc300fdd25705bd3ac024897dc68 h: refs/heads/master i: 196481: faa162f89d92eeb9b3f67b38211d9a78415cdf3e 196479: a81a123f2a4c0479d10273a33240dadaefa62f0d v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/r300.c | 8 -------- trunk/drivers/gpu/drm/radeon/radeon_fence.c | 2 +- 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index 7dc708de7c4a..c8bf51ab3e20 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f2594933df9719bd2b0aaaa8ea9b2b850d6e1c42 +refs/heads/master: a1e9ada3e148dc300fdd25705bd3ac024897dc68 diff --git a/trunk/drivers/gpu/drm/radeon/r300.c b/trunk/drivers/gpu/drm/radeon/r300.c index bb005bff4b08..5d622cb39b33 100644 --- a/trunk/drivers/gpu/drm/radeon/r300.c +++ b/trunk/drivers/gpu/drm/radeon/r300.c @@ -445,14 +445,6 @@ int r300_asic_reset(struct radeon_device *rdev) mdelay(1); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); - /* reset MC */ - WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); - RREG32(R_0000F0_RBBM_SOFT_RESET); - mdelay(500); - WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - mdelay(1); - status = RREG32(R_000E40_RBBM_STATUS); - dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* restore PCI & busmastering */ pci_restore_state(rdev->pdev); r100_enable_bm(rdev); diff --git a/trunk/drivers/gpu/drm/radeon/radeon_fence.c b/trunk/drivers/gpu/drm/radeon/radeon_fence.c index 1b8b9cc271f2..b1f9a81b5d1d 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_fence.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_fence.c @@ -237,10 +237,10 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr) * as signaled for now */ rdev->gpu_lockup = true; - WREG32(rdev->fence_drv.scratch_reg, fence->seq); r = radeon_gpu_reset(rdev); if (r) return r; + WREG32(rdev->fence_drv.scratch_reg, fence->seq); rdev->gpu_lockup = false; } timeout = RADEON_FENCE_JIFFIES_TIMEOUT;