From 5225a04c786cb1df76363b46c9f3403027daae74 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 17 Oct 2008 15:41:26 -0700 Subject: [PATCH] --- yaml --- r: 117238 b: refs/heads/master c: 053d7f244a8739d96d316c77a97cd063804c8e35 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_irq.c | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index c37ba1f8e427..d1a82a2196f6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 35ad68c18148a18938ff4f40e945c9734e7d2265 +refs/heads/master: 053d7f244a8739d96d316c77a97cd063804c8e35 diff --git a/trunk/drivers/gpu/drm/i915/i915_irq.c b/trunk/drivers/gpu/drm/i915/i915_irq.c index 2cd853b2c562..ca55c40353a5 100644 --- a/trunk/drivers/gpu/drm/i915/i915_irq.c +++ b/trunk/drivers/gpu/drm/i915/i915_irq.c @@ -605,6 +605,15 @@ int i915_enable_vblank(struct drm_device *dev, int plane) } spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); + /* Enabling vblank events in IMR comes before PIPESTAT write, or + * there's a race where the PIPESTAT vblank bit gets set to 1, so + * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in + * ISR flashes to 1, but the IIR bit doesn't get set to 1 because + * IMR masks it. It doesn't ever get set after we clear the masking + * in IMR because the ISR bit is edge, not level-triggered, on the + * OR of PIPESTAT bits. + */ + i915_enable_irq(dev_priv, interrupt); pipestat = I915_READ(pipestat_reg); if (IS_I965G(dev)) pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE; @@ -615,7 +624,6 @@ int i915_enable_vblank(struct drm_device *dev, int plane) PIPE_VBLANK_INTERRUPT_STATUS); I915_WRITE(pipestat_reg, pipestat); (void) I915_READ(pipestat_reg); /* Posting read */ - i915_enable_irq(dev_priv, interrupt); spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); return 0;