From 53796a9dfc061632ebb51aa629ef7e007c32d7e0 Mon Sep 17 00:00:00 2001
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Date: Mon, 23 Apr 2012 01:31:49 -0700
Subject: [PATCH] --- yaml --- r: 308116 b: refs/heads/master c:
 6437626928467e81aa4a3087d88cd3f443b3e9ec h: refs/heads/master v: v3

---
 [refs]                             |  2 +-
 trunk/arch/arm/mach-tegra/common.c | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index c7cc8037bc05..b983f7892575 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8703612b0abb33e6daacc0f6b709a006ac85b285
+refs/heads/master: 6437626928467e81aa4a3087d88cd3f443b3e9ec
diff --git a/trunk/arch/arm/mach-tegra/common.c b/trunk/arch/arm/mach-tegra/common.c
index 22df10fb9972..1f762333937e 100644
--- a/trunk/arch/arm/mach-tegra/common.c
+++ b/trunk/arch/arm/mach-tegra/common.c
@@ -93,6 +93,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
 };
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "clk_m",	NULL,		0,		true },
+	{ "pll_p",	"clk_m",	408000000,	true },
+	{ "pll_p_out1",	"pll_p",	9600000,	true },
+	{ NULL,		NULL,		0,		0},
+};
+#endif
+
+
 static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -127,6 +138,7 @@ void __init tegra30_init_early(void)
 {
 	tegra_init_fuse();
 	tegra30_init_clocks();
+	tegra_clk_init_from_table(tegra30_clk_init_table);
 	tegra_init_cache(0x441, 0x551);
 	tegra_pmc_init();
 	tegra_powergate_init();