From 5453aedf1bec9c0ccd5476a3ac9d030ba1240b25 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 27 Aug 2007 15:29:35 +0800 Subject: [PATCH] --- yaml --- r: 65999 b: refs/heads/master c: 07bdda02623d6d9078e45f6b6451bc3508878db1 h: refs/heads/master i: 65997: 3edc45ed808e396343ec73bf0b7841b2f542e01c 65995: 572e2ab3314105e7a86ab7d767a7d481a0d51ee0 65991: 2f99e2e8b11b9643d28788f1d6f66050cb9f2036 65983: c4e7f6eceda6b347405fcb1468df51261a945e6c v: v3 --- [refs] | 2 +- trunk/include/asm-blackfin/cplb.h | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 4ad9a7c046b2..2f99ee9b27fa 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3bebca2d20796dd3dc62c5d3e74148087c7ce5bd +refs/heads/master: 07bdda02623d6d9078e45f6b6451bc3508878db1 diff --git a/trunk/include/asm-blackfin/cplb.h b/trunk/include/asm-blackfin/cplb.h index c9fc77684fb2..df4766892767 100644 --- a/trunk/include/asm-blackfin/cplb.h +++ b/trunk/include/asm-blackfin/cplb.h @@ -65,27 +65,33 @@ #define MAX_CPLBS (16 * 2) +#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) + /* * Number of required data CPLB switchtable entries * MEMSIZE / 4 (we mostly install 4M page size CPLBs * approx 16 for smaller 1MB page size CPLBs for allignment purposes * 1 for L1 Data Memory +* possibly 1 for L2 Data Memory * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO * 1 for ASYNC Memory */ -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) /* * Number of required instruction CPLB switchtable entries * MEMSIZE / 4 (we mostly install 4M page size CPLBs * approx 12 for smaller 1MB page size CPLBs for allignment purposes * 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO */ -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) #define CPLB_ENABLE_ICACHE_P 0