From 54a15d9d57c61315839e54a0ae6030f26921dc47 Mon Sep 17 00:00:00 2001 From: Antonio Quartulli Date: Sat, 14 Apr 2012 13:15:27 +0200 Subject: [PATCH] --- yaml --- r: 300800 b: refs/heads/master c: 6d2003fc26e280001273d0b9dcc02b90f4536708 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/sparc/net/bpf_jit.h | 20 +- trunk/arch/sparc/net/bpf_jit_asm.S | 10 +- trunk/arch/sparc/net/bpf_jit_comp.c | 111 ++-- trunk/drivers/net/ethernet/dec/tulip/dmfe.c | 6 +- trunk/drivers/net/ethernet/realtek/r8169.c | 697 +++++--------------- trunk/net/batman-adv/translation-table.c | 2 +- trunk/net/core/sysctl_net_core.c | 2 +- trunk/net/ipv4/route.c | 2 +- 9 files changed, 215 insertions(+), 637 deletions(-) diff --git a/[refs] b/[refs] index 61b58fb7c073..c3441fe4330d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 798ec84d45754403571d6387396236e877965c5a +refs/heads/master: 6d2003fc26e280001273d0b9dcc02b90f4536708 diff --git a/trunk/arch/sparc/net/bpf_jit.h b/trunk/arch/sparc/net/bpf_jit.h index 33d6b375ff12..74f048be739c 100644 --- a/trunk/arch/sparc/net/bpf_jit.h +++ b/trunk/arch/sparc/net/bpf_jit.h @@ -4,14 +4,13 @@ /* Conventions: * %g1 : temporary * %g2 : Secondary temporary used by SKB data helper stubs. - * %g3 : packet offset passed into SKB data helper stubs. * %o0 : pointer to skb (first argument given to JIT function) * %o1 : BPF A accumulator * %o2 : BPF X accumulator * %o3 : Holds saved %o7 so we can call helper functions without needing * to allocate a register window. - * %o4 : skb->len - skb->data_len - * %o5 : skb->data + * %o4 : skb->data + * %o5 : skb->len - skb->data_len */ #ifndef __ASSEMBLER__ @@ -38,21 +37,6 @@ #define r_TMP G1 #define r_TMP2 G2 #define r_OFF G3 - -/* assembly code in arch/sparc/net/bpf_jit_asm.S */ -extern u32 bpf_jit_load_word[]; -extern u32 bpf_jit_load_half[]; -extern u32 bpf_jit_load_byte[]; -extern u32 bpf_jit_load_byte_msh[]; -extern u32 bpf_jit_load_word_positive_offset[]; -extern u32 bpf_jit_load_half_positive_offset[]; -extern u32 bpf_jit_load_byte_positive_offset[]; -extern u32 bpf_jit_load_byte_msh_positive_offset[]; -extern u32 bpf_jit_load_word_negative_offset[]; -extern u32 bpf_jit_load_half_negative_offset[]; -extern u32 bpf_jit_load_byte_negative_offset[]; -extern u32 bpf_jit_load_byte_msh_negative_offset[]; - #else #define r_SKB %o0 #define r_A %o1 diff --git a/trunk/arch/sparc/net/bpf_jit_asm.S b/trunk/arch/sparc/net/bpf_jit_asm.S index 9d016c7017f7..fdc69324aabc 100644 --- a/trunk/arch/sparc/net/bpf_jit_asm.S +++ b/trunk/arch/sparc/net/bpf_jit_asm.S @@ -30,7 +30,7 @@ bpf_jit_load_word_positive_offset: bne load_word_unaligned nop retl - ld [r_TMP], r_A + ld [r_SKB_DATA + r_OFF], r_A load_word_unaligned: ldub [r_TMP + 0x0], r_OFF ldub [r_TMP + 0x1], r_TMP2 @@ -59,7 +59,7 @@ bpf_jit_load_half_positive_offset: bne load_half_unaligned nop retl - lduh [r_TMP], r_A + lduh [r_SKB_DATA + r_OFF], r_A load_half_unaligned: ldub [r_TMP + 0x0], r_OFF ldub [r_TMP + 0x1], r_TMP2 @@ -195,11 +195,5 @@ bpf_jit_load_byte_msh_negative_offset: sll r_OFF, 2, r_X bpf_error: - /* Make the JIT program return zero. The JIT epilogue - * stores away the original %o7 into r_saved_O7. The - * normal leaf function return is to use "retl" which - * would evalute to "jmpl %o7 + 8, %g0" but we want to - * use the saved value thus the sequence you see here. - */ jmpl r_saved_O7 + 8, %g0 clr %o0 diff --git a/trunk/arch/sparc/net/bpf_jit_comp.c b/trunk/arch/sparc/net/bpf_jit_comp.c index 1a69244e785b..86349cab60c5 100644 --- a/trunk/arch/sparc/net/bpf_jit_comp.c +++ b/trunk/arch/sparc/net/bpf_jit_comp.c @@ -11,6 +11,20 @@ int bpf_jit_enable __read_mostly; +/* assembly code in arch/sparc/net/bpf_jit_asm.S */ +extern u32 bpf_jit_load_word[]; +extern u32 bpf_jit_load_half[]; +extern u32 bpf_jit_load_byte[]; +extern u32 bpf_jit_load_byte_msh[]; +extern u32 bpf_jit_load_word_positive_offset[]; +extern u32 bpf_jit_load_half_positive_offset[]; +extern u32 bpf_jit_load_byte_positive_offset[]; +extern u32 bpf_jit_load_byte_msh_positive_offset[]; +extern u32 bpf_jit_load_word_negative_offset[]; +extern u32 bpf_jit_load_half_negative_offset[]; +extern u32 bpf_jit_load_byte_negative_offset[]; +extern u32 bpf_jit_load_byte_msh_negative_offset[]; + static inline bool is_simm13(unsigned int value) { return value + 0x1000 < 0x2000; @@ -51,22 +65,22 @@ static void bpf_flush_icache(void *start_, void *end_) #define F2(X, Y) (OP(X) | OP2(Y)) #define F3(X, Y) (OP(X) | OP3(Y)) -#define CONDN COND(0x0) -#define CONDE COND(0x1) -#define CONDLE COND(0x2) -#define CONDL COND(0x3) -#define CONDLEU COND(0x4) -#define CONDCS COND(0x5) -#define CONDNEG COND(0x6) -#define CONDVC COND(0x7) -#define CONDA COND(0x8) -#define CONDNE COND(0x9) -#define CONDG COND(0xa) -#define CONDGE COND(0xb) -#define CONDGU COND(0xc) -#define CONDCC COND(0xd) -#define CONDPOS COND(0xe) -#define CONDVS COND(0xf) +#define CONDN COND (0x0) +#define CONDE COND (0x1) +#define CONDLE COND (0x2) +#define CONDL COND (0x3) +#define CONDLEU COND (0x4) +#define CONDCS COND (0x5) +#define CONDNEG COND (0x6) +#define CONDVC COND (0x7) +#define CONDA COND (0x8) +#define CONDNE COND (0x9) +#define CONDG COND (0xa) +#define CONDGE COND (0xb) +#define CONDGU COND (0xc) +#define CONDCC COND (0xd) +#define CONDPOS COND (0xe) +#define CONDVS COND (0xf) #define CONDGEU CONDCC #define CONDLU CONDCS @@ -158,7 +172,7 @@ do { /* sethi %hi(K), REG */ \ /* Emit * - * OP r_A, r_X, r_A + * OP r_A, r_X, r_A */ #define emit_alu_X(OPCODE) \ do { \ @@ -181,7 +195,7 @@ do { \ * is zero. */ #define emit_alu_K(OPCODE, K) \ -do { \ +do { \ if (K) { \ unsigned int _insn = OPCODE; \ _insn |= RS1(r_A) | RD(r_A); \ @@ -190,7 +204,7 @@ do { \ } else { \ emit_set_const(K, r_TMP); \ *prog++ = _insn | RS2(r_TMP); \ - } \ + } \ } \ } while (0) @@ -208,37 +222,39 @@ do { \ do { unsigned int _off = offsetof(STRUCT, FIELD); \ BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \ *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \ -} while (0) +} while(0) #define emit_load32(BASE, STRUCT, FIELD, DEST) \ do { unsigned int _off = offsetof(STRUCT, FIELD); \ BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \ *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \ -} while (0) +} while(0) #define emit_load16(BASE, STRUCT, FIELD, DEST) \ do { unsigned int _off = offsetof(STRUCT, FIELD); \ BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \ *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \ -} while (0) +} while(0) #define __emit_load8(BASE, STRUCT, FIELD, DEST) \ do { unsigned int _off = offsetof(STRUCT, FIELD); \ *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \ -} while (0) +} while(0) #define emit_load8(BASE, STRUCT, FIELD, DEST) \ do { BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8)); \ __emit_load8(BASE, STRUCT, FIELD, DEST); \ -} while (0) +} while(0) #define emit_ldmem(OFF, DEST) \ do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST); \ -} while (0) +} while(0) #define emit_stmem(OFF, SRC) \ do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC); \ -} while (0) +} while(0) + +#define cpu_off offsetof(struct thread_info, cpu) #ifdef CONFIG_SMP #ifdef CONFIG_SPARC64 @@ -276,16 +292,16 @@ do { void *_here = image + addrs[i] - 8; \ #define emit_branch(BR_OPC, DEST) \ do { unsigned int _here = addrs[i] - 8; \ *prog++ = BR_OPC | WDISP22((DEST) - _here); \ -} while (0) +} while(0) #define emit_branch_off(BR_OPC, OFF) \ do { *prog++ = BR_OPC | WDISP22(OFF); \ -} while (0) +} while(0) #define emit_jump(DEST) emit_branch(BA, DEST) -#define emit_read_y(REG) *prog++ = RD_Y | RD(REG) -#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0) +#define emit_read_y(REG) *prog++ = RD_Y | RD(REG); +#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0); #define emit_cmp(R1, R2) \ *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0)) @@ -317,35 +333,6 @@ do { *prog++ = BR_OPC | WDISP22(OFF); \ #define emit_release_stack(SZ) \ *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP)) -/* A note about branch offset calculations. The addrs[] array, - * indexed by BPF instruction, records the address after all the - * sparc instructions emitted for that BPF instruction. - * - * The most common case is to emit a branch at the end of such - * a code sequence. So this would be two instructions, the - * branch and it's delay slot. - * - * Therefore by default the branch emitters calculate the branch - * offset field as: - * - * destination - (addrs[i] - 8) - * - * This "addrs[i] - 8" is the address of the branch itself or - * what "." would be in assembler notation. The "8" part is - * how we take into consideration the branch and it's delay - * slot mentioned above. - * - * Sometimes we need to emit a branch earlier in the code - * sequence. And in these situations we adjust "destination" - * to accomodate this difference. For example, if we needed - * to emit a branch (and it's delay slot) right before the - * final instruction emitted for a BPF opcode, we'd use - * "destination + 4" instead of just plain "destination" above. - * - * This is why you see all of these funny emit_branch() and - * emit_jump() calls with adjusted offsets. - */ - void bpf_jit_compile(struct sk_filter *fp) { unsigned int cleanup_addr, proglen, oldproglen = 0; @@ -391,7 +378,7 @@ void bpf_jit_compile(struct sk_filter *fp) emit_clear(r_X); /* If this filter needs to access skb data, - * load %o4 and %o5 with: + * load %o4 and %o4 with: * %o4 = skb->len - skb->data_len * %o5 = skb->data * And also back up %o7 into r_saved_O7 so we can @@ -506,10 +493,6 @@ void bpf_jit_compile(struct sk_filter *fp) } emit_write_y(G0); #ifdef CONFIG_SPARC32 - /* The Sparc v8 architecture requires - * three instructions between a %y - * register write and the first use. - */ emit_nop(); emit_nop(); emit_nop(); diff --git a/trunk/drivers/net/ethernet/dec/tulip/dmfe.c b/trunk/drivers/net/ethernet/dec/tulip/dmfe.c index 4d6fe604fa64..0ef5b68acd05 100644 --- a/trunk/drivers/net/ethernet/dec/tulip/dmfe.c +++ b/trunk/drivers/net/ethernet/dec/tulip/dmfe.c @@ -767,7 +767,7 @@ static int dmfe_stop(struct DEVICE *dev) /* Reset & stop DM910X board */ dw32(DCR0, DM910X_RESET); - udelay(100); + udelay(5); phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); /* free interrupt */ @@ -1601,9 +1601,7 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset) int i; dw32(DCR9, CR9_SROM_READ); - udelay(5); dw32(DCR9, CR9_SROM_READ | CR9_SRCS); - udelay(5); /* Send the Read Command 110b */ srom_clk_write(ioaddr, SROM_DATA_1); @@ -1617,7 +1615,6 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset) } dw32(DCR9, CR9_SROM_READ | CR9_SRCS); - udelay(5); for (i = 16; i > 0; i--) { dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); @@ -1629,7 +1626,6 @@ static u16 read_srom_word(void __iomem *ioaddr, int offset) } dw32(DCR9, CR9_SROM_READ); - udelay(5); return srom_data; } diff --git a/trunk/drivers/net/ethernet/realtek/r8169.c b/trunk/drivers/net/ethernet/realtek/r8169.c index 00628d84342f..71393ea8ef51 100644 --- a/trunk/drivers/net/ethernet/realtek/r8169.c +++ b/trunk/drivers/net/ethernet/realtek/r8169.c @@ -44,8 +44,6 @@ #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" -#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" -#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" #ifdef RTL8169_DEBUG #define assert(expr) \ @@ -135,8 +133,6 @@ enum mac_version { RTL_GIGA_MAC_VER_34, RTL_GIGA_MAC_VER_35, RTL_GIGA_MAC_VER_36, - RTL_GIGA_MAC_VER_37, - RTL_GIGA_MAC_VER_38, RTL_GIGA_MAC_NONE = 0xff, }; @@ -249,12 +245,6 @@ static const struct { [RTL_GIGA_MAC_VER_36] = _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K, false), - [RTL_GIGA_MAC_VER_37] = - _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, - JUMBO_1K, true), - [RTL_GIGA_MAC_VER_38] = - _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, - JUMBO_9K, false), }; #undef _R @@ -325,8 +315,6 @@ enum rtl_registers { Config0 = 0x51, Config1 = 0x52, Config2 = 0x53, -#define PME_SIGNAL (1 << 5) /* 8168c and later */ - Config3 = 0x54, Config4 = 0x55, Config5 = 0x56, @@ -367,9 +355,6 @@ enum rtl8168_8101_registers { #define CSIAR_BYTE_ENABLE 0x0f #define CSIAR_BYTE_ENABLE_SHIFT 12 #define CSIAR_ADDR_MASK 0x0fff -#define CSIAR_FUNC_CARD 0x00000000 -#define CSIAR_FUNC_SDIO 0x00010000 -#define CSIAR_FUNC_NIC 0x00020000 PMCH = 0x6f, EPHYAR = 0x80, #define EPHYAR_FLAG 0x80000000 @@ -731,11 +716,6 @@ struct rtl8169_private { void (*disable)(struct rtl8169_private *); } jumbo_ops; - struct csi_ops { - void (*write)(void __iomem *, int, int); - u32 (*read)(void __iomem *, int); - } csi_ops; - int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); int (*get_settings)(struct net_device *, struct ethtool_cmd *); void (*phy_reset_enable)(struct rtl8169_private *tp); @@ -788,8 +768,6 @@ MODULE_FIRMWARE(FIRMWARE_8168E_3); MODULE_FIRMWARE(FIRMWARE_8105E_1); MODULE_FIRMWARE(FIRMWARE_8168F_1); MODULE_FIRMWARE(FIRMWARE_8168F_2); -MODULE_FIRMWARE(FIRMWARE_8402_1); -MODULE_FIRMWARE(FIRMWARE_8411_1); static void rtl_lock_work(struct rtl8169_private *tp) { @@ -1100,6 +1078,40 @@ static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) return value; } +static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) +{ + unsigned int i; + + RTL_W32(CSIDR, value); + RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | + CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); + + for (i = 0; i < 100; i++) { + if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) + break; + udelay(10); + } +} + +static u32 rtl_csi_read(void __iomem *ioaddr, int addr) +{ + u32 value = ~0x00; + unsigned int i; + + RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | + CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); + + for (i = 0; i < 100; i++) { + if (RTL_R32(CSIAR) & CSIAR_FLAG) { + value = RTL_R32(CSIDR); + break; + } + udelay(10); + } + + return value; +} + static void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) { @@ -1269,8 +1281,7 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp) if (!netif_running(dev)) return; - if (tp->mac_version == RTL_GIGA_MAC_VER_34 || - tp->mac_version == RTL_GIGA_MAC_VER_38) { + if (tp->mac_version == RTL_GIGA_MAC_VER_34) { if (RTL_R8(PHYstatus) & _1000bpsF) { rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, 0x00000011, ERIAR_EXGMAC); @@ -1305,16 +1316,6 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp) rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, 0x0000003f, ERIAR_EXGMAC); } - } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { - if (RTL_R8(PHYstatus) & _10bps) { - rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011, - 0x4d02, ERIAR_EXGMAC); - rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011, - 0x0060, ERIAR_EXGMAC); - } else { - rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011, - 0x0000, ERIAR_EXGMAC); - } } } @@ -1395,6 +1396,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) u16 reg; u8 mask; } cfg[] = { + { WAKE_ANY, Config1, PMEnable }, { WAKE_PHY, Config3, LinkUp }, { WAKE_MAGIC, Config3, MagicPacket }, { WAKE_UCAST, Config5, UWF }, @@ -1402,32 +1404,16 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) { WAKE_MCAST, Config5, MWF }, { WAKE_ANY, Config5, LanWake } }; - u8 options; RTL_W8(Cfg9346, Cfg9346_Unlock); for (i = 0; i < ARRAY_SIZE(cfg); i++) { - options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; + u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; if (wolopts & cfg[i].opt) options |= cfg[i].mask; RTL_W8(cfg[i].reg, options); } - switch (tp->mac_version) { - case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: - options = RTL_R8(Config1) & ~PMEnable; - if (wolopts) - options |= PMEnable; - RTL_W8(Config1, options); - break; - default: - options = RTL_R8(Config2) & ~PME_SIGNAL; - if (wolopts) - options |= PME_SIGNAL; - RTL_W8(Config2, options); - break; - } - RTL_W8(Cfg9346, Cfg9346_Lock); } @@ -1891,7 +1877,6 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, int mac_version; } mac_info[] = { /* 8168F family. */ - { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, @@ -1929,7 +1914,6 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, /* 8101 family. */ - { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, @@ -3030,28 +3014,6 @@ static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) -{ - /* For 4-corner performance improve */ - rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b80); - rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); - rtl_writephy(tp, 0x1f, 0x0000); - - /* PHY auto speed down */ - rtl_writephy(tp, 0x1f, 0x0007); - rtl_writephy(tp, 0x1e, 0x002d); - rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); - rtl_writephy(tp, 0x1f, 0x0000); - rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); - - /* Improve 10M EEE waveform */ - rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b86); - rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); - rtl_writephy(tp, 0x1f, 0x0000); -} - static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { @@ -3093,117 +3055,53 @@ static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - rtl8168f_hw_phy_config(tp); - - /* Improve 2-pair detection performance */ + /* For 4-corner performance improve */ rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b85); - rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); + rtl_writephy(tp, 0x05, 0x8b80); + rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); rtl_writephy(tp, 0x1f, 0x0000); -} - -static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) -{ - rtl_apply_firmware(tp); - - rtl8168f_hw_phy_config(tp); -} - -static void rtl8411_hw_phy_config(struct rtl8169_private *tp) -{ - void __iomem *ioaddr = tp->mmio_addr; - static const struct phy_reg phy_reg_init[] = { - /* Channel estimation fine tune */ - { 0x1f, 0x0003 }, - { 0x09, 0xa20f }, - { 0x1f, 0x0000 }, - - /* Modify green table for giga & fnet */ - { 0x1f, 0x0005 }, - { 0x05, 0x8b55 }, - { 0x06, 0x0000 }, - { 0x05, 0x8b5e }, - { 0x06, 0x0000 }, - { 0x05, 0x8b67 }, - { 0x06, 0x0000 }, - { 0x05, 0x8b70 }, - { 0x06, 0x0000 }, - { 0x1f, 0x0000 }, - { 0x1f, 0x0007 }, - { 0x1e, 0x0078 }, - { 0x17, 0x0000 }, - { 0x19, 0x00aa }, - { 0x1f, 0x0000 }, - /* Modify green table for 10M */ - { 0x1f, 0x0005 }, - { 0x05, 0x8b79 }, - { 0x06, 0xaa00 }, - { 0x1f, 0x0000 }, - - /* Disable hiimpedance detection (RTCT) */ - { 0x1f, 0x0003 }, - { 0x01, 0x328a }, - { 0x1f, 0x0000 } - }; - - - rtl_apply_firmware(tp); + /* PHY auto speed down */ + rtl_writephy(tp, 0x1f, 0x0007); + rtl_writephy(tp, 0x1e, 0x002d); + rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); - rtl8168f_hw_phy_config(tp); + /* Improve 10M EEE waveform */ + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b86); + rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); /* Improve 2-pair detection performance */ rtl_writephy(tp, 0x1f, 0x0005); rtl_writephy(tp, 0x05, 0x8b85); rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); rtl_writephy(tp, 0x1f, 0x0000); +} - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - - /* Modify green table for giga */ - rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b54); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); - rtl_writephy(tp, 0x05, 0x8b5d); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); - rtl_writephy(tp, 0x05, 0x8a7c); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); - rtl_writephy(tp, 0x05, 0x8a7f); - rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000); - rtl_writephy(tp, 0x05, 0x8a82); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); - rtl_writephy(tp, 0x05, 0x8a85); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); - rtl_writephy(tp, 0x05, 0x8a88); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); - rtl_writephy(tp, 0x1f, 0x0000); +static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) +{ + rtl_apply_firmware(tp); - /* uc same-seed solution */ + /* For 4-corner performance improve */ rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b85); - rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000); + rtl_writephy(tp, 0x05, 0x8b80); + rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); rtl_writephy(tp, 0x1f, 0x0000); - /* eee setting */ - rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); - rtl_writephy(tp, 0x1f, 0x0005); - rtl_writephy(tp, 0x05, 0x8b85); - rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); - rtl_writephy(tp, 0x1f, 0x0004); + /* PHY auto speed down */ rtl_writephy(tp, 0x1f, 0x0007); - rtl_writephy(tp, 0x1e, 0x0020); - rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); + rtl_writephy(tp, 0x1e, 0x002d); + rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); rtl_writephy(tp, 0x1f, 0x0000); - rtl_writephy(tp, 0x0d, 0x0007); - rtl_writephy(tp, 0x0e, 0x003c); - rtl_writephy(tp, 0x0d, 0x4007); - rtl_writephy(tp, 0x0e, 0x0000); - rtl_writephy(tp, 0x0d, 0x0000); + rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); - /* Green feature */ - rtl_writephy(tp, 0x1f, 0x0003); - rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); - rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); + /* Improve 10M EEE waveform */ + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x8b86); + rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); rtl_writephy(tp, 0x1f, 0x0000); } @@ -3250,25 +3148,6 @@ static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8402_hw_phy_config(struct rtl8169_private *tp) -{ - void __iomem *ioaddr = tp->mmio_addr; - - /* Disable ALDPS before setting firmware */ - rtl_writephy(tp, 0x1f, 0x0000); - rtl_writephy(tp, 0x18, 0x0310); - msleep(20); - - rtl_apply_firmware(tp); - - /* EEE setting */ - rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); - rtl_writephy(tp, 0x1f, 0x0004); - rtl_writephy(tp, 0x10, 0x401f); - rtl_writephy(tp, 0x19, 0x7030); - rtl_writephy(tp, 0x1f, 0x0000); -} - static void rtl_hw_phy_config(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); @@ -3357,14 +3236,6 @@ static void rtl_hw_phy_config(struct net_device *dev) rtl8168f_2_hw_phy_config(tp); break; - case RTL_GIGA_MAC_VER_37: - rtl8402_hw_phy_config(tp); - break; - - case RTL_GIGA_MAC_VER_38: - rtl8411_hw_phy_config(tp); - break; - default: break; } @@ -3602,8 +3473,6 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: case RTL_GIGA_MAC_VER_34: - case RTL_GIGA_MAC_VER_37: - case RTL_GIGA_MAC_VER_38: RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); break; @@ -3639,45 +3508,15 @@ static void r810x_phy_power_up(struct rtl8169_private *tp) static void r810x_pll_power_down(struct rtl8169_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - if (rtl_wol_pll_power_down(tp)) return; r810x_phy_power_down(tp); - - switch (tp->mac_version) { - case RTL_GIGA_MAC_VER_07: - case RTL_GIGA_MAC_VER_08: - case RTL_GIGA_MAC_VER_09: - case RTL_GIGA_MAC_VER_10: - case RTL_GIGA_MAC_VER_13: - case RTL_GIGA_MAC_VER_16: - break; - default: - RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); - break; - } } static void r810x_pll_power_up(struct rtl8169_private *tp) { - void __iomem *ioaddr = tp->mmio_addr; - r810x_phy_power_up(tp); - - switch (tp->mac_version) { - case RTL_GIGA_MAC_VER_07: - case RTL_GIGA_MAC_VER_08: - case RTL_GIGA_MAC_VER_09: - case RTL_GIGA_MAC_VER_10: - case RTL_GIGA_MAC_VER_13: - case RTL_GIGA_MAC_VER_16: - break; - default: - RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); - break; - } } static void r8168_phy_power_up(struct rtl8169_private *tp) @@ -3781,6 +3620,13 @@ static void r8168_pll_power_up(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; + if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || + tp->mac_version == RTL_GIGA_MAC_VER_28 || + tp->mac_version == RTL_GIGA_MAC_VER_31) && + r8168dp_check_dash(tp)) { + return; + } + switch (tp->mac_version) { case RTL_GIGA_MAC_VER_25: case RTL_GIGA_MAC_VER_26: @@ -3825,7 +3671,6 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_16: case RTL_GIGA_MAC_VER_29: case RTL_GIGA_MAC_VER_30: - case RTL_GIGA_MAC_VER_37: ops->down = r810x_pll_power_down; ops->up = r810x_pll_power_up; break; @@ -3850,7 +3695,6 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_34: case RTL_GIGA_MAC_VER_35: case RTL_GIGA_MAC_VER_36: - case RTL_GIGA_MAC_VER_38: ops->down = r8168_pll_power_down; ops->up = r8168_pll_power_up; break; @@ -4136,9 +3980,7 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) udelay(20); } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || tp->mac_version == RTL_GIGA_MAC_VER_35 || - tp->mac_version == RTL_GIGA_MAC_VER_36 || - tp->mac_version == RTL_GIGA_MAC_VER_37 || - tp->mac_version == RTL_GIGA_MAC_VER_38) { + tp->mac_version == RTL_GIGA_MAC_VER_36) { RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) udelay(100); @@ -4344,141 +4186,22 @@ static void rtl_hw_start_8169(struct net_device *dev) RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); } -static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) -{ - if (tp->csi_ops.write) - tp->csi_ops.write(tp->mmio_addr, addr, value); -} - -static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) -{ - if (tp->csi_ops.read) - return tp->csi_ops.read(tp->mmio_addr, addr); - else - return ~0; -} - -static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) +static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) { u32 csi; - csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; - rtl_csi_write(tp, 0x070c, csi | bits); -} - -static void rtl_csi_access_enable_1(struct rtl8169_private *tp) -{ - rtl_csi_access_enable(tp, 0x17000000); -} - -static void rtl_csi_access_enable_2(struct rtl8169_private *tp) -{ - rtl_csi_access_enable(tp, 0x27000000); -} - -static void r8169_csi_write(void __iomem *ioaddr, int addr, int value) -{ - unsigned int i; - - RTL_W32(CSIDR, value); - RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | - CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); - - for (i = 0; i < 100; i++) { - if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) - break; - udelay(10); - } -} - -static u32 r8169_csi_read(void __iomem *ioaddr, int addr) -{ - u32 value = ~0x00; - unsigned int i; - - RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | - CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); - - for (i = 0; i < 100; i++) { - if (RTL_R32(CSIAR) & CSIAR_FLAG) { - value = RTL_R32(CSIDR); - break; - } - udelay(10); - } - - return value; -} - -static void r8402_csi_write(void __iomem *ioaddr, int addr, int value) -{ - unsigned int i; - - RTL_W32(CSIDR, value); - RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | - CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | - CSIAR_FUNC_NIC); - - for (i = 0; i < 100; i++) { - if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) - break; - udelay(10); - } + csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; + rtl_csi_write(ioaddr, 0x070c, csi | bits); } -static u32 r8402_csi_read(void __iomem *ioaddr, int addr) +static void rtl_csi_access_enable_1(void __iomem *ioaddr) { - u32 value = ~0x00; - unsigned int i; - - RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | - CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); - - for (i = 0; i < 100; i++) { - if (RTL_R32(CSIAR) & CSIAR_FLAG) { - value = RTL_R32(CSIDR); - break; - } - udelay(10); - } - - return value; + rtl_csi_access_enable(ioaddr, 0x17000000); } -static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp) +static void rtl_csi_access_enable_2(void __iomem *ioaddr) { - struct csi_ops *ops = &tp->csi_ops; - - switch (tp->mac_version) { - case RTL_GIGA_MAC_VER_01: - case RTL_GIGA_MAC_VER_02: - case RTL_GIGA_MAC_VER_03: - case RTL_GIGA_MAC_VER_04: - case RTL_GIGA_MAC_VER_05: - case RTL_GIGA_MAC_VER_06: - case RTL_GIGA_MAC_VER_10: - case RTL_GIGA_MAC_VER_11: - case RTL_GIGA_MAC_VER_12: - case RTL_GIGA_MAC_VER_13: - case RTL_GIGA_MAC_VER_14: - case RTL_GIGA_MAC_VER_15: - case RTL_GIGA_MAC_VER_16: - case RTL_GIGA_MAC_VER_17: - ops->write = NULL; - ops->read = NULL; - break; - - case RTL_GIGA_MAC_VER_37: - case RTL_GIGA_MAC_VER_38: - ops->write = r8402_csi_write; - ops->read = r8402_csi_read; - break; - - default: - ops->write = r8169_csi_write; - ops->read = r8169_csi_read; - break; - } + rtl_csi_access_enable(ioaddr, 0x27000000); } struct ephy_info { @@ -4535,11 +4258,8 @@ static void rtl_enable_clock_request(struct pci_dev *pdev) PktCntrDisable | \ Mac_dbgo_sel) -static void rtl_hw_start_8168bb(struct rtl8169_private *tp) +static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); @@ -4548,22 +4268,17 @@ static void rtl_hw_start_8168bb(struct rtl8169_private *tp) (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); } -static void rtl_hw_start_8168bef(struct rtl8169_private *tp) +static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - - rtl_hw_start_8168bb(tp); + rtl_hw_start_8168bb(ioaddr, pdev); RTL_W8(MaxTxPacketSize, TxPacketMax); RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); } -static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) +static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - RTL_W8(Config1, RTL_R8(Config1) | Speed_down); RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); @@ -4575,9 +4290,8 @@ static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); } -static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) +static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; static const struct ephy_info e_info_8168cp[] = { { 0x01, 0, 0x0001 }, { 0x02, 0x0800, 0x1000 }, @@ -4586,19 +4300,16 @@ static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) { 0x07, 0, 0x2000 } }; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); - __rtl_hw_start_8168cp(tp); + __rtl_hw_start_8168cp(ioaddr, pdev); } -static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) +static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); @@ -4607,12 +4318,9 @@ static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); } -static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) +static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); @@ -4626,57 +4334,52 @@ static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); } -static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) +static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; static const struct ephy_info e_info_8168c_1[] = { { 0x02, 0x0800, 0x1000 }, { 0x03, 0, 0x0002 }, { 0x06, 0x0080, 0x0000 } }; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); - __rtl_hw_start_8168cp(tp); + __rtl_hw_start_8168cp(ioaddr, pdev); } -static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) +static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; static const struct ephy_info e_info_8168c_2[] = { { 0x01, 0, 0x0001 }, { 0x03, 0x0400, 0x0220 } }; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); - __rtl_hw_start_8168cp(tp); + __rtl_hw_start_8168cp(ioaddr, pdev); } -static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) +static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) { - rtl_hw_start_8168c_2(tp); + rtl_hw_start_8168c_2(ioaddr, pdev); } -static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) +static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) { - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); - __rtl_hw_start_8168cp(tp); + __rtl_hw_start_8168cp(ioaddr, pdev); } -static void rtl_hw_start_8168d(struct rtl8169_private *tp) +static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); rtl_disable_clock_request(pdev); @@ -4687,12 +4390,9 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp) RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); } -static void rtl_hw_start_8168dp(struct rtl8169_private *tp) +static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - - rtl_csi_access_enable_1(tp); + rtl_csi_access_enable_1(ioaddr); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -4701,10 +4401,8 @@ static void rtl_hw_start_8168dp(struct rtl8169_private *tp) rtl_disable_clock_request(pdev); } -static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) +static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8168d_4[] = { { 0x0b, ~0, 0x48 }, { 0x19, 0x20, 0x50 }, @@ -4712,7 +4410,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) }; int i; - rtl_csi_access_enable_1(tp); + rtl_csi_access_enable_1(ioaddr); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -4729,10 +4427,8 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) rtl_enable_clock_request(pdev); } -static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) +static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8168e_1[] = { { 0x00, 0x0200, 0x0100 }, { 0x00, 0x0000, 0x0004 }, @@ -4749,7 +4445,7 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) { 0x0a, 0x0000, 0x0040 } }; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); @@ -4766,16 +4462,14 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); } -static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) +static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8168e_2[] = { { 0x09, 0x0000, 0x0080 }, { 0x19, 0x0000, 0x0224 } }; - rtl_csi_access_enable_1(tp); + rtl_csi_access_enable_1(ioaddr); rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); @@ -4806,12 +4500,18 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); } -static void rtl_hw_start_8168f(struct rtl8169_private *tp) +static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; + static const struct ephy_info e_info_8168f_1[] = { + { 0x06, 0x00c0, 0x0020 }, + { 0x08, 0x0001, 0x0002 }, + { 0x09, 0x0000, 0x0080 }, + { 0x19, 0x0000, 0x0224 } + }; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_1(ioaddr); + + rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -4825,6 +4525,8 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); + rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, + ERIAR_EXGMAC); RTL_W8(MaxTxPacketSize, EarlySize); @@ -4832,54 +4534,20 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); - RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); - RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); - RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); -} - -static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) -{ - void __iomem *ioaddr = tp->mmio_addr; - static const struct ephy_info e_info_8168f_1[] = { - { 0x06, 0x00c0, 0x0020 }, - { 0x08, 0x0001, 0x0002 }, - { 0x09, 0x0000, 0x0080 }, - { 0x19, 0x0000, 0x0224 } - }; - - rtl_hw_start_8168f(tp); - - rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); - - rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, - ERIAR_EXGMAC); /* Adjust EEE LED frequency */ RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); -} - -static void rtl_hw_start_8411(struct rtl8169_private *tp) -{ - void __iomem *ioaddr = tp->mmio_addr; - static const struct ephy_info e_info_8168f_1[] = { - { 0x06, 0x00c0, 0x0020 }, - { 0x0f, 0xffff, 0x5200 }, - { 0x1e, 0x0000, 0x4000 }, - { 0x19, 0x0000, 0x0224 } - }; - - rtl_hw_start_8168f(tp); - rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); - - rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, - ERIAR_EXGMAC); + RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); + RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); + RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); } static void rtl_hw_start_8168(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); void __iomem *ioaddr = tp->mmio_addr; + struct pci_dev *pdev = tp->pci_dev; RTL_W8(Cfg9346, Cfg9346_Unlock); @@ -4910,71 +4578,67 @@ static void rtl_hw_start_8168(struct net_device *dev) switch (tp->mac_version) { case RTL_GIGA_MAC_VER_11: - rtl_hw_start_8168bb(tp); + rtl_hw_start_8168bb(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_12: case RTL_GIGA_MAC_VER_17: - rtl_hw_start_8168bef(tp); + rtl_hw_start_8168bef(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_18: - rtl_hw_start_8168cp_1(tp); + rtl_hw_start_8168cp_1(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_19: - rtl_hw_start_8168c_1(tp); + rtl_hw_start_8168c_1(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_20: - rtl_hw_start_8168c_2(tp); + rtl_hw_start_8168c_2(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_21: - rtl_hw_start_8168c_3(tp); + rtl_hw_start_8168c_3(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_22: - rtl_hw_start_8168c_4(tp); + rtl_hw_start_8168c_4(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_23: - rtl_hw_start_8168cp_2(tp); + rtl_hw_start_8168cp_2(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_24: - rtl_hw_start_8168cp_3(tp); + rtl_hw_start_8168cp_3(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_25: case RTL_GIGA_MAC_VER_26: case RTL_GIGA_MAC_VER_27: - rtl_hw_start_8168d(tp); + rtl_hw_start_8168d(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_28: - rtl_hw_start_8168d_4(tp); + rtl_hw_start_8168d_4(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_31: - rtl_hw_start_8168dp(tp); + rtl_hw_start_8168dp(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: - rtl_hw_start_8168e_1(tp); + rtl_hw_start_8168e_1(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_34: - rtl_hw_start_8168e_2(tp); + rtl_hw_start_8168e_2(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_35: case RTL_GIGA_MAC_VER_36: - rtl_hw_start_8168f_1(tp); - break; - - case RTL_GIGA_MAC_VER_38: - rtl_hw_start_8411(tp); + rtl_hw_start_8168f_1(ioaddr, pdev); break; default: @@ -5001,10 +4665,8 @@ static void rtl_hw_start_8168(struct net_device *dev) PktCntrDisable | \ Mac_dbgo_sel) -static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) +static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8102e_1[] = { { 0x01, 0, 0x6e65 }, { 0x02, 0, 0x091f }, @@ -5017,7 +4679,7 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) }; u8 cfg1; - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); RTL_W8(DBG_REG, FIX_NAK_1); @@ -5034,12 +4696,9 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); } -static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) +static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - struct pci_dev *pdev = tp->pci_dev; - - rtl_csi_access_enable_2(tp); + rtl_csi_access_enable_2(ioaddr); rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); @@ -5047,16 +4706,15 @@ static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); } -static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) +static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) { - rtl_hw_start_8102e_2(tp); + rtl_hw_start_8102e_2(ioaddr, pdev); - rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9); + rtl_ephy_write(ioaddr, 0x03, 0xc2f9); } -static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) +static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; static const struct ephy_info e_info_8105e_1[] = { { 0x07, 0, 0x4000 }, { 0x19, 0, 0x0200 }, @@ -5080,44 +4738,12 @@ static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); } -static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) +static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) { - void __iomem *ioaddr = tp->mmio_addr; - - rtl_hw_start_8105e_1(tp); + rtl_hw_start_8105e_1(ioaddr, pdev); rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); } -static void rtl_hw_start_8402(struct rtl8169_private *tp) -{ - void __iomem *ioaddr = tp->mmio_addr; - static const struct ephy_info e_info_8402[] = { - { 0x19, 0xffff, 0xff64 }, - { 0x1e, 0, 0x4000 } - }; - - rtl_csi_access_enable_2(tp); - - /* Force LAN exit from ASPM if Rx/Tx are not idle */ - RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); - - RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); - RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); - - rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402)); - - rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); - - rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); - rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); - rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); - rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); - rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); - rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); - rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, - ERIAR_EXGMAC); -} - static void rtl_hw_start_8101(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); @@ -5141,26 +4767,22 @@ static void rtl_hw_start_8101(struct net_device *dev) switch (tp->mac_version) { case RTL_GIGA_MAC_VER_07: - rtl_hw_start_8102e_1(tp); + rtl_hw_start_8102e_1(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_08: - rtl_hw_start_8102e_3(tp); + rtl_hw_start_8102e_3(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_09: - rtl_hw_start_8102e_2(tp); + rtl_hw_start_8102e_2(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_29: - rtl_hw_start_8105e_1(tp); + rtl_hw_start_8105e_1(ioaddr, pdev); break; case RTL_GIGA_MAC_VER_30: - rtl_hw_start_8105e_2(tp); - break; - - case RTL_GIGA_MAC_VER_37: - rtl_hw_start_8402(tp); + rtl_hw_start_8105e_2(ioaddr, pdev); break; } @@ -6557,7 +6179,6 @@ rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) rtl_init_mdio_ops(tp); rtl_init_pll_power_ops(tp); rtl_init_jumbo_ops(tp); - rtl_init_csi_ops(tp); rtl8169_print_mac_version(tp); diff --git a/trunk/net/batman-adv/translation-table.c b/trunk/net/batman-adv/translation-table.c index e16a3690bdb2..a38d315d3cd6 100644 --- a/trunk/net/batman-adv/translation-table.c +++ b/trunk/net/batman-adv/translation-table.c @@ -1339,7 +1339,7 @@ static int send_tt_request(struct bat_priv *bat_priv, memcpy(tt_request->dst, dst_orig_node->orig, ETH_ALEN); tt_request->header.ttl = TTL; tt_request->ttvn = ttvn; - tt_request->tt_data = tt_crc; + tt_request->tt_data = htons(tt_crc); tt_request->flags = TT_REQUEST; if (full_table) diff --git a/trunk/net/core/sysctl_net_core.c b/trunk/net/core/sysctl_net_core.c index cee599190261..0c2850874254 100644 --- a/trunk/net/core/sysctl_net_core.c +++ b/trunk/net/core/sysctl_net_core.c @@ -256,7 +256,7 @@ static __init int sysctl_core_init(void) { static struct ctl_table empty[1]; - kmemleak_not_leak(register_sysctl_paths(net_core_path, empty)); + register_sysctl_paths(net_core_path, empty); register_net_sysctl_rotable(net_core_path, net_core_table); return register_pernet_subsys(&sysctl_core_ops); } diff --git a/trunk/net/ipv4/route.c b/trunk/net/ipv4/route.c index bcd4744e0e4e..ac4d6b3fa9c9 100644 --- a/trunk/net/ipv4/route.c +++ b/trunk/net/ipv4/route.c @@ -3514,6 +3514,6 @@ int __init ip_rt_init(void) */ void __init ip_static_sysctl_init(void) { - kmemleak_not_leak(register_sysctl_paths(ipv4_path, ipv4_skeleton)); + register_sysctl_paths(ipv4_path, ipv4_skeleton); } #endif