From 54fb139e3ada5f1e1385d3ddfbaca1af785378dc Mon Sep 17 00:00:00 2001
From: Michael Chan <mchan@broadcom.com>
Date: Tue, 28 Aug 2007 15:39:42 -0700
Subject: [PATCH] --- yaml --- r: 64591 b: refs/heads/master c:
 594a9dfae7113d9601b2c353754c40d0b7e00a03 h: refs/heads/master i:   64589:
 e00493c1617fedc015d6daaab1292c9d37252d77   64587:
 14c3165c0ef6eb225102b826bf7aef93072bace8   64583:
 79222b0b428dcb7331ecb4a547255b33d77342d7   64575:
 e74a23dbea1e43175f63e901f7c66e5a5c2860d8 v: v3

---
 [refs]                   | 2 +-
 trunk/drivers/net/bnx2.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 7557d27972f7..72b2af703133 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8e54588161577435d64dfb5cfdf40a73a5705ea0
+refs/heads/master: 594a9dfae7113d9601b2c353754c40d0b7e00a03
diff --git a/trunk/drivers/net/bnx2.c b/trunk/drivers/net/bnx2.c
index 00918602ba88..854d80c330ec 100644
--- a/trunk/drivers/net/bnx2.c
+++ b/trunk/drivers/net/bnx2.c
@@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
 		/* Chip reset. */
 		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
 
+		/* Reading back any register after chip reset will hang the
+		 * bus on 5706 A0 and A1.  The msleep below provides plenty
+		 * of margin for write posting.
+		 */
 		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
 		    (CHIP_ID(bp) == CHIP_ID_5706_A1))
 			msleep(20);