From 5524dc6ff3af04acf0907e220177862c3c6eaa92 Mon Sep 17 00:00:00 2001
From: Wolfgang Grandegger <wg@grandegger.com>
Date: Sun, 17 Aug 2008 10:51:25 +0200
Subject: [PATCH] --- yaml --- r: 109132 b: refs/heads/master c:
 d27a736c7a62c3451e389aa8e0dfc64dab119b9b h: refs/heads/master v: v3

---
 [refs]                                           | 2 +-
 trunk/arch/powerpc/boot/dts/tqm8548-bigflash.dts | 8 +++++++-
 trunk/arch/powerpc/boot/dts/tqm8548.dts          | 3 ++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index edcc04483624..2a6facb0b078 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ba1616d921429ffe7480e8835e85f95ff041add8
+refs/heads/master: d27a736c7a62c3451e389aa8e0dfc64dab119b9b
diff --git a/trunk/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/trunk/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 64d2d5bbcdf1..4199e89b4e50 100644
--- a/trunk/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/trunk/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -50,13 +50,14 @@
 		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
 	};
 
-	soc8548@a0000000 {
+	soc@a0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
 		ranges = <0x0 0xa0000000 0x100000>;
 		reg = <0xa0000000 0x1000>;	// CCSRBAR
 		bus-frequency = <0>;
+		compatible = "fsl,mpc8548-immr", "simple-bus";
 
 		memory-controller@2000 {
 			compatible = "fsl,mpc8548-memory-controller";
@@ -83,6 +84,11 @@
 			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
+
+			rtc@68 {
+				compatible = "dallas,ds1337";
+				reg = <0x68>;
+			};
 		};
 
 		i2c@3100 {
diff --git a/trunk/arch/powerpc/boot/dts/tqm8548.dts b/trunk/arch/powerpc/boot/dts/tqm8548.dts
index 2563112cabd3..58ee4185454b 100644
--- a/trunk/arch/powerpc/boot/dts/tqm8548.dts
+++ b/trunk/arch/powerpc/boot/dts/tqm8548.dts
@@ -50,13 +50,14 @@
 		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
 	};
 
-	soc8548@e0000000 {
+	soc@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
 		ranges = <0x0 0xe0000000 0x100000>;
 		reg = <0xe0000000 0x1000>;	// CCSRBAR
 		bus-frequency = <0>;
+		compatible = "fsl,mpc8548-immr", "simple-bus";
 
 		memory-controller@2000 {
 			compatible = "fsl,mpc8548-memory-controller";