From 5526735c8dd79c247fb948a08d542563f918ab37 Mon Sep 17 00:00:00 2001
From: Herbert Xu ~{PmVHI~} <herbert@gondor.apana.org.au>
Date: Mon, 5 Jun 2006 15:03:37 -0700
Subject: [PATCH] --- yaml --- r: 27146 b: refs/heads/master c:
 f291196979ca80cdef199ca2b55e2758e8c23a0d h: refs/heads/master v: v3

---
 [refs]                                        |  2 +-
 trunk/MAINTAINERS                             |  5 --
 trunk/arch/arm/Kconfig.debug                  |  2 +-
 trunk/arch/arm/mach-ixp4xx/Kconfig            |  2 +-
 trunk/arch/arm/mach-pxa/mainstone.c           |  1 -
 trunk/arch/arm/mach-s3c2410/Kconfig           |  2 +-
 trunk/arch/mips/au1000/common/prom.c          | 24 +++++---
 trunk/arch/mips/au1000/common/sleeper.S       |  5 --
 trunk/arch/mips/ddb5xxx/ddb5476/dbg_io.c      |  2 +-
 trunk/arch/mips/ddb5xxx/ddb5477/kgdb_io.c     |  2 +-
 trunk/arch/mips/gt64120/ev64120/serialGT.c    |  2 +-
 .../arch/mips/gt64120/momenco_ocelot/dbg_io.c |  2 +-
 trunk/arch/mips/ite-boards/generic/dbg_io.c   |  2 +-
 trunk/arch/mips/kernel/cpu-bugs64.c           |  8 +--
 trunk/arch/mips/kernel/cpu-probe.c            |  2 +-
 trunk/arch/mips/kernel/module.c               |  6 --
 trunk/arch/mips/kernel/scall64-o32.S          |  2 +-
 trunk/arch/mips/kernel/setup.c                | 18 +++---
 trunk/arch/mips/kernel/smp.c                  |  5 +-
 trunk/arch/mips/kernel/syscall.c              |  3 +-
 trunk/arch/mips/kernel/traps.c                | 19 +-----
 trunk/arch/mips/math-emu/dp_fint.c            |  4 +-
 trunk/arch/mips/math-emu/dp_flong.c           |  4 +-
 trunk/arch/mips/math-emu/sp_fint.c            |  4 +-
 trunk/arch/mips/math-emu/sp_flong.c           |  4 +-
 trunk/arch/mips/mm/c-r4k.c                    | 34 -----------
 trunk/arch/mips/mm/init.c                     |  2 +-
 trunk/arch/mips/momentum/jaguar_atx/dbg_io.c  |  2 +-
 trunk/arch/mips/momentum/ocelot_c/dbg_io.c    |  2 +-
 trunk/arch/mips/momentum/ocelot_g/dbg_io.c    |  2 +-
 trunk/arch/mips/oprofile/common.c             |  8 +--
 trunk/arch/mips/oprofile/op_model_mipsxx.c    | 32 +++++-----
 trunk/arch/mips/oprofile/op_model_rm9000.c    |  2 +-
 trunk/arch/mips/sgi-ip32/ip32-irq.c           |  4 +-
 trunk/drivers/mmc/Kconfig                     |  2 +-
 .../include/asm-arm/arch-l7200/serial_l7200.h |  2 +-
 trunk/include/asm-arm/arch-l7200/uncompress.h |  2 +-
 trunk/include/asm-mips/addrspace.h            |  1 -
 trunk/include/asm-mips/delay.h                | 22 +++----
 trunk/include/asm-mips/page.h                 |  2 -
 trunk/include/asm-mips/pgtable-32.h           | 61 +++++++------------
 trunk/include/asm-mips/pgtable-64.h           | 13 ++--
 trunk/include/asm-mips/pgtable.h              |  5 +-
 trunk/include/asm-mips/smp.h                  |  5 +-
 trunk/include/asm-mips/sparsemem.h            | 14 -----
 trunk/net/ipv4/tcp_output.c                   | 12 ++--
 46 files changed, 126 insertions(+), 235 deletions(-)
 delete mode 100644 trunk/include/asm-mips/sparsemem.h

diff --git a/[refs] b/[refs]
index b904e0ed1a65..19ae79f287be 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a8c725045eb2eaa6c28a5493cb193f47a5c4afe4
+refs/heads/master: f291196979ca80cdef199ca2b55e2758e8c23a0d
diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS
index c3c5842402df..141c22269eba 100644
--- a/trunk/MAINTAINERS
+++ b/trunk/MAINTAINERS
@@ -1889,11 +1889,6 @@ L:	linux-kernel@vger.kernel.org
 W:	http://www.atnf.csiro.au/~rgooch/linux/kernel-patches.html
 S:	Maintained
 
-MULTIMEDIA CARD SUBSYSTEM
-P:	Russell King
-M:	rmk+mmc@arm.linux.org.uk
-S:	Maintained
-
 MULTISOUND SOUND DRIVER
 P:	Andrew Veliath
 M:	andrewtv@usa.net
diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug
index d22f38b957db..5d3acff8c596 100644
--- a/trunk/arch/arm/Kconfig.debug
+++ b/trunk/arch/arm/Kconfig.debug
@@ -101,7 +101,7 @@ config DEBUG_S3C2410_UART
 	help
 	  Choice for UART for kernel low-level using S3C2410 UARTS,
 	  should be between zero and two. The port must have been
-	  initialised by the boot-loader before use.
+	  initalised by the boot-loader before use.
 
 	  The uncompressor code port configuration is now handled
 	  by CONFIG_S3C2410_LOWLEVEL_UART_PORT.
diff --git a/trunk/arch/arm/mach-ixp4xx/Kconfig b/trunk/arch/arm/mach-ixp4xx/Kconfig
index 3b23f43cb160..2a39f9e481ad 100644
--- a/trunk/arch/arm/mach-ixp4xx/Kconfig
+++ b/trunk/arch/arm/mach-ixp4xx/Kconfig
@@ -141,7 +141,7 @@ config IXP4XX_INDIRECT_PCI
           2) If > 64MB of memory space is required, the IXP4xx can be 
 	     configured to use indirect registers to access PCI This allows 
 	     for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 
-	     The disadvantage of this is that every PCI access requires 
+	     The disadvantadge of this is that every PCI access requires 
 	     three local register accesses plus a spinlock, but in some 
 	     cases the performance hit is acceptable. In addition, you cannot 
 	     mmap() PCI devices in this case due to the indirect nature
diff --git a/trunk/arch/arm/mach-pxa/mainstone.c b/trunk/arch/arm/mach-pxa/mainstone.c
index b307f11951df..02e188d98e7d 100644
--- a/trunk/arch/arm/mach-pxa/mainstone.c
+++ b/trunk/arch/arm/mach-pxa/mainstone.c
@@ -493,7 +493,6 @@ static void __init mainstone_map_io(void)
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
 	/* Maintainer: MontaVista Software Inc. */
 	.phys_io	= 0x40000000,
-	.boot_params	= 0xa0000100,	/* BLOB boot parameter setting */
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= mainstone_map_io,
 	.init_irq	= mainstone_init_irq,
diff --git a/trunk/arch/arm/mach-s3c2410/Kconfig b/trunk/arch/arm/mach-s3c2410/Kconfig
index 970f98dadffc..ce7d81000695 100644
--- a/trunk/arch/arm/mach-s3c2410/Kconfig
+++ b/trunk/arch/arm/mach-s3c2410/Kconfig
@@ -170,7 +170,7 @@ config S3C2410_PM_DEBUG
 	depends on ARCH_S3C2410 && PM
 	help
 	  Say Y here if you want verbose debugging from the PM Suspend and
-	  Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+	  Resume code. See `Documentation/arm/Samsing-S3C24XX/Suspend.txt`
 	  for more information.
 
 config S3C2410_PM_CHECK
diff --git a/trunk/arch/mips/au1000/common/prom.c b/trunk/arch/mips/au1000/common/prom.c
index ae7d8c57bf3f..9c171afd9a53 100644
--- a/trunk/arch/mips/au1000/common/prom.c
+++ b/trunk/arch/mips/au1000/common/prom.c
@@ -1,9 +1,10 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *    PROM library initialisation code, assuming YAMON is the boot loader.
+ *    PROM library initialisation code, assuming a version of
+ *    pmon is the boot code.
  *
- * Copyright 2000, 2001, 2006 MontaVista Software Inc.
+ * Copyright 2000,2001 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *         	ppopov@mvista.com or source@mvista.com
  *
@@ -48,9 +49,9 @@ extern char **prom_argv, **prom_envp;
 
 typedef struct
 {
-	char *name;
-	char *val;
-} t_env_var;
+    char *name;
+/*    char *val; */
+}t_env_var;
 
 
 char * prom_getcmdline(void)
@@ -84,16 +85,21 @@ char *prom_getenv(char *envname)
 {
 	/*
 	 * Return a pointer to the given environment variable.
+	 * Environment variables are stored in the form of "memsize=64".
 	 */
 
 	t_env_var *env = (t_env_var *)prom_envp;
+	int i;
+
+	i = strlen(envname);
 
-	while (env->name) {
-		if (strcmp(envname, env->name) == 0)
-			return env->val;
+	while(env->name) {
+		if(strncmp(envname, env->name, i) == 0) {
+			return(env->name + strlen(envname) + 1);
+		}
 		env++;
 	}
-	return NULL;
+	return(NULL);
 }
 
 inline unsigned char str2hexnum(unsigned char c)
diff --git a/trunk/arch/mips/au1000/common/sleeper.S b/trunk/arch/mips/au1000/common/sleeper.S
index 683d9da84b66..44dac3b0df3b 100644
--- a/trunk/arch/mips/au1000/common/sleeper.S
+++ b/trunk/arch/mips/au1000/common/sleeper.S
@@ -112,11 +112,6 @@ sdsleep:
 	mtc0	k0, CP0_PAGEMASK
 	lw	k0, 0x14(sp)
 	mtc0	k0, CP0_CONFIG
-
-	/* We need to catch the ealry Alchemy SOCs with
-	 * the write-only Config[OD] bit and set it back to one...
-	 */
-	jal	au1x00_fixup_config_od
 	lw	$1, PT_R1(sp)
 	lw	$2, PT_R2(sp)
 	lw	$3, PT_R3(sp)
diff --git a/trunk/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/trunk/arch/mips/ddb5xxx/ddb5476/dbg_io.c
index f2296a999953..85e9e5013679 100644
--- a/trunk/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+++ b/trunk/arch/mips/ddb5xxx/ddb5476/dbg_io.c
@@ -86,7 +86,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up baud rate */
+        /* set up buad rate */
         {
                 uint32 divisor;
 
diff --git a/trunk/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/trunk/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
index 385bbdb10170..1d18d590495b 100644
--- a/trunk/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
+++ b/trunk/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
@@ -86,7 +86,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up baud rate */
+        /* set up buad rate */
         {
                 uint32 divisor;
 
diff --git a/trunk/arch/mips/gt64120/ev64120/serialGT.c b/trunk/arch/mips/gt64120/ev64120/serialGT.c
index 8f0d835491ff..16e34a546e54 100644
--- a/trunk/arch/mips/gt64120/ev64120/serialGT.c
+++ b/trunk/arch/mips/gt64120/ev64120/serialGT.c
@@ -149,7 +149,7 @@ void serial_set(int channel, unsigned long baud)
 #else
 	/*
 	 * Note: Set baud rate, hardcoded here for rate of 115200
-	 * since became unsure of above "baud rate" algorithm (??).
+	 * since became unsure of above "buad rate" algorithm (??).
 	 */
 	outreg(channel, LCR, 0x83);
 	outreg(channel, DLM, 0x00);	// See note above
diff --git a/trunk/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/trunk/arch/mips/gt64120/momenco_ocelot/dbg_io.c
index f0a6a38fcf4d..8720bccfdea2 100644
--- a/trunk/arch/mips/gt64120/momenco_ocelot/dbg_io.c
+++ b/trunk/arch/mips/gt64120/momenco_ocelot/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 	/* disable interrupts */
 	UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up baud rate */
+	/* set up buad rate */
 	{
 		uint32 divisor;
 
diff --git a/trunk/arch/mips/ite-boards/generic/dbg_io.c b/trunk/arch/mips/ite-boards/generic/dbg_io.c
index 6a7ccaf93502..c4f8530fd07e 100644
--- a/trunk/arch/mips/ite-boards/generic/dbg_io.c
+++ b/trunk/arch/mips/ite-boards/generic/dbg_io.c
@@ -72,7 +72,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 	/* disable interrupts */
 	UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up baud rate */
+	/* set up buad rate */
 	{
 		uint32 divisor;
 
diff --git a/trunk/arch/mips/kernel/cpu-bugs64.c b/trunk/arch/mips/kernel/cpu-bugs64.c
index d268827c62bd..47a087b6c11b 100644
--- a/trunk/arch/mips/kernel/cpu-bugs64.c
+++ b/trunk/arch/mips/kernel/cpu-bugs64.c
@@ -206,7 +206,7 @@ static inline void check_daddi(void)
 		"daddi	%0, %1, %3\n\t"
 		".set	pop"
 		: "=r" (v), "=&r" (tmp)
-		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
+		: "I" (0xffffffffffffdb9a), "I" (0x1234));
 	set_except_vector(12, handler);
 	local_irq_restore(flags);
 
@@ -224,7 +224,7 @@ static inline void check_daddi(void)
 		"dsrl	%1, %1, 1\n\t"
 		"daddi	%0, %1, %3"
 		: "=r" (v), "=&r" (tmp)
-		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
+		: "I" (0xffffffffffffdb9a), "I" (0x1234));
 	set_except_vector(12, handler);
 	local_irq_restore(flags);
 
@@ -280,7 +280,7 @@ static inline void check_daddiu(void)
 		"daddu	%1, %2\n\t"
 		".set	pop"
 		: "=&r" (v), "=&r" (w), "=&r" (tmp)
-		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
+		: "I" (0xffffffffffffdb9a), "I" (0x1234));
 
 	if (v == w) {
 		printk("no.\n");
@@ -296,7 +296,7 @@ static inline void check_daddiu(void)
 		"addiu	%1, $0, %4\n\t"
 		"daddu	%1, %2"
 		: "=&r" (v), "=&r" (w), "=&r" (tmp)
-		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
+		: "I" (0xffffffffffffdb9a), "I" (0x1234));
 
 	if (v == w) {
 		printk("yes.\n");
diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c
index 8c2c359a05f4..bef3e2dc7c52 100644
--- a/trunk/arch/mips/kernel/cpu-probe.c
+++ b/trunk/arch/mips/kernel/cpu-probe.c
@@ -655,7 +655,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 	case PRID_IMP_SB1:
 		c->cputype = CPU_SB1;
 		/* FPU in pass1 is known to have issues. */
-		if ((c->processor_id & 0xff) < 0x02)
+		if ((c->processor_id & 0xff) < 0x20)
 			c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 		break;
 	case PRID_IMP_SB1A:
diff --git a/trunk/arch/mips/kernel/module.c b/trunk/arch/mips/kernel/module.c
index d7bf0215bc1d..e54a7f442f8a 100644
--- a/trunk/arch/mips/kernel/module.c
+++ b/trunk/arch/mips/kernel/module.c
@@ -288,9 +288,6 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
 		sym = (Elf_Sym *)sechdrs[symindex].sh_addr
 			+ ELF_MIPS_R_SYM(rel[i]);
 		if (!sym->st_value) {
-			/* Ignore unresolved weak symbol */
-			if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
-				continue;
 			printk(KERN_WARNING "%s: Unknown symbol %s\n",
 			       me->name, strtab + sym->st_name);
 			return -ENOENT;
@@ -328,9 +325,6 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
 		sym = (Elf_Sym *)sechdrs[symindex].sh_addr
 			+ ELF_MIPS_R_SYM(rel[i]);
 		if (!sym->st_value) {
-			/* Ignore unresolved weak symbol */
-			if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
-				continue;
 			printk(KERN_WARNING "%s: Unknown symbol %s\n",
 			       me->name, strtab + sym->st_name);
 			return -ENOENT;
diff --git a/trunk/arch/mips/kernel/scall64-o32.S b/trunk/arch/mips/kernel/scall64-o32.S
index 8efb23a84131..b53a9207f530 100644
--- a/trunk/arch/mips/kernel/scall64-o32.S
+++ b/trunk/arch/mips/kernel/scall64-o32.S
@@ -209,7 +209,7 @@ sys_call_table:
 	PTR	sys_fork
 	PTR	sys_read
 	PTR	sys_write
-	PTR	compat_sys_open			/* 4005 */
+	PTR	sys_open			/* 4005 */
 	PTR	sys_close
 	PTR	sys_waitpid
 	PTR	sys_creat
diff --git a/trunk/arch/mips/kernel/setup.c b/trunk/arch/mips/kernel/setup.c
index 397a70e651b5..bcf1b10e518f 100644
--- a/trunk/arch/mips/kernel/setup.c
+++ b/trunk/arch/mips/kernel/setup.c
@@ -246,7 +246,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en
 #ifdef CONFIG_64BIT
 	/* HACK: Guess if the sign extension was forgotten */
 	if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
-		start |= 0xffffffff00000000UL;
+		start |= 0xffffffff00000000;
 #endif
 
 	end = start + size;
@@ -355,6 +355,8 @@ static inline void bootmem_init(void)
 	}
 #endif
 
+	memory_present(0, first_usable_pfn, max_low_pfn);
+
 	/* Initialize the boot-time allocator with low memory only.  */
 	bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
 
@@ -408,7 +410,6 @@ static inline void bootmem_init(void)
 
 		/* Register lowmem ranges */
 		free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
-		memory_present(0, curr_pfn, curr_pfn + size - 1);
 	}
 
 	/* Reserve the bootmap memory.  */
@@ -418,20 +419,17 @@ static inline void bootmem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 	initrd_below_start_ok = 1;
 	if (initrd_start) {
-		unsigned long initrd_size = ((unsigned char *)initrd_end) -
-			((unsigned char *)initrd_start);
-		const int width = sizeof(long) * 2;
-
+		unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start);
 		printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
 		       (void *)initrd_start, initrd_size);
 
 		if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
 			printk("initrd extends beyond end of memory "
 			       "(0x%0*Lx > 0x%0*Lx)\ndisabling initrd\n",
-			       width,
-			       (unsigned long long) CPHYSADDR(initrd_end),
-			       width,
-			       (unsigned long long) PFN_PHYS(max_low_pfn));
+			       sizeof(long) * 2,
+			       (unsigned long long)CPHYSADDR(initrd_end),
+			       sizeof(long) * 2,
+			       (unsigned long long)PFN_PHYS(max_low_pfn));
 			initrd_start = initrd_end = 0;
 			initrd_reserve_bootmem = 0;
 		}
diff --git a/trunk/arch/mips/kernel/smp.c b/trunk/arch/mips/kernel/smp.c
index 298f82fe8440..d42f358754ad 100644
--- a/trunk/arch/mips/kernel/smp.c
+++ b/trunk/arch/mips/kernel/smp.c
@@ -247,9 +247,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	current_thread_info()->cpu = 0;
 	smp_tune_scheduling();
 	plat_prepare_cpus(max_cpus);
-#ifndef CONFIG_HOTPLUG_CPU
-	cpu_present_map = cpu_possible_map;
-#endif
 }
 
 /* preload SMP state for boot cpu */
@@ -445,7 +442,7 @@ static int __init topology_init(void)
 	int cpu;
 	int ret;
 
-	for_each_present_cpu(cpu) {
+	for_each_cpu(cpu) {
 		ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
 		if (ret)
 			printk(KERN_WARNING "topology_init: register_cpu %d "
diff --git a/trunk/arch/mips/kernel/syscall.c b/trunk/arch/mips/kernel/syscall.c
index 5e8a18a8e2bd..8f4fdd94dbd0 100644
--- a/trunk/arch/mips/kernel/syscall.c
+++ b/trunk/arch/mips/kernel/syscall.c
@@ -276,7 +276,8 @@ void sys_set_thread_area(unsigned long addr)
 
 asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
 {
-	int	tmp;
+	int	tmp, len;
+	char	__user *name;
 
 	switch(cmd) {
 	case MIPS_ATOMIC_SET:
diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c
index a7564b08eb4d..35cb08da3820 100644
--- a/trunk/arch/mips/kernel/traps.c
+++ b/trunk/arch/mips/kernel/traps.c
@@ -819,30 +819,15 @@ asmlinkage void do_watch(struct pt_regs *regs)
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
 {
-	const int field = 2 * sizeof(unsigned long);
-	int multi_match = regs->cp0_status & ST0_TS;
-
 	show_regs(regs);
-
-	if (multi_match) {
-		printk("Index   : %0x\n", read_c0_index());
-		printk("Pagemask: %0x\n", read_c0_pagemask());
-		printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
-		printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
-		printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
-		printk("\n");
-		dump_tlb_all();
-	}
-
-	show_code((unsigned int *) regs->cp0_epc);
-
+	dump_tlb_all();
 	/*
 	 * Some chips may have other causes of machine check (e.g. SB1
 	 * graduation timer)
 	 */
 	panic("Caught Machine Check exception - %scaused by multiple "
 	      "matching entries in the TLB.",
-	      (multi_match) ? "" : "not ");
+	      (regs->cp0_status & ST0_TS) ? "" : "not ");
 }
 
 asmlinkage void do_mt(struct pt_regs *regs)
diff --git a/trunk/arch/mips/math-emu/dp_fint.c b/trunk/arch/mips/math-emu/dp_fint.c
index 39a71de16f47..a1962eb460f8 100644
--- a/trunk/arch/mips/math-emu/dp_fint.c
+++ b/trunk/arch/mips/math-emu/dp_fint.c
@@ -29,9 +29,7 @@
 
 ieee754dp ieee754dp_fint(int x)
 {
-	u64 xm;
-	int xe;
-	int xs;
+	COMPXDP;
 
 	CLEARCX;
 
diff --git a/trunk/arch/mips/math-emu/dp_flong.c b/trunk/arch/mips/math-emu/dp_flong.c
index f08f223e488a..eae90a866aa1 100644
--- a/trunk/arch/mips/math-emu/dp_flong.c
+++ b/trunk/arch/mips/math-emu/dp_flong.c
@@ -29,9 +29,7 @@
 
 ieee754dp ieee754dp_flong(s64 x)
 {
-	u64 xm;
-	int xe;
-	int xs;
+	COMPXDP;
 
 	CLEARCX;
 
diff --git a/trunk/arch/mips/math-emu/sp_fint.c b/trunk/arch/mips/math-emu/sp_fint.c
index e88e125e01c2..7aac13afb09a 100644
--- a/trunk/arch/mips/math-emu/sp_fint.c
+++ b/trunk/arch/mips/math-emu/sp_fint.c
@@ -29,9 +29,7 @@
 
 ieee754sp ieee754sp_fint(int x)
 {
-	unsigned xm;
-	int xe;
-	int xs;
+	COMPXSP;
 
 	CLEARCX;
 
diff --git a/trunk/arch/mips/math-emu/sp_flong.c b/trunk/arch/mips/math-emu/sp_flong.c
index 26d6919a269a..3d6c1d11c178 100644
--- a/trunk/arch/mips/math-emu/sp_flong.c
+++ b/trunk/arch/mips/math-emu/sp_flong.c
@@ -29,9 +29,7 @@
 
 ieee754sp ieee754sp_flong(s64 x)
 {
-	u64 xm;		/* <--- need 64-bit mantissa temp */
-	int xe;
-	int xs;
+	COMPXDP;		/* <--- need 64-bit mantissa temp */
 
 	CLEARCX;
 
diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c
index 4a43924cd4fc..6b3541769602 100644
--- a/trunk/arch/mips/mm/c-r4k.c
+++ b/trunk/arch/mips/mm/c-r4k.c
@@ -1161,31 +1161,6 @@ static void __init setup_scache(void)
 	c->options |= MIPS_CPU_SUBSET_CACHES;
 }
 
-void au1x00_fixup_config_od(void)
-{
-	/*
-	 * c0_config.od (bit 19) was write only (and read as 0)
-	 * on the early revisions of Alchemy SOCs.  It disables the bus
-	 * transaction overlapping and needs to be set to fix various errata.
-	 */
-	switch (read_c0_prid()) {
-	case 0x00030100: /* Au1000 DA */
-	case 0x00030201: /* Au1000 HA */
-	case 0x00030202: /* Au1000 HB */
-	case 0x01030200: /* Au1500 AB */
-	/*
-	 * Au1100 errata actually keeps silence about this bit, so we set it
-	 * just in case for those revisions that require it to be set according
-	 * to arch/mips/au1000/common/cputable.c
-	 */
-	case 0x02030200: /* Au1100 AB */
-	case 0x02030201: /* Au1100 BA */
-	case 0x02030202: /* Au1100 BC */
-		set_c0_config(1 << 19);
-		break;
-	}
-}
-
 static inline void coherency_setup(void)
 {
 	change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1206,15 +1181,6 @@ static inline void coherency_setup(void)
 	case CPU_R4400MC:
 		clear_c0_config(CONF_CU);
 		break;
-	/*
-	 * We need to catch the ealry Alchemy SOCs with
-	 * the write-only co_config.od bit and set it back to one...
-	 */
-	case CPU_AU1000: /* rev. DA, HA, HB */
-	case CPU_AU1100: /* rev. AB, BA, BC ?? */
-	case CPU_AU1500: /* rev. AB */
-		au1x00_fixup_config_od();
-		break;
 	}
 }
 
diff --git a/trunk/arch/mips/mm/init.c b/trunk/arch/mips/mm/init.c
index 33f6e1cdfd5b..c22308b93ff0 100644
--- a/trunk/arch/mips/mm/init.c
+++ b/trunk/arch/mips/mm/init.c
@@ -227,7 +227,7 @@ void __init mem_init(void)
 	for (tmp = 0; tmp < max_low_pfn; tmp++)
 		if (page_is_ram(tmp)) {
 			ram++;
-			if (PageReserved(pfn_to_page(tmp)))
+			if (PageReserved(mem_map+tmp))
 				reservedpages++;
 		}
 
diff --git a/trunk/arch/mips/momentum/jaguar_atx/dbg_io.c b/trunk/arch/mips/momentum/jaguar_atx/dbg_io.c
index d7dea0a136aa..542eac82b63c 100644
--- a/trunk/arch/mips/momentum/jaguar_atx/dbg_io.c
+++ b/trunk/arch/mips/momentum/jaguar_atx/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 	/* disable interrupts */
 	UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up baud rate */
+	/* set up buad rate */
 	{
 		uint32 divisor;
 
diff --git a/trunk/arch/mips/momentum/ocelot_c/dbg_io.c b/trunk/arch/mips/momentum/ocelot_c/dbg_io.c
index f0a6a38fcf4d..8720bccfdea2 100644
--- a/trunk/arch/mips/momentum/ocelot_c/dbg_io.c
+++ b/trunk/arch/mips/momentum/ocelot_c/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 	/* disable interrupts */
 	UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up baud rate */
+	/* set up buad rate */
 	{
 		uint32 divisor;
 
diff --git a/trunk/arch/mips/momentum/ocelot_g/dbg_io.c b/trunk/arch/mips/momentum/ocelot_g/dbg_io.c
index f0a6a38fcf4d..8720bccfdea2 100644
--- a/trunk/arch/mips/momentum/ocelot_g/dbg_io.c
+++ b/trunk/arch/mips/momentum/ocelot_g/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 	/* disable interrupts */
 	UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-	/* set up baud rate */
+	/* set up buad rate */
 	{
 		uint32 divisor;
 
diff --git a/trunk/arch/mips/oprofile/common.c b/trunk/arch/mips/oprofile/common.c
index c31e4cff64e0..91b799d2cd88 100644
--- a/trunk/arch/mips/oprofile/common.c
+++ b/trunk/arch/mips/oprofile/common.c
@@ -14,8 +14,8 @@
 
 #include "op_impl.h"
 
-extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
-extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
+extern struct op_mips_model op_model_mipsxx __attribute__((weak));
+extern struct op_mips_model op_model_rm9000 __attribute__((weak));
 
 static struct op_mips_model *model;
 
@@ -83,11 +83,11 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 	case CPU_74K:
 	case CPU_SB1:
 	case CPU_SB1A:
-		lmodel = &op_model_mipsxx_ops;
+		lmodel = &op_model_mipsxx;
 		break;
 
 	case CPU_RM9000:
-		lmodel = &op_model_rm9000_ops;
+		lmodel = &op_model_rm9000;
 		break;
 	};
 
diff --git a/trunk/arch/mips/oprofile/op_model_mipsxx.c b/trunk/arch/mips/oprofile/op_model_mipsxx.c
index f26a00e13204..e7ce92391303 100644
--- a/trunk/arch/mips/oprofile/op_model_mipsxx.c
+++ b/trunk/arch/mips/oprofile/op_model_mipsxx.c
@@ -23,7 +23,7 @@
 
 #define M_COUNTER_OVERFLOW		(1UL    << 31)
 
-struct op_mips_model op_model_mipsxx_ops;
+struct op_mips_model op_model_mipsxx;
 
 static struct mipsxx_register_config {
 	unsigned int control[4];
@@ -34,7 +34,7 @@ static struct mipsxx_register_config {
 
 static void mipsxx_reg_setup(struct op_counter_config *ctr)
 {
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
+	unsigned int counters = op_model_mipsxx.num_counters;
 	int i;
 
 	/* Compute the performance counter control word.  */
@@ -62,7 +62,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
 
 static void mipsxx_cpu_setup (void *args)
 {
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
+	unsigned int counters = op_model_mipsxx.num_counters;
 
 	switch (counters) {
 	case 4:
@@ -83,7 +83,7 @@ static void mipsxx_cpu_setup (void *args)
 /* Start all counters on current CPU */
 static void mipsxx_cpu_start(void *args)
 {
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
+	unsigned int counters = op_model_mipsxx.num_counters;
 
 	switch (counters) {
 	case 4:
@@ -100,7 +100,7 @@ static void mipsxx_cpu_start(void *args)
 /* Stop all counters on current CPU */
 static void mipsxx_cpu_stop(void *args)
 {
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
+	unsigned int counters = op_model_mipsxx.num_counters;
 
 	switch (counters) {
 	case 4:
@@ -116,7 +116,7 @@ static void mipsxx_cpu_stop(void *args)
 
 static int mipsxx_perfcount_handler(struct pt_regs *regs)
 {
-	unsigned int counters = op_model_mipsxx_ops.num_counters;
+	unsigned int counters = op_model_mipsxx.num_counters;
 	unsigned int control;
 	unsigned int counter;
 	int handled = 0;
@@ -187,37 +187,37 @@ static int __init mipsxx_init(void)
 
 	reset_counters(counters);
 
-	op_model_mipsxx_ops.num_counters = counters;
+	op_model_mipsxx.num_counters = counters;
 	switch (current_cpu_data.cputype) {
 	case CPU_20KC:
-		op_model_mipsxx_ops.cpu_type = "mips/20K";
+		op_model_mipsxx.cpu_type = "mips/20K";
 		break;
 
 	case CPU_24K:
-		op_model_mipsxx_ops.cpu_type = "mips/24K";
+		op_model_mipsxx.cpu_type = "mips/24K";
 		break;
 
 	case CPU_25KF:
-		op_model_mipsxx_ops.cpu_type = "mips/25K";
+		op_model_mipsxx.cpu_type = "mips/25K";
 		break;
 
 #ifndef CONFIG_SMP
 	case CPU_34K:
-		op_model_mipsxx_ops.cpu_type = "mips/34K";
+		op_model_mipsxx.cpu_type = "mips/34K";
 		break;
 
 	case CPU_74K:
-		op_model_mipsxx_ops.cpu_type = "mips/74K";
+		op_model_mipsxx.cpu_type = "mips/74K";
 		break;
 #endif
 
 	case CPU_5KC:
-		op_model_mipsxx_ops.cpu_type = "mips/5K";
+		op_model_mipsxx.cpu_type = "mips/5K";
 		break;
 
 	case CPU_SB1:
 	case CPU_SB1A:
-		op_model_mipsxx_ops.cpu_type = "mips/sb1";
+		op_model_mipsxx.cpu_type = "mips/sb1";
 		break;
 
 	default:
@@ -233,12 +233,12 @@ static int __init mipsxx_init(void)
 
 static void mipsxx_exit(void)
 {
-	reset_counters(op_model_mipsxx_ops.num_counters);
+	reset_counters(op_model_mipsxx.num_counters);
 
 	perf_irq = null_perf_irq;
 }
 
-struct op_mips_model op_model_mipsxx_ops = {
+struct op_mips_model op_model_mipsxx = {
 	.reg_setup	= mipsxx_reg_setup,
 	.cpu_setup	= mipsxx_cpu_setup,
 	.init		= mipsxx_init,
diff --git a/trunk/arch/mips/oprofile/op_model_rm9000.c b/trunk/arch/mips/oprofile/op_model_rm9000.c
index b7063fefa65b..9b75e41c78ef 100644
--- a/trunk/arch/mips/oprofile/op_model_rm9000.c
+++ b/trunk/arch/mips/oprofile/op_model_rm9000.c
@@ -126,7 +126,7 @@ static void rm9000_exit(void)
 	free_irq(rm9000_perfcount_irq, NULL);
 }
 
-struct op_mips_model op_model_rm9000_ops = {
+struct op_mips_model op_model_rm9000 = {
 	.reg_setup	= rm9000_reg_setup,
 	.cpu_setup	= rm9000_cpu_setup,
 	.init		= rm9000_init,
diff --git a/trunk/arch/mips/sgi-ip32/ip32-irq.c b/trunk/arch/mips/sgi-ip32/ip32-irq.c
index 8ba08047d164..de01c9815bdd 100644
--- a/trunk/arch/mips/sgi-ip32/ip32-irq.c
+++ b/trunk/arch/mips/sgi-ip32/ip32-irq.c
@@ -31,12 +31,12 @@
 /* issue a PIO read to make sure no PIO writes are pending */
 static void inline flush_crime_bus(void)
 {
-	crime->control;
+	volatile unsigned long junk = crime->control;
 }
 
 static void inline flush_mace_bus(void)
 {
-	mace->perif.ctrl.misc;
+	volatile unsigned long junk = mace->perif.ctrl.misc;
 }
 
 #undef DEBUG_IRQ
diff --git a/trunk/drivers/mmc/Kconfig b/trunk/drivers/mmc/Kconfig
index 45bcf098e762..003b077c2324 100644
--- a/trunk/drivers/mmc/Kconfig
+++ b/trunk/drivers/mmc/Kconfig
@@ -84,7 +84,7 @@ config MMC_WBSD
 
 config MMC_AU1X
 	tristate "Alchemy AU1XX0 MMC Card Interface support"
-	depends on MMC && SOC_AU1200
+	depends on SOC_AU1X00 && MMC
 	help
 	  This selects the AMD Alchemy(R) Multimedia card interface.
 	  If you have a Alchemy platform with a MMC slot, say Y or M here.
diff --git a/trunk/include/asm-arm/arch-l7200/serial_l7200.h b/trunk/include/asm-arm/arch-l7200/serial_l7200.h
index b1008a9d23e5..238c595d97ea 100644
--- a/trunk/include/asm-arm/arch-l7200/serial_l7200.h
+++ b/trunk/include/asm-arm/arch-l7200/serial_l7200.h
@@ -28,7 +28,7 @@
 #define UARTDR			0x00	/* Tx/Rx data */
 #define RXSTAT			0x04	/* Rx status */
 #define H_UBRLCR		0x08	/* mode register high */
-#define M_UBRLCR		0x0C	/* mode reg mid (MSB of baud)*/
+#define M_UBRLCR		0x0C	/* mode reg mid (MSB of buad)*/
 #define L_UBRLCR		0x10	/* mode reg low (LSB of baud)*/
 #define UARTCON			0x14	/* control register */
 #define UARTFLG			0x18	/* flag register */
diff --git a/trunk/include/asm-arm/arch-l7200/uncompress.h b/trunk/include/asm-arm/arch-l7200/uncompress.h
index 04be2a088639..9fcd40aee3e3 100644
--- a/trunk/include/asm-arm/arch-l7200/uncompress.h
+++ b/trunk/include/asm-arm/arch-l7200/uncompress.h
@@ -6,7 +6,7 @@
  * Changelog:
  *  05-01-2000	SJH	Created
  *  05-13-2000	SJH	Filled in function bodies
- *  07-26-2000	SJH	Removed hard coded baud rate
+ *  07-26-2000	SJH	Removed hard coded buad rate
  */
 
 #include <asm/hardware.h>
diff --git a/trunk/include/asm-mips/addrspace.h b/trunk/include/asm-mips/addrspace.h
index 1386af1cb7d9..42520cc84b0f 100644
--- a/trunk/include/asm-mips/addrspace.h
+++ b/trunk/include/asm-mips/addrspace.h
@@ -129,7 +129,6 @@
 #if defined (CONFIG_CPU_R4300)						\
     || defined (CONFIG_CPU_R4X00)					\
     || defined (CONFIG_CPU_R5000)					\
-    || defined (CONFIG_CPU_RM7000)					\
     || defined (CONFIG_CPU_NEVADA)					\
     || defined (CONFIG_CPU_TX49XX)					\
     || defined (CONFIG_CPU_MIPS64)
diff --git a/trunk/include/asm-mips/delay.h b/trunk/include/asm-mips/delay.h
index 928f30f8c45c..64dd45150f64 100644
--- a/trunk/include/asm-mips/delay.h
+++ b/trunk/include/asm-mips/delay.h
@@ -19,22 +19,20 @@ static inline void __delay(unsigned long loops)
 {
 	if (sizeof(long) == 4)
 		__asm__ __volatile__ (
-		"	.set	noreorder				\n"
-		"	.align	3					\n"
-		"1:	bnez	%0, 1b					\n"
-		"	subu	%0, 1					\n"
-		"	.set	reorder					\n"
+		".set\tnoreorder\n"
+		"1:\tbnez\t%0,1b\n\t"
+		"subu\t%0,1\n\t"
+		".set\treorder"
 		: "=r" (loops)
 		: "0" (loops));
 	else if (sizeof(long) == 8)
 		__asm__ __volatile__ (
-		"	.set	noreorder				\n"
-		"	.align	3					\n"
-		"1:	bnez	%0, 1b					\n"
-		"	dsubu	%0, 1					\n"
-		"	.set	reorder					\n"
-		: "=r" (loops)
-		: "0" (loops));
+		".set\tnoreorder\n"
+		"1:\tbnez\t%0,1b\n\t"
+		"dsubu\t%0,1\n\t"
+		".set\treorder"
+		:"=r" (loops)
+		:"0" (loops));
 }
 
 
diff --git a/trunk/include/asm-mips/page.h b/trunk/include/asm-mips/page.h
index 4035ec79ecd4..a1eab136ff6c 100644
--- a/trunk/include/asm-mips/page.h
+++ b/trunk/include/asm-mips/page.h
@@ -139,11 +139,9 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
 
-#ifndef CONFIG_SPARSEMEM
 #ifndef CONFIG_NEED_MULTIPLE_NODES
 #define pfn_valid(pfn)		((pfn) < max_mapnr)
 #endif
-#endif
 
 #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/trunk/include/asm-mips/pgtable-32.h b/trunk/include/asm-mips/pgtable-32.h
index 087c20769256..4d6bc45df594 100644
--- a/trunk/include/asm-mips/pgtable-32.h
+++ b/trunk/include/asm-mips/pgtable-32.h
@@ -177,67 +177,48 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 	((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
 
 /*
- * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
+ * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
+ * into this range:
  */
-#define PTE_FILE_MAX_BITS	28
+#define PTE_FILE_MAX_BITS	27
 
-#define pte_to_pgoff(_pte)	((((_pte).pte >> 1 ) & 0x07) | \
-				 (((_pte).pte >> 2 ) & 0x38) | \
-				 (((_pte).pte >> 10) <<  6 ))
+#define pte_to_pgoff(_pte) \
+	((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
 
-#define pgoff_to_pte(off)	((pte_t) { (((off) & 0x07) << 1 ) | \
-					   (((off) & 0x38) << 2 ) | \
-					   (((off) >>  6 ) << 10) | \
-					   _PAGE_FILE })
+#define pgoff_to_pte(off) \
+	((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
 
 #else
 
 /* Swap entries must have VALID and GLOBAL bits cleared. */
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __swp_type(x)		(((x).val >> 2) & 0x1f)
-#define __swp_offset(x) 	 ((x).val >> 7)
-#define __swp_entry(type,offset)	\
-		((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
-#else
 #define __swp_type(x)		(((x).val >> 8) & 0x1f)
-#define __swp_offset(x) 	 ((x).val >> 13)
+#define __swp_offset(x)		((x).val >> 13)
 #define __swp_entry(type,offset)	\
-		((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+		((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 /*
- * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
+ * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
+ * into this range:
  */
-#define PTE_FILE_MAX_BITS	30
+#define PTE_FILE_MAX_BITS	27
 
-#define pte_to_pgoff(_pte)	((_pte).pte_high >> 2)
-#define pgoff_to_pte(off) 	((pte_t) { _PAGE_FILE, (off) << 2 })
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+	/* fixme */
+#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
+#define pgoff_to_pte(off) \
+	((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
 
 #else
-/*
- * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
- */
-#define PTE_FILE_MAX_BITS	28
-
-#define pte_to_pgoff(_pte)	((((_pte).pte >> 1) & 0x7) | \
-				 (((_pte).pte >> 2) & 0x8) | \
-				 (((_pte).pte >> 8) <<  4))
+#define pte_to_pgoff(_pte) \
+	((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
 
-#define pgoff_to_pte(off)	((pte_t) { (((off) & 0x7) << 1) | \
-					   (((off) & 0x8) << 2) | \
-					   (((off) >>  4) << 8) | \
-					   _PAGE_FILE })
+#define pgoff_to_pte(off) \
+	((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
 #endif
 
 #endif
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
-#define __swp_entry_to_pte(x)	((pte_t) { 0, (x).val })
-#else
 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)	((pte_t) { (x).val })
-#endif
 
 #endif /* _ASM_PGTABLE_32_H */
diff --git a/trunk/include/asm-mips/pgtable-64.h b/trunk/include/asm-mips/pgtable-64.h
index 2faf5c9ff127..82166b254b27 100644
--- a/trunk/include/asm-mips/pgtable-64.h
+++ b/trunk/include/asm-mips/pgtable-64.h
@@ -224,12 +224,15 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 #define __swp_entry_to_pte(x)	((pte_t) { (x).val })
 
 /*
- * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
- * make things easier, and only use the upper 56 bits for the page offset...
+ * Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset
+ * into this range:
  */
-#define PTE_FILE_MAX_BITS	56
+#define PTE_FILE_MAX_BITS	32
 
-#define pte_to_pgoff(_pte)	((_pte).pte >> 8)
-#define pgoff_to_pte(off)	((pte_t) { ((off) << 8) | _PAGE_FILE })
+#define pte_to_pgoff(_pte) \
+	((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
+
+#define pgoff_to_pte(off) \
+	((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
 
 #endif /* _ASM_PGTABLE_64_H */
diff --git a/trunk/include/asm-mips/pgtable.h b/trunk/include/asm-mips/pgtable.h
index d0af2a3b0152..f80fe75c7800 100644
--- a/trunk/include/asm-mips/pgtable.h
+++ b/trunk/include/asm-mips/pgtable.h
@@ -353,9 +353,8 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-	pte.pte_low  &= _PAGE_CHG_MASK;
-	pte.pte_high &= ~0x3f;
-	pte.pte_low  |= pgprot_val(newprot);
+	pte.pte_low &= _PAGE_CHG_MASK;
+	pte.pte_low |= pgprot_val(newprot);
 	pte.pte_high |= pgprot_val(newprot) & 0x3f;
 	return pte;
 }
diff --git a/trunk/include/asm-mips/smp.h b/trunk/include/asm-mips/smp.h
index e14e4b69de21..75c6fe7c2126 100644
--- a/trunk/include/asm-mips/smp.h
+++ b/trunk/include/asm-mips/smp.h
@@ -48,6 +48,7 @@ extern struct call_data_struct *call_data;
 #define SMP_CALL_FUNCTION	0x2
 
 extern cpumask_t phys_cpu_present_map;
+extern cpumask_t cpu_online_map;
 #define cpu_possible_map	phys_cpu_present_map
 
 extern cpumask_t cpu_callout_map;
@@ -85,9 +86,9 @@ extern void prom_init_secondary(void);
 extern void plat_smp_setup(void);
 
 /*
- * Called in smp_prepare_cpus.
+ * Called after init_IRQ but before __cpu_up.
  */
-extern void plat_prepare_cpus(unsigned int max_cpus);
+extern void prom_prepare_cpus(unsigned int max_cpus);
 
 /*
  * Last chance for the board code to finish SMP initialization before
diff --git a/trunk/include/asm-mips/sparsemem.h b/trunk/include/asm-mips/sparsemem.h
deleted file mode 100644
index 795ac6c23203..000000000000
--- a/trunk/include/asm-mips/sparsemem.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _MIPS_SPARSEMEM_H
-#define _MIPS_SPARSEMEM_H
-#ifdef CONFIG_SPARSEMEM
-
-/*
- * SECTION_SIZE_BITS		2^N: how big each section will be
- * MAX_PHYSMEM_BITS		2^N: how much memory we can have in that space
- */
-#define SECTION_SIZE_BITS       28
-#define MAX_PHYSMEM_BITS        35
-
-#endif /* CONFIG_SPARSEMEM */
-#endif /* _MIPS_SPARSEMEM_H */
-
diff --git a/trunk/net/ipv4/tcp_output.c b/trunk/net/ipv4/tcp_output.c
index 743016baa048..f33c9dddaa12 100644
--- a/trunk/net/ipv4/tcp_output.c
+++ b/trunk/net/ipv4/tcp_output.c
@@ -642,7 +642,7 @@ int tcp_fragment(struct sock *sk, struct sk_buff *skb, u32 len, unsigned int mss
  * eventually). The difference is that pulled data not copied, but
  * immediately discarded.
  */
-static unsigned char *__pskb_trim_head(struct sk_buff *skb, int len)
+static void __pskb_trim_head(struct sk_buff *skb, int len)
 {
 	int i, k, eat;
 
@@ -667,7 +667,6 @@ static unsigned char *__pskb_trim_head(struct sk_buff *skb, int len)
 	skb->tail = skb->data;
 	skb->data_len -= len;
 	skb->len = skb->data_len;
-	return skb->tail;
 }
 
 int tcp_trim_head(struct sock *sk, struct sk_buff *skb, u32 len)
@@ -676,12 +675,11 @@ int tcp_trim_head(struct sock *sk, struct sk_buff *skb, u32 len)
 	    pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
 		return -ENOMEM;
 
-	if (len <= skb_headlen(skb)) {
+	/* If len == headlen, we avoid __skb_pull to preserve alignment. */
+	if (unlikely(len < skb_headlen(skb)))
 		__skb_pull(skb, len);
-	} else {
-		if (__pskb_trim_head(skb, len-skb_headlen(skb)) == NULL)
-			return -ENOMEM;
-	}
+	else
+		__pskb_trim_head(skb, len - skb_headlen(skb));
 
 	TCP_SKB_CB(skb)->seq += len;
 	skb->ip_summed = CHECKSUM_HW;